From nobody Mon Jun 29 13:50:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2080C433EF for ; Wed, 9 Feb 2022 16:18:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236281AbiBIQRz (ORCPT ); Wed, 9 Feb 2022 11:17:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232050AbiBIQRt (ORCPT ); Wed, 9 Feb 2022 11:17:49 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3875AC061355 for ; Wed, 9 Feb 2022 08:17:52 -0800 (PST) Date: Wed, 09 Feb 2022 16:17:49 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1644423470; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MIAzogYAv6v+6hICEIrQlX4VcOOC/GW4tmJ2nBSpYHg=; b=rrIcW3a94AbAAGtf2iHrRM2oIK5LYLBIoMNGlY/QruGUfwo5xGBi9aywBcZ+2ZCx/1dsy5 uirpm685yYgMe3NOz8nuM3+mG3TlA6uAzLZoHNTU2B8rWLQCsuqJALc+iYGljVZ1ggZrvU QC5rWJAr1A0jlErQTuZ4eQWKZSPdxh/eLLaxaTCmozM3Zxg1DqXWoevBjiQ27MkqF9F/4j N81KHb3KxVOs8MKMi7qEM5PvH3LW+OXFxQxK/DEpd1vALWN06nzgbIoFYoa2z5Lqk4FvpO HD1DNfMJ6YFs8h7/0zAk1WPhpOPANp2x/hf2Gccpe4QvUMYvMfpGX1Z7cpyO+A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1644423470; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MIAzogYAv6v+6hICEIrQlX4VcOOC/GW4tmJ2nBSpYHg=; b=05bXof0fc38lSmJ2eCSx0PhbwZtvMsfTeP/hNd+2MLZYMutHLAi253uPIOR784KaQ7sLCy 4ZDFl2Bri317CAAw== From: "irqchip-bot for Alexandre Torgue" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/stm32-exti: Add STM32MP13 support Cc: Alexandre Torgue , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220202140005.860-3-alexandre.torgue@foss.st.com> References: <20220202140005.860-3-alexandre.torgue@foss.st.com> MIME-Version: 1.0 Message-ID: <164442346932.16921.10963525223069470489.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 04133bb1e710bc3d5532694999fbb3d0f1421724 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/04133bb1e710bc3d5532694999fbb3d0f1421724 Author: Alexandre Torgue AuthorDate: Wed, 02 Feb 2022 15:00:04 +01:00 Committer: Marc Zyngier CommitterDate: Wed, 09 Feb 2022 13:43:07=20 irqchip/stm32-exti: Add STM32MP13 support Enhance stm32-exti driver to support STM32MP13 SoC. This SoC uses the same hardware version than STM32MP15. Only EXTI line mapping is changed and following EXTI lines are supported: GPIO, RTC, I2C[1-5], UxART[1-8], USBH_EHCI, USBH_OHCI, USB_OTG, LPTIM[1-5], ETH[1-2]. Signed-off-by: Alexandre Torgue Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220202140005.860-3-alexandre.torgue@foss.= st.com --- drivers/irqchip/irq-stm32-exti.c | 50 +++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index b7cb2da..9d18f47 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -214,6 +214,48 @@ static const struct stm32_desc_irq stm32mp1_desc_irq[]= =3D { { .exti =3D 73, .irq_parent =3D 129, .chip =3D &stm32_exti_h_chip }, }; =20 +static const struct stm32_desc_irq stm32mp13_desc_irq[] =3D { + { .exti =3D 0, .irq_parent =3D 6, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 1, .irq_parent =3D 7, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 2, .irq_parent =3D 8, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 3, .irq_parent =3D 9, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 4, .irq_parent =3D 10, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 5, .irq_parent =3D 24, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 6, .irq_parent =3D 65, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 7, .irq_parent =3D 66, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 8, .irq_parent =3D 67, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 9, .irq_parent =3D 68, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 10, .irq_parent =3D 41, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 11, .irq_parent =3D 43, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 12, .irq_parent =3D 77, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 13, .irq_parent =3D 78, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 14, .irq_parent =3D 106, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 15, .irq_parent =3D 109, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 16, .irq_parent =3D 1, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 19, .irq_parent =3D 3, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 21, .irq_parent =3D 32, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 22, .irq_parent =3D 34, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 23, .irq_parent =3D 73, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 24, .irq_parent =3D 93, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 25, .irq_parent =3D 114, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 26, .irq_parent =3D 38, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 27, .irq_parent =3D 39, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 28, .irq_parent =3D 40, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 29, .irq_parent =3D 72, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 30, .irq_parent =3D 53, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 31, .irq_parent =3D 54, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 32, .irq_parent =3D 83, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 33, .irq_parent =3D 84, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 44, .irq_parent =3D 96, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 47, .irq_parent =3D 92, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 48, .irq_parent =3D 116, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 50, .irq_parent =3D 117, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 52, .irq_parent =3D 118, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 53, .irq_parent =3D 119, .chip =3D &stm32_exti_h_chip_direct = }, + { .exti =3D 68, .irq_parent =3D 63, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 70, .irq_parent =3D 98, .chip =3D &stm32_exti_h_chip_direct }, +}; + static const struct stm32_exti_drv_data stm32mp1_drv_data =3D { .exti_banks =3D stm32mp1_exti_banks, .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), @@ -221,6 +263,13 @@ static const struct stm32_exti_drv_data stm32mp1_drv_d= ata =3D { .irq_nr =3D ARRAY_SIZE(stm32mp1_desc_irq), }; =20 +static const struct stm32_exti_drv_data stm32mp13_drv_data =3D { + .exti_banks =3D stm32mp1_exti_banks, + .bank_nr =3D ARRAY_SIZE(stm32mp1_exti_banks), + .desc_irqs =3D stm32mp13_desc_irq, + .irq_nr =3D ARRAY_SIZE(stm32mp13_desc_irq), +}; + static const struct stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_= data, irq_hw_number_t hwirq) @@ -922,6 +971,7 @@ static int stm32_exti_probe(struct platform_device *pde= v) /* platform driver only for MP1 */ static const struct of_device_id stm32_exti_ids[] =3D { { .compatible =3D "st,stm32mp1-exti", .data =3D &stm32mp1_drv_data}, + { .compatible =3D "st,stm32mp13-exti", .data =3D &stm32mp13_drv_data}, {}, }; MODULE_DEVICE_TABLE(of, stm32_exti_ids);