From nobody Mon Jun 29 15:04:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25C58C433EF for ; Tue, 8 Feb 2022 15:36:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380740AbiBHPgl (ORCPT ); Tue, 8 Feb 2022 10:36:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377107AbiBHPgj (ORCPT ); Tue, 8 Feb 2022 10:36:39 -0500 X-Greylist: delayed 122 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 08 Feb 2022 07:36:38 PST Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BCCAC061576; Tue, 8 Feb 2022 07:36:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644334598; x=1675870598; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=40L17z1hVZaJzNlebR2WYgcAZBEqUhNi3RANKgIqJOs=; b=jKry3YfkdAPAsljgUAjf9ALAsE8ny82I9jnxne2nwInnCF3l95OSBSyD tbPcS0FGzZeCLRwSObKFgPUHLOMV0+up2PUko05Fcg5ToL6JB8M0KpBWU fQtAJpyK4PqPhRWlVz+KF2LlqPOwf7BXEhXAYlwN2miizwlB92p2VbFGi A=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 08 Feb 2022 07:34:35 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 07:34:34 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:34:34 -0800 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:34:30 -0800 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v2 1/3] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset Date: Tue, 8 Feb 2022 21:04:12 +0530 Message-ID: <1644334454-16719-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644334454-16719-1-git-send-email-quic_srivasam@quicinc.com> References: <1644334454-16719-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add AMP enable node and pinmux for primary and secondary I2S for SC7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 40 ++++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++= ++++ 2 files changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index d623d71..c7d6c46 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -436,6 +436,39 @@ qcom,drive-strength =3D <3>; }; }; +&pri_mi2s_data0 { + drive-strength =3D <6>; +}; + +&pri_mi2s_data1 { + drive-strength =3D <6>; +}; + +&pri_mi2s_mclk { + drive-strength =3D <6>; +}; + +&pri_mi2s_sclk { + drive-strength =3D <6>; +}; + +&pri_mi2s_ws { + drive-strength =3D <6>; +}; + +&sec_mi2s_data0 { + drive-strength =3D <6>; + bias-disable; +}; + +&sec_mi2s_sclk { + drive-strength =3D <6>; + bias-disable; +}; + +&sec_mi2s_ws { + drive-strength =3D <6>; +}; =20 &qspi_cs0 { bias-disable; @@ -491,6 +524,13 @@ }; =20 &tlmm { + amp_en: amp-en { + pins =3D "gpio63"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <2>; + }; + nvme_pwren: nvme-pwren { function =3D "gpio"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 937c2e0..76e73e9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3461,6 +3461,46 @@ }; }; =20 + pri_mi2s_data0: pri-mi2s-data0 { + pins =3D "gpio98"; + function =3D "mi2s0_data0"; + }; + + pri_mi2s_data1: pri-mi2s-data1 { + pins =3D "gpio99"; + function =3D "mi2s0_data1"; + }; + + pri_mi2s_mclk: pri-mi2s-mclk { + pins =3D "gpio96"; + function =3D "pri_mi2s"; + }; + + pri_mi2s_sclk: pri-mi2s-sclk { + pins =3D "gpio97"; + function =3D "mi2s0_sck"; + }; + + pri_mi2s_ws: pri-mi2s-ws { + pins =3D "gpio100"; + function =3D "mi2s0_ws"; + }; + + sec_mi2s_data0: sec-mi2s-data0 { + pins =3D "gpio107"; + function =3D "mi2s1_data0"; + }; + + sec_mi2s_sclk: sec-mi2s-sclk { + pins =3D "gpio106"; + function =3D "mi2s1_sck"; + }; + + sec_mi2s_ws: sec-mi2s-ws { + pins =3D "gpio108"; + function =3D "mi2s1_ws"; + }; + qup_uart8_cts: qup-uart8-cts { pins =3D "gpio32"; function =3D "qup10"; --=20 2.7.4 From nobody Mon Jun 29 15:04:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5014CC433EF for ; Tue, 8 Feb 2022 15:36:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380849AbiBHPgq (ORCPT ); Tue, 8 Feb 2022 10:36:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377107AbiBHPgm (ORCPT ); Tue, 8 Feb 2022 10:36:42 -0500 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E3D0C061578; Tue, 8 Feb 2022 07:36:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644334602; x=1675870602; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=PY0ZbX6uZ51k5F7k09YtpVBSHY3rCFpFxxgM1Cs4Qvw=; b=lwe+8XEhmLyNyFp82JMJ08x++hLOsKs25+OJtq2cY5jyJmeRW6ipXJMz GIBwA1vmvfZPjj0RRWaDzTpN1Z7WCvPqXTB/M8PZKpxtrHbD2NzhRRDf4 lGtO2NV210dNhr0vgLgFfiRlbKL2A1F/UIMHCcdDGmdJ6dA0vftJc3GUp g=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 08 Feb 2022 07:34:40 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 07:34:39 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:34:38 -0800 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:34:34 -0800 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v2 2/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node Date: Tue, 8 Feb 2022 21:04:13 +0530 Message-ID: <1644334454-16719-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644334454-16719-1-git-send-email-quic_srivasam@quicinc.com> References: <1644334454-16719-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add LPASS LPI pinctrl node required for Audio functionality on sc7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 150 +++++++++++++++++++++++++++= ++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index c7d6c46..4704a93 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -638,3 +638,153 @@ bias-pull-up; }; }; +&soc { + lpass_tlmm: pinctrl@33c0000 { + compatible =3D "qcom,sc7280-lpass-lpi-pinctrl"; + reg =3D <0 0x33c0000 0x0 0x20000>, + <0 0x3550000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 15>; + + #clock-cells =3D <1>; + + dmic01_active: dmic01-active-pins { + clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic01_sleep: dmic01-sleep-pins { + clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <2>; + pull-down; + input-enable; + }; + }; + + dmic23_active: dmic02-active-pins { + clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic23_sleep: dmic02-sleep-pins { + clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <2>; + pull-down; + input-enable; + }; + }; + + rx_swr_active: rx_swr-active-pins { + clk { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_sleep: rx_swr-sleep-pins { + clk { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + input-enable; + bias-pull-down; + }; + + data { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + input-enable; + bias-pull-down; + }; + }; + + tx_swr_active: tx_swr-active-pins { + clk { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + tx_swr_sleep: tx_swr-sleep-pins { + clk { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + input-enable; + bias-pull-down; + }; + + data { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + input-enable; + bias-bus-hold; + }; + }; + }; +}; --=20 2.7.4 From nobody Mon Jun 29 15:04:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22321C43217 for ; Tue, 8 Feb 2022 15:34:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1380496AbiBHPep (ORCPT ); Tue, 8 Feb 2022 10:34:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380405AbiBHPeo (ORCPT ); Tue, 8 Feb 2022 10:34:44 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7076C061576; Tue, 8 Feb 2022 07:34:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644334483; x=1675870483; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=tQYg4ns3pN6Cjly41q2OmwXQjFd76rsowbPhFUcjCls=; b=a4j309wnGsxZBpzgAu73ktRgXbDL0gPPhnnBuUsD6bSI6Th/9WGmMmn9 CsOtEj0pQ4bYH81n9+tr/ZB7i+FF/ohfBSsJ+3BjExhBwXzci73G1I5AG DoxXF5tf8SIrUrRoud8jGJsoRppksJypp3v0c319Cg8U0PcMLlIbt2wwc I=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 08 Feb 2022 07:34:43 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 07:34:44 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:34:42 -0800 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 8 Feb 2022 07:34:38 -0800 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v2 3/3] arm64: dts: qcom: sc7280: Add wcd9380 pinmux Date: Tue, 8 Feb 2022 21:04:14 +0530 Message-ID: <1644334454-16719-4-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644334454-16719-1-git-send-email-quic_srivasam@quicinc.com> References: <1644334454-16719-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinmux to reset wcd codec, conneceted on SC7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 4704a93..6b38fa1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -594,6 +594,21 @@ */ bias-pull-up; }; + + wcd938x_reset_active: wcd938x_reset_active { + pins =3D "gpio83"; + function =3D "gpio"; + drive-strength =3D <16>; + output-high; + }; + + wcd938x_reset_sleep: wcd938x_reset_sleep { + pins =3D "gpio83"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; }; =20 &sdc1_on { --=20 2.7.4