From nobody Mon Jun 29 18:40:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08DEDC433EF for ; Fri, 4 Feb 2022 04:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356981AbiBDEZv (ORCPT ); Thu, 3 Feb 2022 23:25:51 -0500 Received: from mx.socionext.com ([202.248.49.38]:58076 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356281AbiBDEZo (ORCPT ); Thu, 3 Feb 2022 23:25:44 -0500 Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 04 Feb 2022 13:25:43 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 371032083C4C; Fri, 4 Feb 2022 13:25:43 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 4 Feb 2022 13:25:43 +0900 Received: from plum.e01.socionext.com (unknown [10.212.243.119]) by kinkan2.css.socionext.com (Postfix) with ESMTP id 97587C1E23; Fri, 4 Feb 2022 13:25:42 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Masami Hiramatsu Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH v2 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Date: Fri, 4 Feb 2022 13:25:37 +0900 Message-Id: <1643948739-14889-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643948739-14889-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1643948739-14889-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update PCI endpoint binding document for UniPhier NX1 SoC. Add a compatible string, clock and reset lines for the SoC to the document. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- .../bindings/pci/socionext,uniphier-pcie-ep.yaml | 22 +++++++++++++++---= ---- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-= ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.= yaml index 179ab0858482..437e61618d06 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -20,7 +20,9 @@ allOf: =20 properties: compatible: - const: socionext,uniphier-pro5-pcie-ep + enum: + - socionext,uniphier-pro5-pcie-ep + - socionext,uniphier-nx1-pcie-ep =20 reg: minItems: 4 @@ -41,20 +43,26 @@ properties: - const: atu =20 clocks: + minItems: 1 maxItems: 2 =20 clock-names: - items: - - const: gio - - const: link + oneOf: + - items: # for Pro5 + - const: gio + - const: link + - const: link # for NX1 =20 resets: + minItems: 1 maxItems: 2 =20 reset-names: - items: - - const: gio - - const: link + oneOf: + - items: # for Pro5 + - const: gio + - const: link + - const: link # for NX1 =20 num-ib-windows: const: 16 --=20 2.7.4 From nobody Mon Jun 29 18:40:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0E77C4332F for ; Fri, 4 Feb 2022 04:25:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356963AbiBDEZs (ORCPT ); Thu, 3 Feb 2022 23:25:48 -0500 Received: from mx.socionext.com ([202.248.49.38]:57477 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245220AbiBDEZo (ORCPT ); Thu, 3 Feb 2022 23:25:44 -0500 Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 04 Feb 2022 13:25:43 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 3CD9C2006F53; Fri, 4 Feb 2022 13:25:43 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 4 Feb 2022 13:25:43 +0900 Received: from plum.e01.socionext.com (unknown [10.212.243.119]) by kinkan2.css.socionext.com (Postfix) with ESMTP id C5236C1E22; Fri, 4 Feb 2022 13:25:42 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Masami Hiramatsu Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH v2 2/3] PCI: uniphier-ep: Add support for non-legacy SoC Date: Fri, 4 Feb 2022 13:25:38 +0900 Message-Id: <1643948739-14889-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643948739-14889-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1643948739-14889-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define SoC data that includes pci_epc_features and boolean 'is_legacy' to distinguish between legacy SoC (ex. Pro5) and non-legacy SoC. Rename uniphier_pcie_init_ep() to uniphier_pcie_init_ep_legacy() for initializing PCIe controller implemented in legacy SoC, add new uniphier_pcie_init_ep() and uniphier_pcie_wait_ep() for non-legacy SoC in the same method as pcie-uniphier driver. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 124 ++++++++++++++++++++++= ---- 1 file changed, 106 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/co= ntroller/dwc/pcie-uniphier-ep.c index 69810c6b0d58..073bdf7fcee3 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,17 @@ #define PCL_RSTCTRL2 0x0024 #define PCL_RSTCTRL_PHY_RESET BIT(0) =20 +#define PCL_PINCTRL0 0x002c +#define PCL_PERST_PLDN_REGEN BIT(12) +#define PCL_PERST_NOE_REGEN BIT(11) +#define PCL_PERST_OUT_REGEN BIT(8) +#define PCL_PERST_PLDN_REGVAL BIT(4) +#define PCL_PERST_NOE_REGVAL BIT(3) +#define PCL_PERST_OUT_REGVAL BIT(0) + +#define PCL_PIPEMON 0x0044 +#define PCL_PCLK_ALIVE BIT(15) + #define PCL_MODE 0x8000 #define PCL_MODE_REGEN BIT(8) #define PCL_MODE_REGVAL BIT(0) @@ -51,6 +63,9 @@ #define PCL_APP_INTX 0x8074 #define PCL_APP_INTX_SYS_INT BIT(0) =20 +#define PCL_APP_PM0 0x8078 +#define PCL_SYS_AUX_PWR_DET BIT(8) + /* assertion time of INTx in usec */ #define PCL_INTX_WIDTH_USEC 30 =20 @@ -60,7 +75,12 @@ struct uniphier_pcie_ep_priv { struct clk *clk, *clk_gio; struct reset_control *rst, *rst_gio; struct phy *phy; - const struct pci_epc_features *features; + const struct uniphier_pcie_ep_soc_data *data; +}; + +struct uniphier_pcie_ep_soc_data { + bool is_legacy; + const struct pci_epc_features features; }; =20 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) @@ -91,7 +111,7 @@ static void uniphier_pcie_phy_reset(struct uniphier_pcie= _ep_priv *priv, writel(val, priv->base + PCL_RSTCTRL2); } =20 -static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv) +static void uniphier_pcie_init_ep_legacy(struct uniphier_pcie_ep_priv *pri= v) { u32 val; =20 @@ -116,6 +136,63 @@ static void uniphier_pcie_init_ep(struct uniphier_pcie= _ep_priv *priv) msleep(100); } =20 +static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv) +{ + u32 val; + + if (priv->data->is_legacy) { + uniphier_pcie_init_ep_legacy(priv); + return; + } + + /* set EP mode */ + val =3D readl(priv->base + PCL_MODE); + val |=3D PCL_MODE_REGEN | PCL_MODE_REGVAL; + writel(val, priv->base + PCL_MODE); + + /* use auxiliary power detection */ + val =3D readl(priv->base + PCL_APP_PM0); + val |=3D PCL_SYS_AUX_PWR_DET; + writel(val, priv->base + PCL_APP_PM0); + + /* assert PERST# */ + val =3D readl(priv->base + PCL_PINCTRL0); + val &=3D ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL + | PCL_PERST_PLDN_REGVAL); + val |=3D PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN + | PCL_PERST_PLDN_REGEN; + writel(val, priv->base + PCL_PINCTRL0); + + uniphier_pcie_ltssm_enable(priv, false); + + usleep_range(100000, 200000); + + /* deassert PERST# */ + val =3D readl(priv->base + PCL_PINCTRL0); + val |=3D PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN; + writel(val, priv->base + PCL_PINCTRL0); +} + +static int uniphier_pcie_wait_ep(struct uniphier_pcie_ep_priv *priv) +{ + u32 status; + int ret; + + if (priv->data->is_legacy) + return 0; + + /* wait PIPE clock */ + ret =3D readl_poll_timeout(priv->base + PCL_PIPEMON, status, + status & PCL_PCLK_ALIVE, 100000, 1000000); + if (ret) { + dev_err(priv->pci.dev, + "Failed to initialize controller in EP mode\n"); + return ret; + } + + return 0; +} + static int uniphier_pcie_start_link(struct dw_pcie *pci) { struct uniphier_pcie_ep_priv *priv =3D to_uniphier_pcie(pci); @@ -209,7 +286,7 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep) struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); struct uniphier_pcie_ep_priv *priv =3D to_uniphier_pcie(pci); =20 - return priv->features; + return &priv->data->features; } =20 static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops =3D { @@ -248,8 +325,14 @@ static int uniphier_pcie_ep_enable(struct uniphier_pci= e_ep_priv *priv) =20 uniphier_pcie_phy_reset(priv, false); =20 + ret =3D uniphier_pcie_wait_ep(priv); + if (ret) + goto out_phy_exit; + return 0; =20 +out_phy_exit: + phy_exit(priv->phy); out_rst_gio_assert: reset_control_assert(priv->rst_gio); out_rst_assert: @@ -277,8 +360,8 @@ static int uniphier_pcie_ep_probe(struct platform_devic= e *pdev) if (!priv) return -ENOMEM; =20 - priv->features =3D of_device_get_match_data(dev); - if (WARN_ON(!priv->features)) + priv->data =3D of_device_get_match_data(dev); + if (WARN_ON(!priv->data)) return -EINVAL; =20 priv->pci.dev =3D dev; @@ -288,13 +371,15 @@ static int uniphier_pcie_ep_probe(struct platform_dev= ice *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); =20 - priv->clk_gio =3D devm_clk_get(dev, "gio"); - if (IS_ERR(priv->clk_gio)) - return PTR_ERR(priv->clk_gio); + if (priv->data->is_legacy) { + priv->clk_gio =3D devm_clk_get(dev, "gio"); + if (IS_ERR(priv->clk_gio)) + return PTR_ERR(priv->clk_gio); =20 - priv->rst_gio =3D devm_reset_control_get_shared(dev, "gio"); - if (IS_ERR(priv->rst_gio)) - return PTR_ERR(priv->rst_gio); + priv->rst_gio =3D devm_reset_control_get_shared(dev, "gio"); + if (IS_ERR(priv->rst_gio)) + return PTR_ERR(priv->rst_gio); + } =20 priv->clk =3D devm_clk_get(dev, "link"); if (IS_ERR(priv->clk)) @@ -321,13 +406,16 @@ static int uniphier_pcie_ep_probe(struct platform_dev= ice *pdev) return dw_pcie_ep_init(&priv->pci.ep); } =20 -static const struct pci_epc_features uniphier_pro5_data =3D { - .linkup_notifier =3D false, - .msi_capable =3D true, - .msix_capable =3D false, - .align =3D 1 << 16, - .bar_fixed_64bit =3D BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4), - .reserved_bar =3D BIT(BAR_4), +static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data =3D { + .is_legacy =3D true, + .features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, + .align =3D 1 << 16, + .bar_fixed_64bit =3D BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4), + .reserved_bar =3D BIT(BAR_4), + }, }; =20 static const struct of_device_id uniphier_pcie_ep_match[] =3D { --=20 2.7.4 From nobody Mon Jun 29 18:40:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E19EC433EF for ; Fri, 4 Feb 2022 04:25:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231887AbiBDEZy (ORCPT ); Thu, 3 Feb 2022 23:25:54 -0500 Received: from mx.socionext.com ([202.248.49.38]:45580 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356935AbiBDEZp (ORCPT ); Thu, 3 Feb 2022 23:25:45 -0500 Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 04 Feb 2022 13:25:43 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 9ABD52006F53; Fri, 4 Feb 2022 13:25:43 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 4 Feb 2022 13:25:43 +0900 Received: from plum.e01.socionext.com (unknown [10.212.243.119]) by kinkan2.css.socionext.com (Postfix) with ESMTP id F3629C1E23; Fri, 4 Feb 2022 13:25:42 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Masami Hiramatsu Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH v2 3/3] PCI: uniphier-ep: Add compatible string and SoC-dependent data for NX1 SoC Date: Fri, 4 Feb 2022 13:25:39 +0900 Message-Id: <1643948739-14889-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643948739-14889-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1643948739-14889-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add basic support for UniPhier NX1 SoC as non-legacy SoC. This includes a compatible string and SoC-dependent data. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/co= ntroller/dwc/pcie-uniphier-ep.c index 073bdf7fcee3..6e522724f7ed 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -418,11 +418,26 @@ static const struct uniphier_pcie_ep_soc_data uniphie= r_pro5_data =3D { }, }; =20 +static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data =3D { + .is_legacy =3D false, + .features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, + .align =3D 1 << 12, + .bar_fixed_64bit =3D BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4), + }, +}; + static const struct of_device_id uniphier_pcie_ep_match[] =3D { { .compatible =3D "socionext,uniphier-pro5-pcie-ep", .data =3D &uniphier_pro5_data, }, + { + .compatible =3D "socionext,uniphier-nx1-pcie-ep", + .data =3D &uniphier_nx1_data, + }, { /* sentinel */ }, }; =20 --=20 2.7.4