From nobody Mon Jun 29 22:18:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10BE6C433F5 for ; Wed, 2 Feb 2022 10:53:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343561AbiBBKxT (ORCPT ); Wed, 2 Feb 2022 05:53:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245709AbiBBKxP (ORCPT ); Wed, 2 Feb 2022 05:53:15 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B91FC061714 for ; Wed, 2 Feb 2022 02:53:14 -0800 (PST) Date: Wed, 02 Feb 2022 10:53:12 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1643799193; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Q+pYdL8GgbTSFRMCnYz1Eu7aFcukfwsJ3mc97NcLmm0=; b=2urrzPaDlWxKahSjUkh1bsdYRfMUOK9PPHrIUhuwKzZPYlukr3WRgZHBCiid8Xrm3pff0g +jqxqqrQkKDkwOSl1CJo+A3WZfxTid3Zoz6sU2IZoAxDn8N01x5kGq6LWjT8506BXI35Zi j8XxJDPzojkEH520eNQbwSWoXX+91vp5N76GcqIkzwegT6Styo/3aXLTM0u2T0NtAAVpoo Y/xe6li5nFbBu+cCpaIcjmWJoaOqg9sC/otx+BzDt/Yj79yeujnmRl4fXWrzGWoSqF7o5d vM8onZKiA9XqqKgZYw3xhCLevAGBnAPa6juFi9E43WWE8IjoRWEm8DKKSe6R/g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1643799193; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Q+pYdL8GgbTSFRMCnYz1Eu7aFcukfwsJ3mc97NcLmm0=; b=OWZ8YBjzzOlpFPOC1aVBdYN+GGzdH7CxxfZKgcbabUlv7PmfUZV95acmqLmUd7wQ6p5pAr 56rCSu5/rVhUAkCA== From: "irqchip-bot for Guo Ren" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-fixes] dt-bindings: update riscv plic compatible string Cc: Guo Ren , Anup Patel , Heiko Stuebner , Rob Herring , Rob Herring , Palmer Dabbelt , Samuel Holland , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220130135634.1213301-2-guoren@kernel.org> References: <20220130135634.1213301-2-guoren@kernel.org> MIME-Version: 1.0 Message-ID: <164379919219.16921.17083588550151120882.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-fixes branch of i= rqchip: Commit-ID: 321a8be37e1a93cefeae990107533142c8515933 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/321a8be37e1a93cefeae990107533142c8515933 Author: Guo Ren AuthorDate: Sun, 30 Jan 2022 21:56:33 +08:00 Committer: Marc Zyngier CommitterDate: Wed, 02 Feb 2022 10:48:50=20 dt-bindings: update riscv plic compatible string Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core. Signed-off-by: Guo Ren Cc: Anup Patel Cc: Heiko Stuebner Cc: Rob Herring Cc: Rob Herring Cc: Palmer Dabbelt Cc: Samuel Holland Reviewed-by: Rob Herring Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220130135634.1213301-2-guoren@kernel.org --- Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.y= aml | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 0dfa6b2..27092c6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -35,6 +35,10 @@ description: contains a specific memory layout, which is documented in chapter 8 of t= he SiFive U5 Coreplex Series Manual . =20 + The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the + T-HEAD PLIC implementation requires setting a delegation bit to allow ac= cess + from S-mode. So add thead,c900-plic to distinguish them. + maintainers: - Sagar Kadam - Paul Walmsley @@ -42,12 +46,17 @@ maintainers: =20 properties: compatible: - items: - - enum: - - sifive,fu540-c000-plic - - starfive,jh7100-plic - - canaan,k210-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-plic + - starfive,jh7100-plic + - canaan,k210-plic + - const: sifive,plic-1.0.0 + - items: + - enum: + - allwinner,sun20i-d1-plic + - const: thead,c900-plic =20 reg: maxItems: 1