From nobody Sun Sep 22 10:33:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDAB6C433EF for ; Thu, 27 Jan 2022 11:43:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240668AbiA0LnL (ORCPT ); Thu, 27 Jan 2022 06:43:11 -0500 Received: from mailgw01.mediatek.com ([60.244.123.138]:33306 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S240666AbiA0LnK (ORCPT ); Thu, 27 Jan 2022 06:43:10 -0500 X-UUID: a8193240ab8547b0a76e0344327fdd2b-20220127 X-UUID: a8193240ab8547b0a76e0344327fdd2b-20220127 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 410029040; Thu, 27 Jan 2022 19:43:05 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 27 Jan 2022 19:43:04 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 Jan 2022 19:43:03 +0800 From: To: , , , , CC: , , , , , , xinlei lee Subject: [v1,1/3] dt-bindings: display: mediatek: dsi: add documentation for MT8186 SoC Date: Thu, 27 Jan 2022 19:42:51 +0800 Message-ID: <1643283773-7081-2-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1643283773-7081-1-git-send-email-xinlei.lee@mediatek.com> References: <1643283773-7081-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: xinlei lee Add binding documentation for the MT8186 SoC. Signed-off-by: Xinlei Lee --- Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ds= i.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index 36b0145..c82b8b2 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. =20 Required properties: - compatible: "mediatek,-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. +- the supported chips are mt2701, mt7623, mt8167, mt8173, mt8183 and mt818= 6. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks --=20 2.6.4