From nobody Tue Jun 30 09:25:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E3F5C433EF for ; Thu, 20 Jan 2022 17:28:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230351AbiATR2Z (ORCPT ); Thu, 20 Jan 2022 12:28:25 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:2816 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232481AbiATR07 (ORCPT ); Thu, 20 Jan 2022 12:26:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1642699619; x=1674235619; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=6jInWTX408P7RecMOrWiYnkPUBDk2GOLJu9WeLAMFsw=; b=wjGkbc5kFy+POKUOQt4Zg/ZdOpwspKx8b4AmA3hSU2P43ZeDHR7ih/pV SImeuwOykIpiH3GwFH1MNSV1qb+AQ4d3uovLHXPxTtFVMvTq8ggU8SJH8 sXFcnnKwEVWoB758qWX2KEMLLUVLdOL1pugr9qQzRtjYnlZvp45v8Zhd/ 0=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 20 Jan 2022 09:26:59 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Jan 2022 09:26:57 -0800 X-QCInternal: smtphost Received: from c-sbhanu-linux.qualcomm.com ([10.242.50.201]) by ironmsg01-blr.qualcomm.com with ESMTP; 20 Jan 2022 22:56:33 +0530 Received: by c-sbhanu-linux.qualcomm.com (Postfix, from userid 2344807) id BA66F538E; Thu, 20 Jan 2022 22:56:31 +0530 (IST) From: Shaik Sajida Bhanu To: adrian.hunter@intel.com, quic_asutoshd@quicinc.com, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: stummala@codeaurora.org, vbadigan@codeaurora.org, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, sartgarg@codeaurora.org, nitirawa@codeaurora.org, sayalil@codeaurora.org, Shaik Sajida Bhanu , Liangliang Lu , "Bao D . Nguyen" Subject: [PATCH V3 1/4] mmc: sdhci: Capture eMMC and SD card errors Date: Thu, 20 Jan 2022 22:56:19 +0530 Message-Id: <1642699582-14785-2-git-send-email-quic_c_sbhanu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642699582-14785-1-git-send-email-quic_c_sbhanu@quicinc.com> References: <1642699582-14785-1-git-send-email-quic_c_sbhanu@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add changes to capture eMMC and SD card errors. This is useful for debug and testing. Signed-off-by: Shaik Sajida Bhanu Signed-off-by: Liangliang Lu Signed-off-by: Sayali Lokhande Signed-off-by: Bao D. Nguyen --- drivers/mmc/host/sdhci-msm.c | 3 ++ drivers/mmc/host/sdhci.c | 72 ++++++++++++++++++++++++++++++++++++----= ---- include/linux/mmc/host.h | 31 +++++++++++++++++++ 3 files changed, 94 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 50c71e0..309eb7b 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -128,6 +128,8 @@ =20 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 =20 +#define MSM_MMC_ERR_STATS_ENABLE 1 + /* Timeout value to avoid infinite waiting for pwr_irq */ #define MSM_PWR_IRQ_TIMEOUT_MS 5000 =20 @@ -2734,6 +2736,7 @@ static int sdhci_msm_probe(struct platform_device *pd= ev) if (ret) goto pm_runtime_disable; =20 + host->mmc->err_stats_enabled =3D MSM_MMC_ERR_STATS_ENABLE; pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); =20 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 07c6da1..74b356e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -113,6 +113,8 @@ void sdhci_dumpregs(struct sdhci_host *host) if (host->ops->dump_vendor_regs) host->ops->dump_vendor_regs(host); =20 + if (host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_enable(host->mmc); SDHCI_DUMP("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"= ); } EXPORT_SYMBOL_GPL(sdhci_dumpregs); @@ -3159,6 +3161,8 @@ static void sdhci_timeout_timer(struct timer_list *t) spin_lock_irqsave(&host->lock, flags); =20 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_REQ_TIMEOUT); pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); @@ -3181,6 +3185,8 @@ static void sdhci_timeout_data_timer(struct timer_lis= t *t) =20 if (host->data || host->data_cmd || (host->cmd && sdhci_data_line_cmd(host->cmd))) { + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_REQ_TIMEOUT); pr_err("%s: Timeout waiting for hardware interrupt.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); @@ -3240,11 +3246,18 @@ static void sdhci_cmd_irq(struct sdhci_host *host, = u32 intmask, u32 *intmask_p) =20 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { - if (intmask & SDHCI_INT_TIMEOUT) + if (intmask & SDHCI_INT_TIMEOUT) { host->cmd->error =3D -ETIMEDOUT; - else + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_CMD_TIMEOUT); + } else { host->cmd->error =3D -EILSEQ; - + if (host->cmd->opcode !=3D MMC_SEND_TUNING_BLOCK || + host->cmd->opcode !=3D MMC_SEND_TUNING_BLOCK_HS200) { + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_CMD_CRC); + } + } /* Treat data command CRC error the same as data CRC error */ if (host->cmd->data && (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) =3D=3D @@ -3265,6 +3278,8 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u3= 2 intmask, u32 *intmask_p) int err =3D (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? -ETIMEDOUT : -EILSEQ; + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_AUTO_CMD); =20 if (sdhci_auto_cmd23(host, mrq)) { mrq->sbc->error =3D err; @@ -3342,6 +3357,8 @@ static void sdhci_data_irq(struct sdhci_host *host, u= 32 intmask) if (intmask & SDHCI_INT_DATA_TIMEOUT) { host->data_cmd =3D NULL; data_cmd->error =3D -ETIMEDOUT; + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_CMD_TIMEOUT); __sdhci_finish_mrq(host, data_cmd->mrq); return; } @@ -3375,18 +3392,29 @@ static void sdhci_data_irq(struct sdhci_host *host,= u32 intmask) return; } =20 - if (intmask & SDHCI_INT_DATA_TIMEOUT) + if (intmask & SDHCI_INT_DATA_TIMEOUT) { host->data->error =3D -ETIMEDOUT; + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_DAT_TIMEOUT); + } else if (intmask & SDHCI_INT_DATA_END_BIT) host->data->error =3D -EILSEQ; else if ((intmask & SDHCI_INT_DATA_CRC) && SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) - !=3D MMC_BUS_TEST_R) + !=3D MMC_BUS_TEST_R) { host->data->error =3D -EILSEQ; + if (host->cmd->opcode !=3D MMC_SEND_TUNING_BLOCK || + host->cmd->opcode !=3D MMC_SEND_TUNING_BLOCK_HS200) { + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_DAT_CRC); + } + } else if (intmask & SDHCI_INT_ADMA_ERROR) { pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc), intmask); sdhci_adma_show_error(host); + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_ADMA); host->data->error =3D -EIO; if (host->ops->adma_workaround) host->ops->adma_workaround(host, intmask); @@ -3905,20 +3933,40 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 int= mask, int *cmd_error, if (!host->cqe_on) return false; =20 - if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) + if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) { *cmd_error =3D -EILSEQ; - else if (intmask & SDHCI_INT_TIMEOUT) + if (intmask & SDHCI_INT_CRC) { + if (host->cmd->opcode !=3D MMC_SEND_TUNING_BLOCK || + host->cmd->opcode !=3D MMC_SEND_TUNING_BLOCK_HS200) { + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_CMD_CRC); + } + } + } else if (intmask & SDHCI_INT_TIMEOUT) { *cmd_error =3D -ETIMEDOUT; - else + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_CMD_TIMEOUT); + } else *cmd_error =3D 0; =20 - if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) + if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) { *data_error =3D -EILSEQ; - else if (intmask & SDHCI_INT_DATA_TIMEOUT) + if (intmask & SDHCI_INT_DATA_CRC) { + if (host->cmd->opcode !=3D MMC_SEND_TUNING_BLOCK || + host->cmd->opcode !=3D MMC_SEND_TUNING_BLOCK_HS200) { + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_DAT_CRC); + } + } + } else if (intmask & SDHCI_INT_DATA_TIMEOUT) { *data_error =3D -ETIMEDOUT; - else if (intmask & SDHCI_INT_ADMA_ERROR) + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_DAT_TIMEOUT); + } else if (intmask & SDHCI_INT_ADMA_ERROR) { *data_error =3D -EIO; - else + if (host->mmc && host->mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(host->mmc, MMC_ERR_ADMA); + } else *data_error =3D 0; =20 /* Clear selected interrupts. */ diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 7afb57c..883b50b 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -93,6 +93,23 @@ struct mmc_clk_phase_map { =20 struct mmc_host; =20 +enum mmc_err_stat { + MMC_ERR_CMD_TIMEOUT, + MMC_ERR_CMD_CRC, + MMC_ERR_DAT_TIMEOUT, + MMC_ERR_DAT_CRC, + MMC_ERR_AUTO_CMD, + MMC_ERR_ADMA, + MMC_ERR_TUNING, + MMC_ERR_CMDQ_RED, + MMC_ERR_CMDQ_GCE, + MMC_ERR_CMDQ_ICCE, + MMC_ERR_REQ_TIMEOUT, + MMC_ERR_CMDQ_REQ_TIMEOUT, + MMC_ERR_ICE_CFG, + MMC_ERR_MAX, +}; + struct mmc_host_ops { /* * It is optional for the host to implement pre_req and post_req in @@ -500,6 +517,9 @@ struct mmc_host { =20 /* Host Software Queue support */ bool hsq_enabled; + u32 err_stats[MMC_ERR_MAX]; + bool err_stats_enabled; + bool err_state; =20 unsigned long private[] ____cacheline_aligned; }; @@ -635,6 +655,17 @@ static inline enum dma_data_direction mmc_get_dma_dir(= struct mmc_data *data) return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE; } =20 +static inline void mmc_debugfs_err_stats_enable(struct mmc_host *mmc) +{ + mmc->err_state =3D true; +} + +static inline void mmc_debugfs_err_stats_inc(struct mmc_host *mmc, + enum mmc_err_stat stat) { + + mmc->err_stats[stat] +=3D 1; +} + int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); int mmc_send_abort_tuning(struct mmc_host *host, u32 opcode); int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd); --=20 QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member=20 of Code Aurora Forum, hosted by The Linux Foundation From nobody Tue Jun 30 09:25:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F07CC433FE for ; Thu, 20 Jan 2022 17:28:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230140AbiATR2V (ORCPT ); Thu, 20 Jan 2022 12:28:21 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:38887 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346833AbiATR05 (ORCPT ); Thu, 20 Jan 2022 12:26:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1642699617; x=1674235617; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=2FIjShg5baSboHk5Y596ymu0qrv2AoIjmxzwRiyXO74=; b=rVis5IPdzyu6Q5vtTGNkx5tHaYnyEjsFzv3OOV1co4BOYbAxK4bjLdIN aIPdfvx+OxVwJo0uHWyKc5SefJqVzCKWJhrrmvQxH4qWuK5NKGgBEilOQ +embhBIE2kFKhKJ2t0O1Te8xYBM9CX+6G7+MNkLNJhlFuR2qHAxlvh5S+ 0=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 20 Jan 2022 09:26:57 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Jan 2022 09:26:55 -0800 X-QCInternal: smtphost Received: from c-sbhanu-linux.qualcomm.com ([10.242.50.201]) by ironmsg01-blr.qualcomm.com with ESMTP; 20 Jan 2022 22:56:35 +0530 Received: by c-sbhanu-linux.qualcomm.com (Postfix, from userid 2344807) id 4EEE6538E; Thu, 20 Jan 2022 22:56:34 +0530 (IST) From: Shaik Sajida Bhanu To: adrian.hunter@intel.com, quic_asutoshd@quicinc.com, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: stummala@codeaurora.org, vbadigan@codeaurora.org, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, sartgarg@codeaurora.org, nitirawa@codeaurora.org, sayalil@codeaurora.org, Shaik Sajida Bhanu , Liangliang Lu , "Bao D . Nguyen" Subject: [PATCH V3 2/4] mmc: debugfs: Add debug fs entry for mmc driver Date: Thu, 20 Jan 2022 22:56:20 +0530 Message-Id: <1642699582-14785-3-git-send-email-quic_c_sbhanu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642699582-14785-1-git-send-email-quic_c_sbhanu@quicinc.com> References: <1642699582-14785-1-git-send-email-quic_c_sbhanu@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add debug fs entry to query eMMC and SD card errors statistics Signed-off-by: Shaik Sajida Bhanu Signed-off-by: Liangliang Lu Signed-off-by: Sayali Lokhande Signed-off-by: Bao D. Nguyen --- drivers/mmc/core/debugfs.c | 81 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 81 insertions(+) diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c index 3fdbc80..f4cb594 100644 --- a/drivers/mmc/core/debugfs.c +++ b/drivers/mmc/core/debugfs.c @@ -223,6 +223,82 @@ static int mmc_clock_opt_set(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE(mmc_clock_fops, mmc_clock_opt_get, mmc_clock_opt_= set, "%llu\n"); =20 +static int mmc_err_state_get(void *data, u64 *val) +{ + struct mmc_host *host =3D data; + + if (!host) + return -EINVAL; + + *val =3D host->err_state ? 1 : 0; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(mmc_err_state, mmc_err_state_get, NULL, "%llu\n"); + +static int mmc_err_stats_show(struct seq_file *file, void *data) +{ + struct mmc_host *host =3D (struct mmc_host *)file->private; + const char *desc[MMC_ERR_MAX] =3D { + [MMC_ERR_CMD_TIMEOUT] =3D "Command Timeout Occurred", + [MMC_ERR_CMD_CRC] =3D "Command CRC Errors Occurred", + [MMC_ERR_DAT_TIMEOUT] =3D "Data Timeout Occurred", + [MMC_ERR_DAT_CRC] =3D "Data CRC Errors Occurred", + [MMC_ERR_AUTO_CMD] =3D "Auto-Cmd Error Occurred", + [MMC_ERR_ADMA] =3D "ADMA Error Occurred", + [MMC_ERR_TUNING] =3D "Tuning Error Occurred", + [MMC_ERR_CMDQ_RED] =3D "CMDQ RED Errors", + [MMC_ERR_CMDQ_GCE] =3D "CMDQ GCE Errors", + [MMC_ERR_CMDQ_ICCE] =3D "CMDQ ICCE Errors", + [MMC_ERR_REQ_TIMEOUT] =3D "Request Timedout", + [MMC_ERR_CMDQ_REQ_TIMEOUT] =3D "CMDQ Request Timedout", + [MMC_ERR_ICE_CFG] =3D "ICE Config Errors", + }; + int i; + + if (!host) + return -EINVAL; + + if (!host->err_stats_enabled) { + seq_printf(file, "Not supported by driver\n"); + return 0; + } + + for (i =3D 0; i < MMC_ERR_MAX; i++) { + if (desc[i]) + seq_printf(file, "# %s:\t %d\n", + desc[i], host->err_stats[i]); + } + + return 0; +} + +static int mmc_err_stats_open(struct inode *inode, struct file *file) +{ + return single_open(file, mmc_err_stats_show, inode->i_private); +} + +static ssize_t mmc_err_stats_write(struct file *filp, const char __user *u= buf, + size_t cnt, loff_t *ppos) +{ + struct mmc_host *host =3D filp->f_mapping->host->i_private; + + if (!host) + return -EINVAL; + + pr_debug("%s: Resetting MMC error statistics\n", __func__); + memset(host->err_stats, 0, sizeof(host->err_stats)); + + return cnt; +} + +static const struct file_operations mmc_err_stats_fops =3D { + .open =3D mmc_err_stats_open, + .read =3D seq_read, + .write =3D mmc_err_stats_write, +}; + void mmc_add_host_debugfs(struct mmc_host *host) { struct dentry *root; @@ -236,6 +312,11 @@ void mmc_add_host_debugfs(struct mmc_host *host) debugfs_create_file_unsafe("clock", S_IRUSR | S_IWUSR, root, host, &mmc_clock_fops); =20 + debugfs_create_file("err_state", 0600, root, host, + &mmc_err_state); + debugfs_create_file("err_stats", 0600, root, host, + &mmc_err_stats_fops); + #ifdef CONFIG_FAIL_MMC_REQUEST if (fail_request) setup_fault_attr(&fail_default_attr, fail_request); --=20 QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member=20 of Code Aurora Forum, hosted by The Linux Foundation From nobody Tue Jun 30 09:25:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7425CC28CF5 for ; Thu, 20 Jan 2022 17:28:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229955AbiATR2S (ORCPT ); Thu, 20 Jan 2022 12:28:18 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:48739 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231523AbiATR05 (ORCPT ); Thu, 20 Jan 2022 12:26:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1642699617; x=1674235617; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=4daRwd6XUkVJ25mEal3fAjXhPYFJ0f4AY8G1bpkWBSM=; b=KcAeSXflC1LpyjzOcOILgOH6jl0AVU1UBrI5Oo7usXh+XtA4U4MnCD2K njEa1/ApIsoXhvG6dieJ+PRdMZWOPP0HeeVgj5jAjaq/0ZmTMqljvMBVo owdX9jAUC8N2r+OYfdVZ7QTSsT/laF8Ws96f5xZP8CowQxav0TkLhU8Wt I=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 20 Jan 2022 09:26:57 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Jan 2022 09:26:55 -0800 X-QCInternal: smtphost Received: from c-sbhanu-linux.qualcomm.com ([10.242.50.201]) by ironmsg01-blr.qualcomm.com with ESMTP; 20 Jan 2022 22:56:39 +0530 Received: by c-sbhanu-linux.qualcomm.com (Postfix, from userid 2344807) id A7018538E; Thu, 20 Jan 2022 22:56:37 +0530 (IST) From: Shaik Sajida Bhanu To: adrian.hunter@intel.com, quic_asutoshd@quicinc.com, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: stummala@codeaurora.org, vbadigan@codeaurora.org, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, sartgarg@codeaurora.org, nitirawa@codeaurora.org, sayalil@codeaurora.org, Shaik Sajida Bhanu , Liangliang Lu , "Bao D . Nguyen" Subject: [PATCH V3 3/4] mmc: core: Capture eMMC and SD card errors Date: Thu, 20 Jan 2022 22:56:21 +0530 Message-Id: <1642699582-14785-4-git-send-email-quic_c_sbhanu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642699582-14785-1-git-send-email-quic_c_sbhanu@quicinc.com> References: <1642699582-14785-1-git-send-email-quic_c_sbhanu@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add changes to capture eMMC and SD card errors. This is useful for debug and testing. Signed-off-by: Shaik Sajida Bhanu Signed-off-by: Liangliang Lu Signed-off-by: Sayali Lokhande Signed-off-by: Bao D. Nguyen Signed-off-by: Ram Prakash Gupta --- drivers/mmc/core/core.c | 8 ++++++++ drivers/mmc/core/queue.c | 3 +++ 2 files changed, 11 insertions(+) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 368f104..c586d69 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -2242,6 +2242,14 @@ void mmc_rescan(struct work_struct *work) if (freqs[i] <=3D host->f_min) break; } + + /* + * Ignore the command timeout errors observed during + * the card init as those are excepted. + */ + + if (host && host->err_stats_enabled) + host->err_stats[MMC_ERR_CMD_TIMEOUT] =3D 0; mmc_release_host(host); =20 out: diff --git a/drivers/mmc/core/queue.c b/drivers/mmc/core/queue.c index c69b2d9..7dc9dfb 100644 --- a/drivers/mmc/core/queue.c +++ b/drivers/mmc/core/queue.c @@ -100,6 +100,9 @@ static enum blk_eh_timer_return mmc_cqe_timed_out(struc= t request *req) enum mmc_issue_type issue_type =3D mmc_issue_type(mq, req); bool recovery_needed =3D false; =20 + if (host->err_stats_enabled) + mmc_debugfs_err_stats_inc(host, MMC_ERR_CMDQ_REQ_TIMEOUT); + switch (issue_type) { case MMC_ISSUE_ASYNC: case MMC_ISSUE_DCMD: --=20 QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member=20 of Code Aurora Forum, hosted by The Linux Foundation From nobody Tue Jun 30 09:25:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF0C0C41535 for ; Thu, 20 Jan 2022 17:28:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233525AbiATR2R (ORCPT ); Thu, 20 Jan 2022 12:28:17 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:38887 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346829AbiATR0z (ORCPT ); Thu, 20 Jan 2022 12:26:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1642699615; x=1674235615; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=WKv6tCtQgSCkfw+0HJkKanv62ISYhKm0cbdrYhfgvT0=; b=xutkIUzWDwKZOkA7ynExj+Yx6XnT9kLFC8OJDxiyqCktOhVg5trAPp9e ThlwgSBkNQAJXNjvyOlms6NVUGUh5gT3mt9t51SeJf+Y2rRI7mt9tTmXM ukEg/hI9IxnVtdCzsoHyNgSyPS5yu9WhcGEAiK5PfvjzC7Of6Opz1FLhc A=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 20 Jan 2022 09:26:55 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Jan 2022 09:26:53 -0800 X-QCInternal: smtphost Received: from c-sbhanu-linux.qualcomm.com ([10.242.50.201]) by ironmsg01-blr.qualcomm.com with ESMTP; 20 Jan 2022 22:56:41 +0530 Received: by c-sbhanu-linux.qualcomm.com (Postfix, from userid 2344807) id 786FB538E; Thu, 20 Jan 2022 22:56:39 +0530 (IST) From: Shaik Sajida Bhanu To: adrian.hunter@intel.com, quic_asutoshd@quicinc.com, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: stummala@codeaurora.org, vbadigan@codeaurora.org, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, sartgarg@codeaurora.org, nitirawa@codeaurora.org, sayalil@codeaurora.org, Shaik Sajida Bhanu , Liangliang Lu , "Bao D . Nguyen" Subject: [PATCH V3 4/4] mmc: cqhci: Capture eMMC and SD card errors Date: Thu, 20 Jan 2022 22:56:22 +0530 Message-Id: <1642699582-14785-5-git-send-email-quic_c_sbhanu@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642699582-14785-1-git-send-email-quic_c_sbhanu@quicinc.com> References: <1642699582-14785-1-git-send-email-quic_c_sbhanu@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add changes to capture eMMC and SD card errors. This is useful for debug and testing. Signed-off-by: Shaik Sajida Bhanu Signed-off-by: Liangliang Lu Signed-off-by: Sayali Lokhande Signed-off-by: Bao D. Nguyen Signed-off-by: Ram Prakash Gupta --- drivers/mmc/host/cqhci-core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c index b0d30c3..2908d30 100644 --- a/drivers/mmc/host/cqhci-core.c +++ b/drivers/mmc/host/cqhci-core.c @@ -822,8 +822,15 @@ irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmas= k, int cmd_error, pr_debug("%s: cqhci: IRQ status: 0x%08x\n", mmc_hostname(mmc), status); =20 if ((status & (CQHCI_IS_RED | CQHCI_IS_GCE | CQHCI_IS_ICCE)) || - cmd_error || data_error) + cmd_error || data_error) { + if ((status & CQHCI_IS_RED) && mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(mmc, MMC_ERR_CMDQ_RED); + if ((status & CQHCI_IS_GCE) && (mmc->err_stats_enabled)) + mmc_debugfs_err_stats_inc(mmc, MMC_ERR_CMDQ_GCE); + if ((status & CQHCI_IS_ICCE) && mmc->err_stats_enabled) + mmc_debugfs_err_stats_inc(mmc, MMC_ERR_CMDQ_ICCE); cqhci_error_irq(mmc, status, cmd_error, data_error); + } =20 if (status & CQHCI_IS_TCC) { /* read TCN and complete the request */ --=20 QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member=20 of Code Aurora Forum, hosted by The Linux Foundation