From nobody Tue Jun 30 20:12:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C73FC433EF for ; Mon, 10 Jan 2022 12:58:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235153AbiAJM6Q (ORCPT ); Mon, 10 Jan 2022 07:58:16 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:18076 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343536AbiAJM4J (ORCPT ); Mon, 10 Jan 2022 07:56:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1641819369; x=1673355369; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=851dCihNv0ZUDPuYNHdZbMaYmXs4Oons/vrRaL0TMEc=; b=VxDc8AKjRe7gV7dDhQcdiL5H+5qjcyc78X8ZxFNqhUad1KCJbJW1a7Gc Dz0U2sbSaP5n6Lq6q3svqmFbJ7KM41368RgXHLRAbQtPBe2OUm+rsPvIR K/1LjkqTp+GkWB0orjxYw/6+UkYSLhO9nsBRPZVMeajfN5UI1V6NmO1Is A=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 10 Jan 2022 04:56:08 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Jan 2022 04:56:06 -0800 X-QCInternal: smtphost Received: from rajeevny-linux.qualcomm.com ([10.204.66.121]) by ironmsg02-blr.qualcomm.com with ESMTP; 10 Jan 2022 18:25:46 +0530 Received: by rajeevny-linux.qualcomm.com (Postfix, from userid 2363605) id 34D79219EF; Mon, 10 Jan 2022 18:25:45 +0530 (IST) From: Rajeev Nandan To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Rajeev Nandan , linux-kernel@vger.kernel.org, sean@poorly.run, robdclark@gmail.com, robh+dt@kernel.org, robh@kernel.org, quic_abhinavk@quicinc.com, quic_kalyant@quicinc.com, quic_mkrishn@quicinc.com, jonathan@marek.ca, dmitry.baryshkov@linaro.org, airlied@linux.ie, daniel@ffwll.ch, swboyd@chromium.org Subject: [v2 1/3] dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties Date: Mon, 10 Jan 2022 18:25:35 +0530 Message-Id: <1641819337-17037-2-git-send-email-quic_rajeevny@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1641819337-17037-1-git-send-email-quic_rajeevny@quicinc.com> References: <1641819337-17037-1-git-send-email-quic_rajeevny@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In most cases, the default values of DSI PHY tuning registers should be sufficient as they are fully optimized. However, in some cases where extreme board parasitics cause the eye shape to degrade, the override bits can be used to improve the signal quality. The general guidelines for DSI PHY tuning include: - High and moderate data rates may benefit from the drive strength and drive level tuning. - Drive strength tuning will affect the output impedance and may be used for matching optimization. - Drive level tuning will affect the output levels without affecting the impedance. The clock and data lanes have a calibration circuitry feature. The drive strength tuning can be done by adjusting rescode offset for hstop/hsbot, and the drive level tuning can be done by adjusting the LDO output level for the HSTX drive. Signed-off-by: Rajeev Nandan --- Changes in v2: - More details in the commit text (Stephen Boyd) - Use human understandable values (Stephen Boyd, Dmitry Baryshkov) - Do not take values that are going to be unused (Dmitry Baryshkov) .../bindings/display/msm/dsi-phy-10nm.yaml | 33 ++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yam= l b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml index 4399715..d0eb8f6 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -35,6 +35,35 @@ properties: Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target =20 + phy-rescode-offset-top: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 5 + maxItems: 5 + description: + Integer array of offset for pull-up legs rescode for all five lanes. + To offset the drive strength from the calibrated value in an increas= ing + or decreasing manner, use 6 bit two=E2=80=99s complement values. + + phy-rescode-offset-bot: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 5 + maxItems: 5 + description: + Integer array of offset for pull-down legs rescode for all five lane= s. + To offset the drive strength from the calibrated value in an increas= ing + or decreasing manner, use 6 bit two=E2=80=99s complement values. + + phy-drive-ldo-level: + $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 0 + maximum: 7 + description: + The PHY LDO has an amplitude tuning feature to adjust the LDO output + for the HSTX drive. To offset the drive level from the default value, + supported levels are with the following mapping: + 0 =3D 375mV, 1 =3D 400mV, 2 =3D 425mV, 3 =3D 450mV, 4 =3D 475mV, 5 = =3D 500mV, + 6 =3D 500mV, 7 =3D 500mV + required: - compatible - reg @@ -64,5 +93,9 @@ examples: clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "iface", "ref"; + + phy-resocde-offset-top =3D /bits/ 8 <0x0 0x0 0x0 0x0 0x0>; + phy-rescode-offset-bot =3D /bits/ 8 <0x0 0x0 0x0 0x0 0x0>; + phy-drive-ldo-level =3D /bits/ 8 <1>; }; ... --=20 2.7.4 From nobody Tue Jun 30 20:12:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEB66C433F5 for ; Mon, 10 Jan 2022 12:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234187AbiAJM60 (ORCPT ); Mon, 10 Jan 2022 07:58:26 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:61254 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343550AbiAJM4K (ORCPT ); Mon, 10 Jan 2022 07:56:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1641819370; x=1673355370; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=9t/Xu5PgIegcYhMGwAj50Sze7qm72rRfmBmOT9p3+WU=; b=GV9zXUy1cNZMsS06f5tr4z7tzyBa2XRV0r/J4AFgRDuWbgQEUBPFNbOG rnqd+jQ7o+alpZvbBsOvvKzHqn/kSgBDNIqaYVSa2wjkVTSeRp06zeRdw 6oo3tbOM/9BvK52vQ9I0CekLYFTwEihWpIsYKgK5sibBHnvSyqP5oUnok 0=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 10 Jan 2022 04:56:09 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Jan 2022 04:56:07 -0800 X-QCInternal: smtphost Received: from rajeevny-linux.qualcomm.com ([10.204.66.121]) by ironmsg02-blr.qualcomm.com with ESMTP; 10 Jan 2022 18:25:47 +0530 Received: by rajeevny-linux.qualcomm.com (Postfix, from userid 2363605) id 4373A219F1; Mon, 10 Jan 2022 18:25:46 +0530 (IST) From: Rajeev Nandan To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Rajeev Nandan , linux-kernel@vger.kernel.org, sean@poorly.run, robdclark@gmail.com, robh+dt@kernel.org, robh@kernel.org, quic_abhinavk@quicinc.com, quic_kalyant@quicinc.com, quic_mkrishn@quicinc.com, jonathan@marek.ca, dmitry.baryshkov@linaro.org, airlied@linux.ie, daniel@ffwll.ch, swboyd@chromium.org Subject: [v2 2/3] drm/msm/dsi: Add dsi phy tuning configuration support Date: Mon, 10 Jan 2022 18:25:36 +0530 Message-Id: <1641819337-17037-3-git-send-email-quic_rajeevny@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1641819337-17037-1-git-send-email-quic_rajeevny@quicinc.com> References: <1641819337-17037-1-git-send-email-quic_rajeevny@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for MSM DSI PHY tuning configuration. Current design is to support drive strength and drive level/amplitude tuning for 10nm PHY version, but this can be extended to other PHY versions. Signed-off-by: Rajeev Nandan --- Changes in v2: - New. - Split into generic code and 10nm-specific part (Dmitry Baryshkov) drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 3 +++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 8c65ef6..ee3739d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -739,6 +739,9 @@ static int dsi_phy_driver_probe(struct platform_device = *pdev) } } =20 + if (phy->cfg->ops.tuning_cfg_init) + phy->cfg->ops.tuning_cfg_init(phy); + ret =3D dsi_phy_regulator_init(phy); if (ret) goto fail; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index b91303a..b559a2b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -25,6 +25,7 @@ struct msm_dsi_phy_ops { void (*save_pll_state)(struct msm_dsi_phy *phy); int (*restore_pll_state)(struct msm_dsi_phy *phy); bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable); + void (*tuning_cfg_init)(struct msm_dsi_phy *phy); }; =20 struct msm_dsi_phy_cfg { @@ -81,6 +82,20 @@ struct msm_dsi_dphy_timing { #define DSI_PIXEL_PLL_CLK 1 #define NUM_PROVIDED_CLKS 2 =20 +#define DSI_LANE_MAX 5 + +/** + * struct msm_dsi_phy_tuning_cfg - Holds PHY tuning config parameters. + * @rescode_offset_top: Offset for pull-up legs rescode. + * @rescode_offset_bot: Offset for pull-down legs rescode. + * @vreg_ctrl: vreg ctrl to drive LDO level + */ +struct msm_dsi_phy_tuning_cfg { + u8 rescode_offset_top[DSI_LANE_MAX]; + u8 rescode_offset_bot[DSI_LANE_MAX]; + u8 vreg_ctrl; +}; + struct msm_dsi_phy { struct platform_device *pdev; void __iomem *base; @@ -98,6 +113,7 @@ struct msm_dsi_phy { =20 struct msm_dsi_dphy_timing timing; const struct msm_dsi_phy_cfg *cfg; + struct msm_dsi_phy_tuning_cfg tuning_cfg; =20 enum msm_dsi_phy_usecase usecase; bool regulator_ldo_mode; --=20 2.7.4 From nobody Tue Jun 30 20:12:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 434D1C4332F for ; Mon, 10 Jan 2022 13:00:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230165AbiAJNAF (ORCPT ); Mon, 10 Jan 2022 08:00:05 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:18076 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231394AbiAJM6J (ORCPT ); Mon, 10 Jan 2022 07:58:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1641819490; x=1673355490; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=p+GfconfbCV29XFjTmFEjVwoR0nqMLcivRQLR9DnBfk=; b=N+vJgC+l9XCvdVZ2vdpovuhg4UlyWjskWeXmDy+2RWEVQl8I5DqToYw/ rkEYzTftqxCv8DE3fZc0QlY4AE9qz9OopbonC2JziZa2rw0MbGjSJL5h6 BDbAxoyYMVp2jkfhi8LZq/ReWGnX23Vl7iiDxwvhF+GAMnj9Qy+qrXgB3 A=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 10 Jan 2022 04:56:11 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Jan 2022 04:56:09 -0800 X-QCInternal: smtphost Received: from rajeevny-linux.qualcomm.com ([10.204.66.121]) by ironmsg02-blr.qualcomm.com with ESMTP; 10 Jan 2022 18:25:48 +0530 Received: by rajeevny-linux.qualcomm.com (Postfix, from userid 2363605) id 2D491219EE; Mon, 10 Jan 2022 18:25:47 +0530 (IST) From: Rajeev Nandan To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Rajeev Nandan , linux-kernel@vger.kernel.org, sean@poorly.run, robdclark@gmail.com, robh+dt@kernel.org, robh@kernel.org, quic_abhinavk@quicinc.com, quic_kalyant@quicinc.com, quic_mkrishn@quicinc.com, jonathan@marek.ca, dmitry.baryshkov@linaro.org, airlied@linux.ie, daniel@ffwll.ch, swboyd@chromium.org Subject: [v2 3/3] drm/msm/dsi: Add 10nm dsi phy tuning configuration support Date: Mon, 10 Jan 2022 18:25:37 +0530 Message-Id: <1641819337-17037-4-git-send-email-quic_rajeevny@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1641819337-17037-1-git-send-email-quic_rajeevny@quicinc.com> References: <1641819337-17037-1-git-send-email-quic_rajeevny@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The clock and data lanes of the DSI PHY have a calibration circuitry feature. As per the MSM DSI PHY tuning guidelines, the drive strength tuning can be done by adjusting rescode offset for hstop/hsbot, and the drive level tuning can be done by adjusting the LDO output level for the HSTX drive. Signed-off-by: Rajeev Nandan --- Changes in v2: - Split into generic code and 10nm-specific part (Dmitry Baryshkov) - Fix the backward compatibility (Dmitry Baryshkov) drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 51 ++++++++++++++++++++++++++= ---- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/m= sm/dsi/phy/dsi_phy_10nm.c index d8128f5..40cd0f7 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -775,10 +775,13 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_= dsi_phy *phy) dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0); dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i), i =3D=3D 4 ? 0x80 : 0x0); - dsi_phy_write(lane_base + - REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i), 0x0); - dsi_phy_write(lane_base + - REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i), 0x0); + + /* platform specific dsi phy drive strength adjustment */ + dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i), + phy->tuning_cfg.rescode_offset_top[i]); + dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i), + phy->tuning_cfg.rescode_offset_bot[i]); + dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]); } @@ -834,8 +837,9 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, /* Select MS1 byte-clk */ dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL, 0x10); =20 - /* Enable LDO */ - dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_VREG_CTRL, 0x59); + /* Enable LDO with platform specific drive level/amplitude adjustment */ + dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_VREG_CTRL, + phy->tuning_cfg.vreg_ctrl); =20 /* Configure PHY lane swap (TODO: we need to calculate this) */ dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG0, 0x21); @@ -922,6 +926,39 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *p= hy) DBG("DSI%d PHY disabled", phy->id); } =20 +static void dsi_10nm_phy_tuning_cfg_init(struct msm_dsi_phy *phy) +{ + struct device *dev =3D &phy->pdev->dev; + u8 offset_top[DSI_LANE_MAX] =3D { 0 }; /* No offset */ + u8 offset_bot[DSI_LANE_MAX] =3D { 0 }; /* No offset */ + u8 ldo_level =3D 0x1; /* 400mV */ + int ret, i; + + /* Drive strength adjustment parameters */ + ret =3D of_property_read_u8_array(dev->of_node, "phy-resocde-offset-top", + offset_top, DSI_LANE_MAX); + if (ret && ret !=3D -EINVAL) + DRM_DEV_ERROR(dev, "failed to parse phy-resocde-offset-top, %d\n", ret); + + for (i =3D 0; i < DSI_LANE_MAX; i++) + phy->tuning_cfg.rescode_offset_top[i] =3D 0x3f & offset_top[i]; + + ret =3D of_property_read_u8_array(dev->of_node, "phy-resocde-offset-bot", + offset_bot, DSI_LANE_MAX); + if (ret && ret !=3D -EINVAL) + DRM_DEV_ERROR(dev, "failed to parse phy-resocde-offset-bot, %d\n", ret); + + for (i =3D 0; i < DSI_LANE_MAX; i++) + phy->tuning_cfg.rescode_offset_bot[i] =3D 0x3f & offset_bot[i]; + + /* Drive level/amplitude adjustment parameters */ + ret =3D of_property_read_u8(dev->of_node, "phy-drive-ldo-level", &ldo_lev= el); + if (ret && ret !=3D -EINVAL) + DRM_DEV_ERROR(dev, "failed to parse phy-drive-ldo-level, %d\n", ret); + + phy->tuning_cfg.vreg_ctrl =3D 0x58 | (0x7 & ldo_level); +} + const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs =3D { .has_phy_lane =3D true, .reg_cfg =3D { @@ -936,6 +973,7 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs =3D { .pll_init =3D dsi_pll_10nm_init, .save_pll_state =3D dsi_10nm_pll_save_state, .restore_pll_state =3D dsi_10nm_pll_restore_state, + .tuning_cfg_init =3D dsi_10nm_phy_tuning_cfg_init, }, .min_pll_rate =3D 1000000000UL, .max_pll_rate =3D 3500000000UL, @@ -957,6 +995,7 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs =3D= { .pll_init =3D dsi_pll_10nm_init, .save_pll_state =3D dsi_10nm_pll_save_state, .restore_pll_state =3D dsi_10nm_pll_restore_state, + .tuning_cfg_init =3D dsi_10nm_phy_tuning_cfg_init, }, .min_pll_rate =3D 1000000000UL, .max_pll_rate =3D 3500000000UL, --=20 2.7.4