From nobody Tue Jun 30 23:32:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4DB5C4332F for ; Fri, 7 Jan 2022 00:57:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344439AbiAGA5c (ORCPT ); Thu, 6 Jan 2022 19:57:32 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:26842 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230133AbiAGA53 (ORCPT ); Thu, 6 Jan 2022 19:57:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1641517049; x=1673053049; h=from:to:cc:subject:date:message-id:mime-version; bh=+Z7xRVSlmNeiIFWUHvEdTDAW69uc9POi1AmSX78ne+Q=; b=DW01MZc4I917lHP+xMYZwdIZng3V8NsZGq57y3s5NcYBCU4zhLLLdmiu MEZhbEKUFodoIBBFyuimom8hleild7zsCVFwMYDUYKs/DiUoM5B0bBknR knMaqnuyYI4bMxTmFhLNo9iMskOC0Wkwzml1NoVr94WQ6nMFMGxmz+0Tx k=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 06 Jan 2022 16:57:28 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jan 2022 16:57:28 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 6 Jan 2022 16:57:27 -0800 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 6 Jan 2022 16:57:25 -0800 From: Kuogee Hsieh To: , , , , , , , , CC: , , , , , , , , Kuogee Hsieh Subject: [PATCH v4] drm/msm/dp: add support of tps4 (training pattern 4) for HBR3 Date: Thu, 6 Jan 2022 16:57:08 -0800 Message-ID: <1641517028-27639-1-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kuogee Hsieh Some DP sinkers prefer to use tps4 instead of tps3 during training #2. This patch will use tps4 to perform link training #2 if sinker's DPCD supports it. Changes in V2: -- replace dp_catalog_ctrl_set_pattern() with dp_catalog_ctrl_set_pattern= _state_bit() Changes in V3: -- change state_ctrl_bits type to u32 and pattern type to u8 Changes in V4: -- align } else if { and } else { Signed-off-by: Kuogee Hsieh Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/dp/dp_catalog.c | 12 ++++++------ drivers/gpu/drm/msm/dp/dp_catalog.h | 2 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 ++++++++++++----- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/d= p_catalog.c index 6ae9b29..64f0b26 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -456,19 +456,19 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp= _catalog, dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); } =20 -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, - u32 pattern) +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, + u32 state_bit) { int bit, ret; u32 data; struct dp_catalog_private *catalog =3D container_of(dp_catalog, struct dp_catalog_private, dp_catalog); =20 - bit =3D BIT(pattern - 1); - DRM_DEBUG_DP("hw: bit=3D%d train=3D%d\n", bit, pattern); + bit =3D BIT(state_bit - 1); + DRM_DEBUG_DP("hw: bit=3D%d train=3D%d\n", bit, state_bit); dp_catalog_ctrl_state_ctrl(dp_catalog, bit); =20 - bit =3D BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; + bit =3D BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; =20 /* Poll for mainlink ready status */ ret =3D readx_poll_timeout(readl, catalog->io->dp_controller.link.base + @@ -476,7 +476,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_c= atalog, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); if (ret < 0) { - DRM_ERROR("set pattern for link_train=3D%d failed\n", pattern); + DRM_ERROR("set state_bit for link_train=3D%d failed\n", state_bit); return ret; } return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/d= p_catalog.h index 6965afa..7dea101 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -94,7 +94,7 @@ void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_= catalog, bool enable); void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u3= 2 tb); void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid); -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, u32 pattern= ); +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u= 32 pattern); void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable= ); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 39558a2..ad64ddd 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1083,7 +1083,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_privat= e *ctrl, =20 *training_step =3D DP_TRAINING_1; =20 - ret =3D dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); + ret =3D dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); if (ret) return ret; dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | @@ -1181,7 +1181,8 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_privat= e *ctrl, int *training_step) { int tries =3D 0, ret =3D 0; - char pattern; + u8 pattern; + u32 state_ctrl_bit; int const maximum_retries =3D 5; u8 link_status[DP_LINK_STATUS_SIZE]; =20 @@ -1189,12 +1190,18 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_priv= ate *ctrl, =20 *training_step =3D DP_TRAINING_2; =20 - if (drm_dp_tps3_supported(ctrl->panel->dpcd)) + if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { + pattern =3D DP_TRAINING_PATTERN_4; + state_ctrl_bit =3D 4; + } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { pattern =3D DP_TRAINING_PATTERN_3; - else + state_ctrl_bit =3D 3; + } else { pattern =3D DP_TRAINING_PATTERN_2; + state_ctrl_bit =3D 2; + } =20 - ret =3D dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); + ret =3D dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_b= it); if (ret) return ret; =20 --=20 The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project