From nobody Wed Jul 1 14:37:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8759C433EF for ; Mon, 20 Dec 2021 17:15:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240109AbhLTRPY (ORCPT ); Mon, 20 Dec 2021 12:15:24 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:25741 "EHLO alexa-out-sd-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230225AbhLTRPX (ORCPT ); Mon, 20 Dec 2021 12:15:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1640020523; x=1671556523; h=from:to:cc:subject:date:message-id:mime-version; bh=sUnftenY0Dcj8cPcjDNYikb7V009NGvqmMjZYFYjV3I=; b=IJ6DuSlOSqrgHIUkwYQ3NBwMGRs+1Lc54kUQrbFNDI+ssFaoMnrDMEUe UhB9zPE0w6u3n+kJPO+pGdBd7jxK13lAW2PpGUFM3hIwYaX9kYLJ37nMl MFa91ThpKxiMmWsPriepEb4klzAXtLpufXY5XCy3BEVksGxFqkMdb8yTs 8=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 20 Dec 2021 09:15:22 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2021 09:15:22 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 09:15:21 -0800 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Mon, 20 Dec 2021 09:15:21 -0800 From: Kuogee Hsieh To: , , , , , , , CC: , , , , , , , Subject: [PATCH v9] phy: qcom-qmp: add display port v4 voltage and pre-emphasis swing tables Date: Mon, 20 Dec 2021 09:15:12 -0800 Message-ID: <1640020512-17224-1-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit aff188feb5e1 ("phy: qcom-qmp: add support for sm8250-usb3-dp phy")' added functions to support V4 of the PHY, but it did not update voltage and pre-emphasis tables accordingly. This patch add v4 voltage and pre-emphasis swing tables to complete v4 phy implementation. Both voltage and pre-emphasis swing level are set during link training negotiation between host and sink. There are totally four tables added. A voltage swing table for both hbr and hbr1, a voltage table for both hbr2 and hbr3, a pre-emphasis table for both hbr and hbr1 and a pre-emphasis table for both hbr2 and hbr3. In addition, write 0x0a to TX_TX_POL_INV is added to complete the sequence of configure dp phy base on the hardware documentation. Fixes: aff188feb5e1 ("phy: qcom-qmp: add support for sm8250-usb3-dp phy") Signed-off-by: Kuogee Hsieh Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson --- drivers/phy/qualcomm/phy-qcom-qmp.c | 112 +++++++++++++++++++++++++-------= ---- 1 file changed, 77 insertions(+), 35 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy= -qcom-qmp.c index 456a59d..d41e30c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -4255,40 +4255,50 @@ static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_= phy *qphy) qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); } =20 -static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] =3D { +#define MAX_SWING_LEVEL 4 +#define MAX_VOLTAGE_LEVEL 4 +#define MAX_EMPHASIS_LEVEL 4 + +static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[MAX_SWING_LEVEL][MAX_EMPH= ASIS_LEVEL] =3D { { 0x00, 0x0c, 0x15, 0x1a }, { 0x02, 0x0e, 0x16, 0xff }, { 0x02, 0x11, 0xff, 0xff }, { 0x04, 0xff, 0xff, 0xff } }; =20 -static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] =3D { +static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[MAX_SWING_LEVEL][MAX_VOL= TAGE_LEVEL] =3D { { 0x02, 0x12, 0x16, 0x1a }, { 0x09, 0x19, 0x1f, 0xff }, { 0x10, 0x1f, 0xff, 0xff }, { 0x1f, 0xff, 0xff, 0xff } }; =20 -static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] =3D { +static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[MAX_SWING_LEVEL][MAX_EMPHAS= IS_LEVEL] =3D { { 0x00, 0x0c, 0x14, 0x19 }, { 0x00, 0x0b, 0x12, 0xff }, { 0x00, 0x0b, 0xff, 0xff }, { 0x04, 0xff, 0xff, 0xff } }; =20 -static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] =3D { +static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[MAX_SWING_LEVEL][MAX_VOLTA= GE_LEVEL] =3D { { 0x08, 0x0f, 0x16, 0x1f }, { 0x11, 0x1e, 0x1f, 0xff }, { 0x19, 0x1f, 0xff, 0xff }, { 0x1f, 0xff, 0xff, 0xff } }; =20 -static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy, - unsigned int drv_lvl_reg, unsigned int emp_post_reg) +static int __qcom_qmp_phy_configure_dp_swing + (struct qmp_phy *qphy, + unsigned int drv_lvl_reg, + unsigned int emp_post_reg, + const u8 voltage_swing_hbr_rbr[MAX_SWING_LEVEL][MAX_VOLTAGE_LEVEL], + const u8 pre_emphasis_hbr_rbr[MAX_SWING_LEVEL][MAX_EMPHASIS_LEVEL], + const u8 voltage_swing_hbr3_hbr2[MAX_SWING_LEVEL][MAX_VOLTAGE_LEVEL], + const u8 pre_emphasis_hbr3_hbr2[MAX_SWING_LEVEL][MAX_EMPHASIS_LEVEL]) { const struct phy_configure_opts_dp *dp_opts =3D &qphy->dp_opts; unsigned int v_level =3D 0, p_level =3D 0; - u8 voltage_swing_cfg, pre_emphasis_cfg; + u8 voltage, emphasis; int i; =20 for (i =3D 0; i < dp_opts->lanes; i++) { @@ -4297,26 +4307,25 @@ static int qcom_qmp_phy_configure_dp_swing(struct q= mp_phy *qphy, } =20 if (dp_opts->link_rate <=3D 2700) { - voltage_swing_cfg =3D qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; - pre_emphasis_cfg =3D qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; + voltage =3D voltage_swing_hbr_rbr[v_level][p_level]; + emphasis =3D pre_emphasis_hbr_rbr[v_level][p_level]; } else { - voltage_swing_cfg =3D qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level= ]; - pre_emphasis_cfg =3D qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; + voltage =3D voltage_swing_hbr3_hbr2[v_level][p_level]; + emphasis =3D pre_emphasis_hbr3_hbr2[v_level][p_level]; } =20 /* TODO: Move check to config check */ - if (voltage_swing_cfg =3D=3D 0xFF && pre_emphasis_cfg =3D=3D 0xFF) + if (voltage =3D=3D 0xFF && emphasis =3D=3D 0xFF) return -EINVAL; =20 /* Enable MUX to use Cursor values from these registers */ - voltage_swing_cfg |=3D DP_PHY_TXn_TX_DRV_LVL_MUX_EN; - pre_emphasis_cfg |=3D DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; - - writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); - writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); - writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); - writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); + voltage |=3D DP_PHY_TXn_TX_DRV_LVL_MUX_EN; + emphasis |=3D DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; =20 + writel(voltage, qphy->tx + drv_lvl_reg); + writel(emphasis, qphy->tx + emp_post_reg); + writel(voltage, qphy->tx2 + drv_lvl_reg); + writel(emphasis, qphy->tx2 + emp_post_reg); return 0; } =20 @@ -4325,9 +4334,14 @@ static void qcom_qmp_v3_phy_configure_dp_tx(struct q= mp_phy *qphy) const struct phy_configure_opts_dp *dp_opts =3D &qphy->dp_opts; u32 bias_en, drvr_en; =20 - if (qcom_qmp_phy_configure_dp_swing(qphy, - QSERDES_V3_TX_TX_DRV_LVL, - QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) + if (__qcom_qmp_phy_configure_dp_swing + (qphy, + QSERDES_V3_TX_TX_DRV_LVL, + QSERDES_V3_TX_TX_EMP_POST1_LVL, + qmp_dp_v3_voltage_swing_hbr_rbr, + qmp_dp_v3_pre_emphasis_hbr_rbr, + qmp_dp_v3_voltage_swing_hbr3_hbr2, + qmp_dp_v3_pre_emphasis_hbr3_hbr2) < 0) return; =20 if (dp_opts->lanes =3D=3D 1) { @@ -4465,6 +4479,35 @@ static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_p= hy *qphy) return 0; } =20 +/* The values in these tables are given without MUX_EN (0x20) bit set */ +static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[MAX_SWING_LEVEL][MAX_EMPH= ASIS_LEVEL] =3D { + { 0x00, 0x0c, 0x15, 0x1b }, + { 0x02, 0x0e, 0x16, 0xff }, + { 0x02, 0x11, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v4_voltage_swing_hbr3_hbr2[MAX_SWING_LEVEL][MAX_VOL= TAGE_LEVEL] =3D { + { 0x02, 0x12, 0x16, 0x1a }, + { 0x09, 0x19, 0x1f, 0xff }, + { 0x10, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[MAX_SWING_LEVEL][MAX_EMPHAS= IS_LEVEL] =3D { + { 0x00, 0x0e, 0x15, 0x1b }, + { 0x00, 0x0e, 0x15, 0xff }, + { 0x00, 0x0e, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[MAX_SWING_LEVEL][MAX_VOLTA= GE_LEVEL] =3D { + { 0x08, 0x0f, 0x16, 0x1f }, + { 0x11, 0x1e, 0x1f, 0xff }, + { 0x16, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) { writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_= PWRDN | @@ -4494,16 +4537,14 @@ static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_= phy *qphy) =20 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) { - /* Program default values before writing proper values */ - writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); - writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); - - writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); - writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); - - qcom_qmp_phy_configure_dp_swing(qphy, + __qcom_qmp_phy_configure_dp_swing + (qphy, QSERDES_V4_TX_TX_DRV_LVL, - QSERDES_V4_TX_TX_EMP_POST1_LVL); + QSERDES_V4_TX_TX_EMP_POST1_LVL, + qmp_dp_v4_voltage_swing_hbr_rbr, + qmp_dp_v4_pre_emphasis_hbr_rbr, + qmp_dp_v4_voltage_swing_hbr3_hbr2, + qmp_dp_v4_pre_emphasis_hbr3_hbr2); } =20 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) @@ -4622,6 +4663,9 @@ static int qcom_qmp_v4_phy_configure_dp_phy(struct qm= p_phy *qphy) writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); =20 + writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); + writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); + writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); udelay(2000); writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); @@ -4633,11 +4677,9 @@ static int qcom_qmp_v4_phy_configure_dp_phy(struct q= mp_phy *qphy) 10000)) return -ETIMEDOUT; =20 - writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); - writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); =20 - writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); - writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); + writel(0x22, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); + writel(0x22, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); =20 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); --=20 The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project