From nobody Wed Jul 1 17:38:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DDBDC433FE for ; Fri, 17 Dec 2021 11:46:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235699AbhLQLqH (ORCPT ); Fri, 17 Dec 2021 06:46:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233332AbhLQLqG (ORCPT ); Fri, 17 Dec 2021 06:46:06 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57764C061574; Fri, 17 Dec 2021 03:46:06 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id y9so1845467pgj.5; Fri, 17 Dec 2021 03:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NeabA99WFW7MqI88OwEli7p5Eii1CpqvzDH2hHk3FdA=; b=XlAiVXPB3cegN82KShPyUBx9mMtd6KwzEOpqBbr3EmSayTLbD6ZWz4EobFhhePZxpS Kh1iZHLdo82NYlOGF5d4F1oZ9Ki9bnnJHTM8IeaPPR11Ygz91fTxde7xrYLTLfgme901 v31tTzVebynary0FY7dwM06F2995RyNt07zBO7hGkljjFktfSS9bg4Qv4+TQPUfa6ry2 fxbKLm5kAtxJD1pQF59Hr+/+SsQ/xRbBaRNZBjv6pvYfbZ7KtNTuJ9a0u4hYkaMnFwq5 710InWCqL6lXjv9ovwX7sRMnnNzYtEaa+EFLfaU4le/wuvQnvboxr9fauk4d8DGctQgI P5Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NeabA99WFW7MqI88OwEli7p5Eii1CpqvzDH2hHk3FdA=; b=RCJkwhJSB/KDLMkdvsJWrT3UnD7taAYhdWvHTtdvQx1R93aIKxhL2o0rjUgjWLiWMV Vm77kX1sMBXW9G5/NXLXHe8w66k+/sJTH6Q9mkounfpZwh0XcKqSEgeY655aKhUdNrbk jsMWu/qlsZaPK94qTzPq3GX+RKX9gj48J7TJ8Iza3QCokUHwlAca/oxU22q/8rCzhUHJ gVTkEy5hP9aA9nN6y97B48o7n1Jz9bwOPE9+IEWe3wd1vHgCAK22TPabdVq52ioyLW9C 8/om4kvCuL8WBSqaywVKyD/8Ml+Or6PmfG2V9lLtc4LA25J6wPXqMmgpvJstGrQ83KT5 lenA== X-Gm-Message-State: AOAM533qEDlfh5gJtBG3aVCFVAAiKSHv9pbJe4Pvkc3JzQniWuQESgXH ygdH8Yq35qFW7TPRQVCrUrc= X-Google-Smtp-Source: ABdhPJxP/r+YHFVcwDOSyLoVF2ywtZH0hW0yvgO4AaiwbTPMQr3t9gT/ReAIRxblEldURcrsb1qGuw== X-Received: by 2002:a63:175c:: with SMTP id 28mr2589481pgx.66.1639741565927; Fri, 17 Dec 2021 03:46:05 -0800 (PST) Received: from scdiu3.sunplus.com ([113.196.136.192]) by smtp.googlemail.com with ESMTPSA id kb1sm1663225pjb.56.2021.12.17.03.46.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Dec 2021 03:46:05 -0800 (PST) From: Hammer Hsieh X-Google-Original-From: Hammer Hsieh To: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, robh+dt@kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: wells.lu@sunplus.com, Hammer Hsieh Subject: [PATCH v1 1/2] dt-bindings:pwm:Add bindings doc for Sunplus SoC PWM Driver Date: Fri, 17 Dec 2021 19:46:07 +0800 Message-Id: <1639741568-5846-2-git-send-email-hammer.hsieh@sunplus.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1639741568-5846-1-git-send-email-hammer.hsieh@sunplus.com> References: <1639741568-5846-1-git-send-email-hammer.hsieh@sunplus.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add bindings doc for Sunplus SoC PWM Driver Signed-off-by: Hammer Hsieh --- .../devicetree/bindings/pwm/pwm-sunplus.yaml | 45 ++++++++++++++++++= ++++ MAINTAINERS | 5 +++ 2 files changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sunplus.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-sunplus.yaml b/Docum= entation/devicetree/bindings/pwm/pwm-sunplus.yaml new file mode 100644 index 0000000..9af19df --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sunplus.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-sunplus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SoC PWM Controller + +maintainers: + - Hammer Hsieh + +properties: + '#pwm-cells': + const: 2 + + compatible: + items: + - const: sunplus,sp7021-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - '#pwm-cells' + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm: pwm@9c007a00 { + #pwm-cells =3D <2>; + compatible =3D "sunplus,sp7021-pwm"; + reg =3D <0x9c007a00 0x80>; + clocks =3D <&clkc 0xa2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 13f9a84..721ed79 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18242,6 +18242,11 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/dlink/sundance.c =20 +SUNPLUS PWM DRIVER +M: Hammer Hsieh +S: Maintained +F: Documentation/devicetree/bindings/pwm/pwm-sunplus.yaml + SUPERH M: Yoshinori Sato M: Rich Felker --=20 2.7.4 From nobody Wed Jul 1 17:38:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4A25C433EF for ; Fri, 17 Dec 2021 11:46:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235715AbhLQLqJ (ORCPT ); Fri, 17 Dec 2021 06:46:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235700AbhLQLqI (ORCPT ); Fri, 17 Dec 2021 06:46:08 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50B5EC06173E; Fri, 17 Dec 2021 03:46:08 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id co15so2026362pjb.2; Fri, 17 Dec 2021 03:46:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VfYvv8CdBWc6RQO1VF2WxtqklqiNs45I0XH86gJfgtU=; b=oqM2SRnZMuQjX53B6bAKCtUtrHH9kCw/FVOdUN934xGAWXvOo/aC+PoSOUpLJkxgBb qll8OYHqG0N74Gan81uh7uv+njksvD0tlWYBmImET6/WsGCf/KNzntfq5tOyrhr6642d iDn5b04x3DhXVWHl0kxNR3q/8gVuCXkBdpZuE3sqewyVBKYkAyxnn8S+xV40D7nmS4oc LxsNNJxtI9LlLP0WcHI2ppSLOnhnb3hlQocW842lZjTUYX0mOnzYhwXjAdzd+t2VupUQ UzdBbBnTTJbW1BX5ROmRFwoayiDzh1DaXowyvhlH8N3CSAEMfS0P5mjSVz4U2ZcOWq6N 1Q1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VfYvv8CdBWc6RQO1VF2WxtqklqiNs45I0XH86gJfgtU=; b=I4iyEFQGiPsl/+w8D84NU8/4aS0N4gvermvqbnvSn2I7i4jqoTK4leVQhrJWk041/k i4knbb49zAt/k11eoFOpKa1de57kWEKY7p3BwXaykmc2wFoO3ip0NDps72m92W7A8tyy iqAkgGucpCMI69nTP3k4TtPvjUyfQv7poiNsreJhX1an+xzPaSui+nVMjDgYk6S49ztn 1UtSkgcijTi29hHVKWRxJ34WlOE8nBkJ/t0Fl98EkZSwVmsAcu72nEyp8WYiX02PBVkq vKrgzufe9wBDmqgYfyTVUIB5ZaYjCDt8yeYCjXC2ZpfpIHrLHka7vQHgPbq/10HcLIZh 5V0g== X-Gm-Message-State: AOAM533p/6UdYJHB9itNB+7CuPuHc3lmiPHhDn+T356lFq2uUEvEFied 77J39kV/a0vSSzyZSkTcmQPPf6ZFVhFSGw== X-Google-Smtp-Source: ABdhPJwrFm1ODH5bToECJnRe4XshOgVfudwDL3SqHaxkEeCEdpNblTVHxSgbOq6DLrxqX+jU4LH9AA== X-Received: by 2002:a17:90b:517:: with SMTP id r23mr11916278pjz.152.1639741567818; Fri, 17 Dec 2021 03:46:07 -0800 (PST) Received: from scdiu3.sunplus.com ([113.196.136.192]) by smtp.googlemail.com with ESMTPSA id kb1sm1663225pjb.56.2021.12.17.03.46.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Dec 2021 03:46:07 -0800 (PST) From: Hammer Hsieh X-Google-Original-From: Hammer Hsieh To: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, robh+dt@kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: wells.lu@sunplus.com, Hammer Hsieh Subject: [PATCH v1 2/2] pwm:sunplus-pwm:Add Sunplus SoC PWM Driver Date: Fri, 17 Dec 2021 19:46:08 +0800 Message-Id: <1639741568-5846-3-git-send-email-hammer.hsieh@sunplus.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1639741568-5846-1-git-send-email-hammer.hsieh@sunplus.com> References: <1639741568-5846-1-git-send-email-hammer.hsieh@sunplus.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add Sunplus SoC PWM Driver Signed-off-by: Hammer Hsieh --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 11 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sunplus.c | 192 ++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 205 insertions(+) create mode 100644 drivers/pwm/pwm-sunplus.c diff --git a/MAINTAINERS b/MAINTAINERS index 721ed79..1c9e3c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18246,6 +18246,7 @@ SUNPLUS PWM DRIVER M: Hammer Hsieh S: Maintained F: Documentation/devicetree/bindings/pwm/pwm-sunplus.yaml +F: drivers/pwm/pwm-sunplus.c =20 SUPERH M: Yoshinori Sato diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 21e3b05..9df5d5f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -526,6 +526,17 @@ config PWM_SPRD To compile this driver as a module, choose M here: the module will be called pwm-sprd. =20 +config PWM_SUNPLUS + tristate "Sunplus PWM support" + depends on ARCH_SUNPLUS || COMPILE_TEST + depends on HAS_IOMEM && OF + help + Generic PWM framework driver for the PWM controller on + Sunplus SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sunplus. + config PWM_STI tristate "STiH4xx PWM support" depends on ARCH_STI || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 708840b..be58616 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_PWM_STM32) +=3D pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) +=3D pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) +=3D pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) +=3D pwm-sun4i.o +obj-$(CONFIG_PWM_SUNPLUS) +=3D pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) +=3D pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) +=3D pwm-tiecap.o obj-$(CONFIG_PWM_TIEHRPWM) +=3D pwm-tiehrpwm.o diff --git a/drivers/pwm/pwm-sunplus.c b/drivers/pwm/pwm-sunplus.c new file mode 100644 index 0000000..0ae59fc --- /dev/null +++ b/drivers/pwm/pwm-sunplus.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM device driver for SUNPLUS SoCs + * + * Author: Hammer Hsieh + */ +#include +#include +#include +#include +#include +#include + +#define PWM_SUP_CONTROL0 0x000 +#define PWM_SUP_CONTROL1 0x004 +#define PWM_SUP_FREQ_BASE 0x008 +#define PWM_SUP_DUTY_BASE 0x018 +#define PWM_SUP_FREQ(ch) (PWM_SUP_FREQ_BASE + 4 * (ch)) +#define PWM_SUP_DUTY(ch) (PWM_SUP_DUTY_BASE + 4 * (ch)) +#define PWM_SUP_FREQ_MAX GENMASK(15, 0) +#define PWM_SUP_DUTY_MAX GENMASK(7, 0) + +#define PWM_SUP_NUM 4 +#define PWM_BYPASS_BIT_SHIFT 8 +#define PWM_DD_SEL_BIT_SHIFT 8 +#define PWM_SUP_FREQ_SCALER 256 + +struct sunplus_pwm { + struct pwm_chip chip; + void __iomem *base; + struct clk *clk; +}; + +static inline struct sunplus_pwm *to_sunplus_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct sunplus_pwm, chip); +} + +static void sunplus_reg_init(void __iomem *base) +{ + u32 i, value; + + /* turn off all pwm channel output */ + value =3D readl(base + PWM_SUP_CONTROL0); + value &=3D ~GENMASK((PWM_SUP_NUM - 1), 0); + writel(value, base + PWM_SUP_CONTROL0); + + /* init all pwm channel clock source */ + value =3D readl(base + PWM_SUP_CONTROL1); + value |=3D GENMASK((PWM_SUP_NUM - 1), 0); + writel(value, base + PWM_SUP_CONTROL1); + + /* init all freq and duty setting */ + for (i =3D 0; i < PWM_SUP_NUM; i++) { + writel(0, base + PWM_SUP_FREQ(i)); + writel(0, base + PWM_SUP_DUTY(i)); + } +} + +static int sunplus_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sunplus_pwm *priv =3D to_sunplus_pwm(chip); + u32 period_ns, duty_ns, value; + u32 dd_freq, duty; + u64 tmp; + + if (!state->enabled) { + value =3D readl(priv->base + PWM_SUP_CONTROL0); + value &=3D ~BIT(pwm->hwpwm); + writel(value, priv->base + PWM_SUP_CONTROL0); + return 0; + } + + period_ns =3D state->period; + duty_ns =3D state->duty_cycle; + + /* cal pwm freq and check value under range */ + tmp =3D clk_get_rate(priv->clk) * (u64)period_ns; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, PWM_SUP_FREQ_SCALER); + dd_freq =3D (u32)tmp; + + if (dd_freq =3D=3D 0) + return -EINVAL; + + if (dd_freq > PWM_SUP_FREQ_MAX) + dd_freq =3D PWM_SUP_FREQ_MAX; + + writel(dd_freq, priv->base + PWM_SUP_FREQ(pwm->hwpwm)); + + /* cal and set pwm duty */ + value =3D readl(priv->base + PWM_SUP_CONTROL0); + value |=3D BIT(pwm->hwpwm); + if (duty_ns =3D=3D period_ns) { + value |=3D BIT(pwm->hwpwm + PWM_BYPASS_BIT_SHIFT); + duty =3D PWM_SUP_DUTY_MAX; + } else { + value &=3D ~BIT(pwm->hwpwm + PWM_BYPASS_BIT_SHIFT); + tmp =3D (u64)duty_ns * PWM_SUP_FREQ_SCALER + (period_ns >> 1); + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, (u64)period_ns); + duty =3D (u32)tmp; + duty |=3D (pwm->hwpwm << PWM_DD_SEL_BIT_SHIFT); + } + writel(value, priv->base + PWM_SUP_CONTROL0); + writel(duty, priv->base + PWM_SUP_DUTY(pwm->hwpwm)); + + return 0; +} + +static void sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device= *pwm, + struct pwm_state *state) +{ + struct sunplus_pwm *priv =3D to_sunplus_pwm(chip); + u32 value; + + value =3D readl(priv->base + PWM_SUP_CONTROL0); + + if (value & BIT(pwm->hwpwm)) + state->enabled =3D true; + else + state->enabled =3D false; +} + +static const struct pwm_ops sunplus_pwm_ops =3D { + .apply =3D sunplus_pwm_apply, + .get_state =3D sunplus_pwm_get_state, + .owner =3D THIS_MODULE, +}; + +static int sunplus_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sunplus_pwm *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk =3D devm_clk_get_optional(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "get pwm clock failed\n"); + + ret =3D clk_prepare_enable(priv->clk); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, + (void(*)(void *))clk_disable_unprepare, + priv->clk); + if (ret) + return ret; + + priv->chip.dev =3D dev; + priv->chip.ops =3D &sunplus_pwm_ops; + priv->chip.npwm =3D PWM_SUP_NUM; + + sunplus_reg_init(priv->base); + + platform_set_drvdata(pdev, priv); + + ret =3D devm_pwmchip_add(dev, &priv->chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Cannot register sunplus PWM\n"); + + return 0; +} + +static const struct of_device_id sunplus_pwm_of_match[] =3D { + { .compatible =3D "sunplus,sp7021-pwm", }, + {} +}; +MODULE_DEVICE_TABLE(of, sunplus_pwm_of_match); + +static struct platform_driver sunplus_pwm_driver =3D { + .probe =3D sunplus_pwm_probe, + .driver =3D { + .name =3D "sunplus-pwm", + .of_match_table =3D sunplus_pwm_of_match, + }, +}; +module_platform_driver(sunplus_pwm_driver); + +MODULE_DESCRIPTION("Sunplus SoC PWM Driver"); +MODULE_AUTHOR("Hammer Hsieh "); +MODULE_LICENSE("GPL v2"); --=20 2.7.4