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Thu, 18 Dec 2025 12:27:14 -0800 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v1 2/9] iommu/arm-smmu-v3: Add alloc_id/free_id functions to arm_smmu_invs Date: Thu, 18 Dec 2025 12:26:48 -0800 Message-ID: <1541ea4a9e9c935c2f907c0c5f13a4af2bdc2114.1766088962.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37A:EE_|SN7PR12MB8772:EE_ X-MS-Office365-Filtering-Correlation-Id: c1a18c0b-a9b5-4bc6-2c27-08de3e73def7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NhdFV2eXxynULxEZlaKFxkx1xCg/h/GyudZ8KdKc8FSLpH0u4a4s5Cxskvd/?= =?us-ascii?Q?EvwIV3BwUCXdQOKnz5Yd9pCNb9e/75WmlDIBfdRe66hgW0K1VAAHY8MOeA5b?= =?us-ascii?Q?xqsCe5lbaQJAiru++tbfVWN32Xy0a2ozloe4THjv4ucZW5dVNzYIUlqUlZTz?= =?us-ascii?Q?6+nZSTFJqH/gIgGPSycz+e7ARngZ40PZS9cBIlG9sdtbm2fq8uRv1AQBYbN5?= =?us-ascii?Q?jGtTvfH2r7DeUrT88bqjmaF2Q+Zn11wUZjdZc9ZnSQZ7ACxZESkhDEYGg/sh?= =?us-ascii?Q?k7MPUcyiCyWx78watqlyzwIxgJ7/Cf7VpimKWnlOZAD4cKEM+J/L0osNudYf?= =?us-ascii?Q?YivBqcj1Xqt9alhDSYPguDAegF59tkeE23vFWQrTXMH1lW1Ex+tcpM5/VG6L?= =?us-ascii?Q?YtkW54RwfFZAabrFJehd52nYMBdI0c/EAgSJz29twggPOOXFXTeireHtZSnE?= =?us-ascii?Q?+RnFcYoW0yoCf2zyOfZe5jLBfSCSu2a9ybjMcrRaDrqGPv82FKM9xMoZkTEw?= =?us-ascii?Q?lIPU774ZpEkMep+kCakS7dBo0cAXp6AxwCo4uE9My7WSYXQQdSGA/RPVspXc?= =?us-ascii?Q?+/gXGOoMmsjuvPdaka0EzY/Fupcael7yBHjUUBSYXbtbFTcMAu7JgTZhqJvL?= =?us-ascii?Q?tVo231WzXc1PyvJ1o+ErKlWsHCXA+8POScJDprrUew97K/DucY2DMR9DG/Bv?= =?us-ascii?Q?lpYz9aJIzZ6IzZADOAtHw3uodRJf/hfJsu9IxiBlNZJqv8OXQiKnMvrpI0aJ?= =?us-ascii?Q?uOPUOCrr9bZH6F3OOZhH3usKvjMbJDZ/1JSLAbDqK0F9P+T1dEIzlyZqGkmR?= =?us-ascii?Q?hQrJa/TbTQpZ4OzE8jJPCGHw4LKQRUfPmLQDVWw/K2brNqMh/7C2b+Dr4hik?= =?us-ascii?Q?uWUmTf05OSr4eWBqHiVwxeYfk7LXDCDrbbHcL9UcNdlUaMrqI04Jk/UDycak?= =?us-ascii?Q?f2C/NbURBcFTJ5O4QDcEUtexBSJSvWHHGHa8tdeRRV8zWe9JV2SZjO/ARMZ9?= =?us-ascii?Q?mwwjO/MqbArfoV+Z6cPqTB6+V1tlrPa0Mp1ZamBD1yiaMQewfXTe6mr0U23a?= =?us-ascii?Q?yGSv0tPfZ17e468hk46GhdLscPjfYvEWlR/fe/ZJWqq0DFfO8blmPrML1MWk?= =?us-ascii?Q?+CNCQn6K7Dm5rh1MCDm51mc3ssmYKXIuBLhptUHoERDg2ETYDvAIIRxnl720?= =?us-ascii?Q?KVM1TeJGDalkEalIBD/OVP6sc9xUuZnfPAS4OKH+X+SzPCsxozGucIVUokiI?= =?us-ascii?Q?/fQioh5ny+C8yY5QfZfRrAK8pvnmiDVsu6ErrxR62U+sW9zYwAOsaBQX7QW4?= =?us-ascii?Q?tS5Hhdb5XWTg6Or+MaxJ55OdYTUQdnhtCp2mbNPk2TjMdiob1Y4jYFNyTFWq?= =?us-ascii?Q?qMotEXyiXakpdJSVoPsJcgjIq++6nlPfFLwC8oTG/qZSUCYt+uL+qwI/JuWh?= =?us-ascii?Q?wyabcG8+iRJ4yUtMeiWv+Xr6+gJj9qd5cDWth9NCAbCYPqduRiTv0GxzR2fY?= =?us-ascii?Q?xINMwP10T/2yz/hb8wQbXuSp5dN+3wMoP1Dl4ezYNcpwwqoxccXITM1tIOvy?= =?us-ascii?Q?Nm2d+Ps6yw4E5s/3eV8=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:31.4898 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c1a18c0b-a9b5-4bc6-2c27-08de3e73def7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8772 Content-Type: text/plain; charset="utf-8" An iotlb tag (ASID/VMID) will not be used: 1) Before being installed to CD/STE during a device attachment 2) After being removed from CD/STE during a device detachment Both (1) and (2) exactly align with the lifecyle of the domain->invs. So, it becomes very nature to use domain->invs to allocate/free an ASID/VMID. Add a pair of function ops in struct arm_smmu_invs, to manage iotlb tag. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 93 +++++++++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 0a5aead300b6..b275673c03ce 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -691,6 +691,9 @@ static inline bool arm_smmu_inv_is_ats(const struct arm= _smmu_inv *inv) * @rwlock: optional rwlock to fench ATS operations * @has_ats: flag if the array contains an INV_TYPE_ATS or INV_TYPE_ATS_FU= LL * @rcu: rcu head for kfree_rcu() + * @smmu_domain: owner domain of the array + * @alloc_id: a callback to allocate a new iotlb tag + * @free_id: a callback to free an iotlb tag when its user counter reaches= 0 * @inv: flexible invalidation array * * The arm_smmu_invs is an RCU data structure. During a ->attach_dev callb= ack, @@ -720,6 +723,9 @@ struct arm_smmu_invs { rwlock_t rwlock; bool has_ats; struct rcu_head rcu; + struct arm_smmu_domain *smmu_domain; + int (*alloc_id)(struct arm_smmu_inv *inv, void *data); + void (*free_id)(struct arm_smmu_inv *inv, bool flush); struct arm_smmu_inv inv[] __counted_by(max_invs); }; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index bf0df16cec45..8a2b7064d29b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3117,6 +3117,94 @@ static void arm_smmu_disable_iopf(struct arm_smmu_ma= ster *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } =20 +/* + * When an array entry's users count reaches zero, it means the ASID/VMID = is no + * longer being invalidated by map/unmap and must be cleaned. The rule is = that + * all ASIDs/VMIDs not in an invalidation array are left cleared in the IO= TLB. + */ +static void arm_smmu_inv_free_asid(struct arm_smmu_inv *inv, bool flush) +{ + lockdep_assert_held(&arm_smmu_asid_lock); + + if (inv->type !=3D INV_TYPE_S1_ASID) + return; + if (refcount_read(&inv->users)) + return; + + if (flush) { + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D inv->nsize_opcode, + .tlbi.asid =3D inv->id, + }; + + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); + } + + /* Lastly, free the ASID as the last user detached */ + xa_erase(&arm_smmu_asid_xa, inv->id); +} + +static void arm_smmu_inv_free_vmid(struct arm_smmu_inv *inv, bool flush) +{ + lockdep_assert_held(&arm_smmu_asid_lock); + + /* Note S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR already */ + if (inv->type !=3D INV_TYPE_S2_VMID) + return; + if (refcount_read(&inv->users)) + return; + + if (flush) { + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D inv->nsize_opcode, + .tlbi.vmid =3D inv->id, + }; + + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); + } + + /* Lastly, free the VMID as the last user detached */ + ida_free(&inv->smmu->vmid_map, inv->id); +} + +static int arm_smmu_inv_alloc_asid(struct arm_smmu_inv *inv, void *data) +{ + struct arm_smmu_domain *smmu_domain =3D data; + struct arm_smmu_device *smmu =3D inv->smmu; + u32 asid; + int ret; + + lockdep_assert_held(&arm_smmu_asid_lock); + + /* Allocate a new iotlb_tag.id */ + WARN_ON(inv->type !=3D INV_TYPE_S1_ASID); + + ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, + XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); + if (ret) + return ret; + inv->id =3D asid; + return 0; +} + +static int arm_smmu_inv_alloc_vmid(struct arm_smmu_inv *inv, void *data) +{ + struct arm_smmu_device *smmu =3D inv->smmu; + int vmid; + + lockdep_assert_held(&arm_smmu_asid_lock); + + WARN_ON(inv->type !=3D INV_TYPE_S2_VMID); + + /* Reserve VMID 0 for stage-2 bypass STEs */ + vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, + GFP_KERNEL); + if (vmid < 0) + return vmid; + inv->id =3D vmid; + return 0; +} + static struct arm_smmu_inv * arm_smmu_master_build_inv(struct arm_smmu_master *master, enum arm_smmu_inv_type type, u32 id, ioasid_t ssid, @@ -3191,12 +3279,17 @@ arm_smmu_master_build_invs(struct arm_smmu_master *= master, bool ats_enabled, smmu_domain->cd.asid, IOMMU_NO_PASID, pgsize)) return NULL; + master->build_invs->alloc_id =3D arm_smmu_inv_alloc_asid; + master->build_invs->free_id =3D arm_smmu_inv_free_asid; + master->build_invs->smmu_domain =3D smmu_domain; break; case ARM_SMMU_DOMAIN_S2: if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, pgsize)) return NULL; + master->build_invs->alloc_id =3D arm_smmu_inv_alloc_vmid; + master->build_invs->free_id =3D arm_smmu_inv_free_vmid; break; default: WARN_ON(true); --=20 2.43.0