From nobody Mon Feb 9 20:36:27 2026 Received: from mail-244116.protonmail.ch (mail-244116.protonmail.ch [109.224.244.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 218E84508F6 for ; Tue, 20 Jan 2026 14:42:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768920134; cv=none; b=M/h1EeFvibA7HCcTDhLnnXs0OcNSQI6qlcoCHiRcywgw/L7hvSpdDNJo5sdfR5Zx6jNXS3d0WHoVSwLgIcRsDO5EZW5O3jIEUIfuXj0yY8acX3wx2TeKsjW8E1DCO9KnBbrKIqbDx/C9W9ibzcKmMSWQiMOxb12dsmRTFEPjudY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768920134; c=relaxed/simple; bh=Vp7wvXs1X+WpB+8Ieij5V9OSyokg9jwLq0n8VcCMx2Y=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=c8ZY92/gI8nGV4xUITs9mCLnbg2WY3yG/GuSZ/um53M7FF3jKkxSYdcFWDKITOEZ1z/QeZDr7gwsjba0mJRFr1VSsQF2Rg/zC46/X1oJ0bRUMfPgcnFBmXRpdraUlOpZ+ZXm+54V2cWs7NxSENvCG8LtblwJi/AevIBFygeJi3I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=j9Nrt0vZ; arc=none smtp.client-ip=109.224.244.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="j9Nrt0vZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1768920131; x=1769179331; bh=zjE8BIWza7IkaqtfQnzJQAf4sY9/wASLGKR2SLDOBjs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=j9Nrt0vZUnYd0sLoQ+qaXR/SNmzYEAnnzNvdrLtAefb2W8vA61Sih3MTJS7Lz9tE0 tfInP5XZZ9VQPFxjyNxkfYFD/dQpL5GXlK9lT2n4BhhuunFLus0tWrB1xlqWCkC0q8 2pIZ1X6sunBh+TP6VNCuraELFOgg7wLyVfMk5DJe3d0FcbhaZYlDqxHobvsqIvmxNU b+xrRmdPaBHlgXY0Bf0aM8JyMlJDruF2oiHqNl8GNtf3YYfimByEduMAmPdbt9TGSp WWOeHM/fCbcsifH7+plrRuBr2HsHypyx5iigt5M00aVyQA6Ldim88NOulhJ7UbTzW8 2cwIURTwO2w5g== Date: Tue, 20 Jan 2026 14:42:06 +0000 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Maciej Wieczor-Retman , Alexander Potapenko , linux-kernel@vger.kernel.org Subject: [PATCH v9 10/13] x86/mm: Initialize LAM_SUP Message-ID: <143b3ec86f2f356fa2b3357178d2486452808924.1768845098.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: c4eef6d0a91ce9ce99349cd83c67db1057d515b2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman To make use of KASAN's tag based mode on x86, Linear Address Masking (LAM) needs to be enabled. To do that the 28th bit in CR4 has to be set. Set the bit in early memory initialization. When launching secondary CPUs the LAM bit gets lost. To avoid this add it in a mask in head_64.S. The bitmask permits some bits of CR4 to pass from the primary CPU to the secondary CPUs without being cleared. Signed-off-by: Maciej Wieczor-Retman Acked-by: Alexander Potapenko --- Changelog v9: - Rename patch title so it fits the tip standards. Changelog v7: - Add Alexander's acked-by tag. Changelog v6: - boot_cpu_has() -> cpu_feature_enabled() arch/x86/kernel/head_64.S | 3 +++ arch/x86/mm/init.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 21816b48537c..c5a0bfbe280d 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -209,6 +209,9 @@ SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL) * there will be no global TLB entries after the execution." */ movl $(X86_CR4_PAE | X86_CR4_LA57), %edx +#ifdef CONFIG_ADDRESS_MASKING + orl $X86_CR4_LAM_SUP, %edx +#endif #ifdef CONFIG_X86_MCE /* * Preserve CR4.MCE if the kernel will enable #MC support. diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 8bf6ad4b9400..a8442b255481 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -764,6 +764,9 @@ void __init init_mem_mapping(void) probe_page_size_mask(); setup_pcid(); =20 + if (cpu_feature_enabled(X86_FEATURE_LAM) && IS_ENABLED(CONFIG_KASAN_SW_TA= GS)) + cr4_set_bits_and_update_boot(X86_CR4_LAM_SUP); + #ifdef CONFIG_X86_64 end =3D max_pfn << PAGE_SHIFT; #else --=20 2.52.0