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Mon, 14 Apr 2025 21:58:08 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 01/11] iommu/arm-smmu-v3: Pass in vmid to arm_smmu_make_s2_domain_ste() Date: Mon, 14 Apr 2025 21:57:36 -0700 Message-ID: <137d6eb98c2b7ea9d5cc2fb0f44f3c73065aa23a.1744692494.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992D:EE_|IA0PR12MB8373:EE_ X-MS-Office365-Filtering-Correlation-Id: 8155f1f0-cd47-4ebc-725b-08dd7bda2614 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|30052699003|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?SwhY8zp0IDjlz6a/cHfsgXamb7fOR3Y67jaepVIebjY/boSu4sBqjkpj/A5p?= =?us-ascii?Q?6WMxyUo8FQL4wMNwkpLzlP2cdFTpFxaZDkYg+/AyJxXWHHCZxL3F5RF/hkyq?= =?us-ascii?Q?zlLEpYIhChjNuDgSH/YXzljUIpis3IBylwA8zCWf9081QAG8Iy5pGsreCeGA?= =?us-ascii?Q?1/ZRP58AePkUSUIGMmQ/HkdeIx+6BNAZg8gGMY5k+wm2HHtBEhmdWUm/HYrg?= =?us-ascii?Q?ARWWiIEU1HkZBpKxtIEjC/4Ynnu2mu+RAhjHAgYZ0nGCC+dccar2HzsAiOdc?= =?us-ascii?Q?5nDbALZinYDY9v0mWZgXx82BSjxg4ajruBcBwwuBMhQgrkbAgjnJF+m5yLTP?= =?us-ascii?Q?UuT0sQDfJZ1f44d6YI1gfAutqRQPd1dG+uaDQzhxY6cQOYKRZc7iRYRaas1c?= =?us-ascii?Q?wLm+7YXgXn8nBVal4we8Zw3Xge6fw374+suU1Deu2NheI88xHBUtO5q5eeL8?= =?us-ascii?Q?AarRD3alLgfnjHjuIsabaeBKB5uprMqc/XD2+oA/AW7UC3+qpp+kxMeqxDbj?= =?us-ascii?Q?N073iOwAKOGKH3kk0Q92V3/+H0V3kg7L/ecWrzbOXihJdxFhk0R2OqTR0LC9?= =?us-ascii?Q?+AcMwJt4/nGBKSMI+7EBE6WTALQn1rT3NjJvpdnYrCxxwRohXjJsHCCIhbf6?= =?us-ascii?Q?hXR70isqv5SCZwvw6DDV4rIWaX0Kk/x+58W0xkiTitg35JJ2gCEJQr+7WfZm?= =?us-ascii?Q?xEm1KPtLS/OIVDeMdQcu2zL0A2TXnGYwRMu2e9DdVD0DcOYuHrps+gMdjcNs?= =?us-ascii?Q?6nAfzRazbonwv9rqbO5sK9mZp9v3r2qWrbDWJXGmZrA7GoMSyzLMOwUmBBqF?= =?us-ascii?Q?Saq8tkxoDLr3bri9t6jHUVGDkLePn59qI8HgpjWo3I/sB2MY3RjBNvZoG60P?= =?us-ascii?Q?r/b+Tqva1XOootwMoQ4cGUyW3Lxb+rnTJSk27Trs+pb8BybJCi13FxAffjw4?= =?us-ascii?Q?C8TbQ2Fk1J2NWGLkSWnVuqlHyiajASp5G8wXuYHzjyjxhQcCLR8BBQGcEq8I?= =?us-ascii?Q?iQ9EQSztQ7mLzG4e5T3mR/2ua+WvjNofqeQEgrCGJCB7thkcl0sMxs5k95FR?= =?us-ascii?Q?+mRjgx2ANz9m9KHPc1k/nVmWSl+Pb0qldPw0+DNr+iJEMPvjgqmBY3/hG5/g?= =?us-ascii?Q?bweU+fhDTKMzyjNeLqe1WnUeH5vWEFgLdOqjaBgM3NrdHxo4qp9PhBC0EHTE?= =?us-ascii?Q?exeX2r2tcrOZY4hjz9USdsXIRpBLW6PTJ2ggSGTdYcQaDvI1HPwvClZ2T6Hr?= =?us-ascii?Q?aGgTBr8Cuh6Vnsj5UosivwC0w0VR24pFx0wNJRl68Web2cHy65zbVmoFNn0G?= =?us-ascii?Q?OW8ucHWtJ/vz4xO7gerqmrX7JBFD4fobEiI5/U+5G+HZyZ+/9LyEU4exc3Fa?= =?us-ascii?Q?1WOe7nonUZWe35uXr0M7dqd8sDYtetFRx4GAYdyk8IQoOutVArwnFDzFlMRI?= =?us-ascii?Q?NOznNFtlvuwwTVrHErvFObvwFyRh+2qQaBZgnU2Ft6NhxaAVjlaYvEFOf15K?= =?us-ascii?Q?K9KphwdEN25y1hSaStynQ4YoEqgvZK8Iq5U1?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(30052699003)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:22.6408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8155f1f0-cd47-4ebc-725b-08dd7bda2614 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8373 Content-Type: text/plain; charset="utf-8" An stage-2 STE requires a vmid that has been so far allocated per domain, so arm_smmu_make_s2_domain_ste() has been extracting the vmid from the S2 domain. To share an S2 parent domain across vSMMUs in the same VM, a vmid will be no longer allocated for nor stored in the S2 domain, but per vSMMU, which means the arm_smmu_make_s2_domain_ste() can get a vmid either from an S2 domain (non nesting parent) or a vSMMU. Allow to pass in vmid explicitly to arm_smmu_make_s2_domain_ste(), giving its callers a chance to pick the vmid between a domain or a vSMMU. Add a WARN_ON_ONCE to validate the input vmid. Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 6 ++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 3 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++++--- 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index dd1ad56ce863..d4837a33fb81 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -894,7 +894,7 @@ struct arm_smmu_entry_writer_ops { void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain, + struct arm_smmu_domain *smmu_domain, u16 vmid, bool ats_enabled); =20 #if IS_ENABLED(CONFIG_KUNIT) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index e4fd8d522af8..d86dba6691e8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -34,8 +34,9 @@ static void arm_smmu_make_nested_cd_table_ste( struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) { - arm_smmu_make_s2_domain_ste( - target, master, nested_domain->vsmmu->s2_parent, ats_enabled); + arm_smmu_make_s2_domain_ste(target, master, + nested_domain->vsmmu->s2_parent, + nested_domain->vsmmu->vmid, ats_enabled); =20 target->data[0] =3D cpu_to_le64(STRTAB_STE_0_V | FIELD_PREP(STRTAB_STE_0_CFG, @@ -78,6 +79,7 @@ static void arm_smmu_make_nested_domain_ste( case STRTAB_STE_0_CFG_BYPASS: arm_smmu_make_s2_domain_ste(target, master, nested_domain->vsmmu->s2_parent, + nested_domain->vsmmu->vmid, ats_enabled); break; case STRTAB_STE_0_CFG_ABORT: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d2671bfd3798..7fac5a112c5c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -316,7 +316,8 @@ static void arm_smmu_test_make_s2_ste(struct arm_smmu_s= te *ste, io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.sl =3D 3; io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.tsz =3D 4; =20 - arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, ats_enabled); + arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, + smmu_domain.s2_cfg.vmid, ats_enabled); } =20 static void arm_smmu_v3_write_ste_test_s2_to_abort(struct kunit *test) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index c32c0b92dc69..1ec5efca1d42 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1656,10 +1656,9 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); =20 void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain, + struct arm_smmu_domain *smmu_domain, u16 vmid, bool ats_enabled) { - struct arm_smmu_s2_cfg *s2_cfg =3D &smmu_domain->s2_cfg; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr =3D @@ -1667,6 +1666,8 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, u64 vtcr_val; struct arm_smmu_device *smmu =3D master->smmu; =20 + WARN_ON_ONCE(!vmid); + memset(target, 0, sizeof(*target)); target->data[0] =3D cpu_to_le64( STRTAB_STE_0_V | @@ -1690,7 +1691,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); target->data[2] =3D cpu_to_le64( - FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | + FIELD_PREP(STRTAB_STE_2_S2VMID, vmid) | FIELD_PREP(STRTAB_STE_2_VTCR, vtcr_val) | STRTAB_STE_2_S2AA64 | #ifdef __BIG_ENDIAN @@ -2990,6 +2991,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) } case ARM_SMMU_DOMAIN_S2: arm_smmu_make_s2_domain_ste(&target, master, smmu_domain, + smmu_domain->s2_cfg.vmid, state.ats_enabled); arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); --=20 2.43.0