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Tue, 17 Mar 2026 00:59:30 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v13 1/8] iommu/arm-smmu-v3: Add a missing dma_wmb() for hitless STE update Date: Tue, 17 Mar 2026 00:59:16 -0700 Message-ID: <131b813acdfac4db4587538530a877358e634a2a.1773733797.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE8:EE_|DS5PPFFF21E27DC:EE_ X-MS-Office365-Filtering-Correlation-Id: ec80fa0c-f0e4-4f16-ff01-08de83fb2773 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|7416014|1800799024|18002099003|56012099003|22082099003|7053199007; X-Microsoft-Antispam-Message-Info: MCy1Xe4J0MpeOuaZTo3sS5N8+1FtMdGNxtKgKaU9pi+hJFH7oq/7Kj0IZhOQQJEspY5z5DyjOatJQ5zHlvNEkXAT+3BcOI5eIBVT7BBQ07pA/jZJ6hMTdPhkeHIO3sYMWwUaWBBmXOwQ8EECrcPi7EpNm5t3HnDkCpAAhKZCXBikIRRMPSiupnHBqLmTqHEDdxsP/nRvyAAh29hY6yCXdDL3bqKf1B+J+7a+wfOPOKQ7/UVew/UPQdh6ZIxF+tRS7t1FuHhEKs93s39ImJQ7lejsw7TSrMl5mOndrD5QU7VvwGDxxAabTHpFB+q35UK+2C0p/7s7uDdpChVzrZfSHcruFL1RL0dF2DOI4mWeELqpqHayjKbcWdAw9UQPrCcxE0fMtkVRfwkiQA7JHIheH/g/5Mk88OH4bMmdRYRM6+o1KrxDBxESxT9XAtrPNZyIGVsLvVc8RWaPlp/XD0X8E1buRZ7D6OIP2IM4t0z5KvHpULdWwibC50d6t/0YlMqVeXQysabU2ANwtP3AXb5EdIiIUwYf1D17dOtg4IDa/sCPpHslfkDYXBr4KwFqNhb9JXaYYkW12zfgTCIDbEkOmFJ5pwjXdsGBWyGIvmWY0BFeJtKxkaP4XriGFsM7s9AUT2Hlw+I7d9PeJfWimujGkkVK6ozgHwXFaKcDT3JuXb+A+PXN5ZNlkhds7ZrESqxTRIncOW47xGXuozyL0cBpgKSGuaJO2vG6IwDvOVZtnU6UtWTQZoe8jxFLDiHZzelzwH3WcfukQFYmZPjEo94/GQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(7416014)(1800799024)(18002099003)(56012099003)(22082099003)(7053199007);DIR:OUT;SFP:1101; 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charset="utf-8" When writing a new (previously invalid) valid IOPTE to a page table, then installing the page table into an STE hitlesslessly (e.g. in S2TTB field), there is a window before an STE invalidation, where the page-table may be accessed by SMMU but the new IOPTE is still siting in the CPU cache. This could occur when we allocate an iommu_domain and immediately install it hitlessly, while there would be no dma_wmb() for the page table memory prior to the earliest point of HW reading the STE. Fix it by adding a dma_wmb() prior to updating the STE. Fixes: 56e1a4cc2588 ("iommu/arm-smmu-v3: Add unit tests for arm_smmu_write_= entry") Cc: stable@vger.kernel.org Reported-by: Will Deacon Closes: https://lore.kernel.org/linux-iommu/aXdlnLLFUBwjT0V5@willie-the-tru= ck/ Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 4d00d796f0783..606abe051e68b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1236,6 +1236,13 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writ= er *writer, __le64 *entry, __le64 unused_update[NUM_ENTRY_QWORDS]; u8 used_qword_diff; =20 + /* + * Many of the entry structures have pointers to other structures that + * need to have their updates be visible before any writes of the entry + * happen. + */ + dma_wmb(); + used_qword_diff =3D arm_smmu_entry_qword_diff(writer, entry, target, unused_update); if (hweight8(used_qword_diff) =3D=3D 1) { --=20 2.43.0