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Thu, 18 Dec 2025 12:27:23 -0800 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v1 9/9] iommu/arm-smmu-v3: Allow sharing domain across SMMUs Date: Thu, 18 Dec 2025 12:26:55 -0800 Message-ID: <1274d3dbf29ecb23dbcc8efcd56ea63f94662737.1766088963.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|SA3PR12MB7858:EE_ X-MS-Office365-Filtering-Correlation-Id: fa150a49-4be6-4e0c-490a-08de3e73e8fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KVpLxryPzsoXYDAw4a7o+4+mZ43MYYVbb7H5dHTJYgWsXXg9w6wuQ7uQc8cO?= =?us-ascii?Q?OJRmlTJUIQE9ehR4ZCcIKnG7Psl2Ha+kg/zqbH15R4Pv/5t4hfipsi0Q7vBn?= =?us-ascii?Q?84ou76PPjLlH+AEsnyATnaMt+Y/AU/9vrvMVxUW97dazk+Cu8vueiHWNaW4e?= =?us-ascii?Q?536ztMay0iye8d92DE220lIVXp3LRy4T+kFnguSWCJlqMRO0fCZ0qf6DFkXI?= =?us-ascii?Q?TOYGsh9GOtkucH0WuuNp6R0bpe83kKrGmpRVzQC49+qVqc3Fjbg9A9WNdbn9?= =?us-ascii?Q?jgWjQfIHRDqK5su27gjzJbTsyIkmTka4Kos9LryVAS6uwxcEb0mXpBPN+uIp?= =?us-ascii?Q?Y9P6aO0wi3DnCX0qSGCIwA9E+GbGAi2mLc4ES6kW8ggpTUiUtHpk97jKToa9?= =?us-ascii?Q?Dw4BWYc9QVw5P4uXs00dMpm0arqWLHisUrwmEMhoUFB89LXoce9FsxKLehiJ?= =?us-ascii?Q?rThk3HpPLTmEFRJMN5dgQ2CxiGjnH7euKfv+t2KstkHxJwaTT6imGL8BZygJ?= =?us-ascii?Q?pELShqzyThPPXWmgH0zrTAw/zOx5BbwMDVcXPArZPo1K5zbwkuUwowqvwIRF?= =?us-ascii?Q?ua9+SSfM81Wk+2IX2+QCl/Wj3K3yPuu0MTemy/8yH4SUi/qqAR73GnRybA8Z?= =?us-ascii?Q?dhCCD+jExCTZnHOYYuZcRTbJBoUzKW4fdWjrwEzASjrgxffoi6j42gPAuGnX?= =?us-ascii?Q?M5TqBjRbwFf6VAMQZi8AklWhcUVcvHJh0A3dmd7T8t9gb/VgxO/4E24lXzAy?= =?us-ascii?Q?XoOwtkUL4vpoz+YHOkPRKWZsDIoPp+s07wE2YmbhlPAs9nIxk5H/BLUyYyJX?= =?us-ascii?Q?UBbtSXp4kAJUhYRdiB/cqjtwSfJ1SftQYTnEtC7F+TuCQagLqzXvRU5ZObW+?= =?us-ascii?Q?NiE5d/jtKc7hvbmXqgsfvctZAahvimVuzD7F5rPyZ9oKAldrXsPWV5x2u3V9?= =?us-ascii?Q?MxctynIHgjXHUi5Vof21CwklTHzkIjf5CG3iuYK4XSlC2LpRpI11ag79/D3Z?= =?us-ascii?Q?unXLScrhJLG8sk6BKDfD495NJ8npq2SA/yW+Dvx8eGW+hicc0HZ80gcYyadK?= =?us-ascii?Q?uJaYF9vy5aDppfUo+IbFYXZWWjbSfAd/NS6o9flYPSYqn8rNG+bZj25ImzPH?= =?us-ascii?Q?i6cGFK/Kb/D9GfNUTTkh5p7VADgXx3FwNs9bA1ciDgQtk3we3/vl5glWsjtd?= =?us-ascii?Q?7baiZfGSFdJ/TlAtsN8qeXvG04KPwrjnwNQrgic3kraDh+uzhQTEUo2Unemb?= =?us-ascii?Q?PAC2GpViv4W3hvNJWvFBKmJxr4xq9JOEx5zcwjHfrS95VT5grwqiI0NFqOoY?= =?us-ascii?Q?kQaCcYgwNVwzudasg0rBEsB/lbHrRV1vxcvAvfAPoXqkiVNDcQIrFXtttSWi?= =?us-ascii?Q?t21FjJdNvJY9+M/qN0gmyx0iwp9eqg2emAf9xGy3TcRfl7q4AhZkauHfZv5B?= =?us-ascii?Q?xG5W+28G7LyCIPHq3J18OtNMuXODAoR+ZatJ+Zn5kYvXpeK6AUCLfd3f/zzH?= =?us-ascii?Q?yagPA+4GTLE7pcWv/0cIcSq/rjtPc15B1aKBS9zOhgxFyhGmcKD90E/C8FGa?= =?us-ascii?Q?ayNbzNeuRZX6XGalLQw=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:48.3125 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa150a49-4be6-4e0c-490a-08de3e73e8fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7858 Content-Type: text/plain; charset="utf-8" VMM needs a domain holding the mappings between gPA to hPA. It can be an S1 domain or an S2 nesting parent domain, depending on whether the VM is built with a vSMMU or not. Given that the IOAS for this gPA mapping is the same across SMMU instances, this domain can be shared across devices even if they sit behind different SMMUs, so long as the underlying page table is compatible between the SMMU instances. There is no direct information about the page table from the master device, but a comparison can be done between the physical SMMU that the domain was allocated for and the physical SMMU that the device is behind. Replace the smmu test in arm_smmu_attach_dev() and arm_vsmmu_init() with a compatibility test for the S1 and S2 cases respectively. The compatibility test goes through the physical SMMU parameters that were used to decide the page table formats. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 20 +++++++++++++++++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 4d7b7eb52dfd..d64e4e7c162d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -992,6 +992,26 @@ struct arm_smmu_nested_domain { __le64 ste[2]; }; =20 +static inline bool +arm_smmu_domain_can_share(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *new_smmu) +{ + struct arm_smmu_device *base_smmu =3D smmu_domain->smmu; + + if (base_smmu =3D=3D new_smmu) + return true; + /* Only support identical SMMUs for now */ + if (base_smmu->features !=3D new_smmu->features) + return false; + if (base_smmu->iommu.ops !=3D new_smmu->iommu.ops) + return false; + if (base_smmu->pgsize_bitmap !=3D new_smmu->pgsize_bitmap) + return false; + if (base_smmu->ias > new_smmu->ias || base_smmu->oas > new_smmu->oas) + return false; + return true; +} + /* The following are exposed for testing purposes. */ struct arm_smmu_entry_writer_ops; struct arm_smmu_entry_writer { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 1c877d30f86e..f2318e31d875 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -462,7 +462,7 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, container_of(viommu->iommu_dev, struct arm_smmu_device, iommu); struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent_domain); =20 - if (s2_parent->smmu !=3D smmu) + if (!arm_smmu_domain_can_share(s2_parent, smmu)) return -EINVAL; =20 vsmmu->smmu =3D smmu; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 04e21af9c578..ab329614da1f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3684,7 +3684,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, state.master =3D master =3D dev_iommu_priv_get(dev); smmu =3D master->smmu; =20 - if (smmu_domain->smmu !=3D smmu) + if (!arm_smmu_domain_can_share(smmu_domain, smmu)) return -EINVAL; =20 if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { --=20 2.43.0