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Peter Anvin" , Dave Hansen , Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Borislav Petkov , "Edgecombe, Rick P" , Oleg Vasilev , Arthur Petukhovsky , Stefan Radig , Misha Sakhnov References: <7d0d307d-71eb-4913-8023-bccc7a8a4a3d@neon.tech> Content-Language: en-US In-Reply-To: <7d0d307d-71eb-4913-8023-bccc7a8a4a3d@neon.tech> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Preparation for returning errors when alloc_low_page() fails. phys_pte_init() is excluded because it can't fail, and it's useful for it to return 'paddr_last' instead. This patch depends on the previous patch ("x86/mm: Update mapped addresses in phys_{pmd,pud}_init()"). Signed-off-by: Em Sharnoff --- Changleog: - v2: Switch from special-casing zero value to using ERR_PTR() - v3: Fix -Wint-conversion errors - v4: Switch return type to int, split alloc handling into separate patch. --- arch/x86/include/asm/pgtable.h | 2 +- arch/x86/mm/init.c | 14 +++-- arch/x86/mm/init_32.c | 4 +- arch/x86/mm/init_64.c | 100 ++++++++++++++++++++++----------- arch/x86/mm/mem_encrypt_amd.c | 8 ++- arch/x86/mm/mm_internal.h | 8 +-- 6 files changed, 87 insertions(+), 49 deletions(-) diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h index 138d55f48a4f..b09194c42688 100644 --- a/arch/x86/include/asm/pgtable.h +++ b/arch/x86/include/asm/pgtable.h @@ -1244,7 +1244,7 @@ extern int direct_gbpages; void init_mem_mapping(void); void early_alloc_pgt_buf(void); void __init poking_init(void); -void init_memory_mapping(unsigned long start, unsigned long end, pgprot_t = prot); +int init_memory_mapping(unsigned long start, unsigned long end, pgprot_t p= rot); =20 #ifdef CONFIG_X86_64 extern pgd_t trampoline_pgd_entry; diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 1461873b44f1..1dc8fbd8cb63 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -543,11 +543,12 @@ void add_paddr_range_mapped(unsigned long start_paddr= , unsigned long end_paddr) * This runs before bootmem is initialized and gets pages directly from * the physical memory. To access them they are temporarily mapped. */ -void __ref init_memory_mapping(unsigned long start, +int __ref init_memory_mapping(unsigned long start, unsigned long end, pgprot_t prot) { struct map_range mr[NR_RANGE_MR]; int nr_range, i; + int ret; =20 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", start, end - 1); @@ -555,11 +556,14 @@ void __ref init_memory_mapping(unsigned long start, memset(mr, 0, sizeof(mr)); nr_range =3D split_mem_range(mr, 0, start, end); =20 - for (i =3D 0; i < nr_range; i++) - kernel_physical_mapping_init(mr[i].start, mr[i].end, - mr[i].page_size_mask, prot); + for (i =3D 0; i < nr_range; i++) { + ret =3D kernel_physical_mapping_init(mr[i].start, mr[i].end, + mr[i].page_size_mask, prot); + if (ret) + return ret; + } =20 - return; + return 0; } =20 /* diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index 4427ac433041..57bd154c206d 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c @@ -245,7 +245,7 @@ static inline int is_x86_32_kernel_text(unsigned long a= ddr) * of max_low_pfn pages, by creating page tables starting from address * PAGE_OFFSET: */ -void __init +int __init kernel_physical_mapping_init(unsigned long start, unsigned long end, unsigned long page_size_mask, @@ -384,7 +384,7 @@ kernel_physical_mapping_init(unsigned long start, } =20 add_paddr_range_mapped(start, last_map_addr); - return; + return 0; } =20 #ifdef CONFIG_HIGHMEM diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index e729108bee30..b18ab2dcc799 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -503,7 +503,7 @@ phys_pte_init(pte_t *pte_page, unsigned long paddr, uns= igned long paddr_end, * Create PMD level page table mapping for physical addresses. The virtual * and physical address have to be aligned at this level. */ -static void __meminit +static int __meminit phys_pmd_init(pmd_t *pmd_page, unsigned long paddr, unsigned long paddr_en= d, unsigned long page_size_mask, pgprot_t prot, bool init) { @@ -585,7 +585,7 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long paddr, uns= igned long paddr_end, * It is idempotent, so this is ok. */ add_paddr_range_mapped(paddr_first, paddr_last); - return; + return 0; } =20 /* @@ -593,12 +593,14 @@ phys_pmd_init(pmd_t *pmd_page, unsigned long paddr, u= nsigned long paddr_end, * and physical address do not have to be aligned at this level. KASLR can * randomize virtual addresses up to this level. */ -static void __meminit +static int __meminit phys_pud_init(pud_t *pud_page, unsigned long paddr, unsigned long paddr_en= d, unsigned long page_size_mask, pgprot_t _prot, bool init) { unsigned long pages =3D 0, paddr_next; unsigned long vaddr =3D (unsigned long)__va(paddr); + int ret; + int i =3D pud_index(vaddr); =20 for (; i < PTRS_PER_PUD; i++, paddr =3D paddr_next) { @@ -623,8 +625,10 @@ phys_pud_init(pud_t *pud_page, unsigned long paddr, un= signed long paddr_end, if (!pud_none(*pud)) { if (!pud_leaf(*pud)) { pmd =3D pmd_offset(pud, 0); - phys_pmd_init(pmd, paddr, paddr_end, - page_size_mask, prot, init); + ret =3D phys_pmd_init(pmd, paddr, paddr_end, + page_size_mask, prot, init); + if (ret) + return ret; continue; } /* @@ -660,33 +664,39 @@ phys_pud_init(pud_t *pud_page, unsigned long paddr, u= nsigned long paddr_end, } =20 pmd =3D alloc_low_page(); - phys_pmd_init(pmd, paddr, paddr_end, - page_size_mask, prot, init); + ret =3D phys_pmd_init(pmd, paddr, paddr_end, + page_size_mask, prot, init); =20 spin_lock(&init_mm.page_table_lock); pud_populate_init(&init_mm, pud, pmd, init); spin_unlock(&init_mm.page_table_lock); + + /* + * Bail only after updating pud to keep progress from pmd across + * retries. + */ + if (ret) + return ret; } =20 update_page_count(PG_LEVEL_1G, pages); =20 - return; + return 0; } =20 -static void __meminit +static int __meminit phys_p4d_init(p4d_t *p4d_page, unsigned long paddr, unsigned long paddr_en= d, unsigned long page_size_mask, pgprot_t prot, bool init) { unsigned long vaddr, vaddr_end, vaddr_next, paddr_next; + int ret; =20 vaddr =3D (unsigned long)__va(paddr); vaddr_end =3D (unsigned long)__va(paddr_end); =20 - if (!pgtable_l5_enabled()) { - phys_pud_init((pud_t *) p4d_page, paddr, paddr_end, - page_size_mask, prot, init); - return; - } + if (!pgtable_l5_enabled()) + return phys_pud_init((pud_t *) p4d_page, paddr, paddr_end, + page_size_mask, prot, init); =20 for (; vaddr < vaddr_end; vaddr =3D vaddr_next) { p4d_t *p4d =3D p4d_page + p4d_index(vaddr); @@ -708,24 +718,33 @@ phys_p4d_init(p4d_t *p4d_page, unsigned long paddr, u= nsigned long paddr_end, =20 if (!p4d_none(*p4d)) { pud =3D pud_offset(p4d, 0); - phys_pud_init(pud, paddr, __pa(vaddr_end), - page_size_mask, prot, init); + ret =3D phys_pud_init(pud, paddr, __pa(vaddr_end), + page_size_mask, prot, init); + if (ret) + return ret; continue; } =20 pud =3D alloc_low_page(); - phys_pud_init(pud, paddr, __pa(vaddr_end), - page_size_mask, prot, init); + ret =3D phys_pud_init(pud, paddr, __pa(vaddr_end), + page_size_mask, prot, init); =20 spin_lock(&init_mm.page_table_lock); p4d_populate_init(&init_mm, p4d, pud, init); spin_unlock(&init_mm.page_table_lock); + + /* + * Bail only after updating p4d to keep progress from pud across + * retries. + */ + if (ret) + return ret; } =20 - return; + return 0; } =20 -static void __meminit +static int __meminit __kernel_physical_mapping_init(unsigned long paddr_start, unsigned long paddr_end, unsigned long page_size_mask, @@ -733,6 +752,7 @@ __kernel_physical_mapping_init(unsigned long paddr_star= t, { bool pgd_changed =3D false; unsigned long vaddr, vaddr_start, vaddr_end, vaddr_next; + int ret; =20 vaddr =3D (unsigned long)__va(paddr_start); vaddr_end =3D (unsigned long)__va(paddr_end); @@ -746,14 +766,16 @@ __kernel_physical_mapping_init(unsigned long paddr_st= art, =20 if (pgd_val(*pgd)) { p4d =3D (p4d_t *)pgd_page_vaddr(*pgd); - phys_p4d_init(p4d, __pa(vaddr), __pa(vaddr_end), - page_size_mask, prot, init); + ret =3D phys_p4d_init(p4d, __pa(vaddr), __pa(vaddr_end), + page_size_mask, prot, init); + if (ret) + return ret; continue; } =20 p4d =3D alloc_low_page(); - phys_p4d_init(p4d, __pa(vaddr), __pa(vaddr_end), - page_size_mask, prot, init); + ret =3D phys_p4d_init(p4d, __pa(vaddr), __pa(vaddr_end), + page_size_mask, prot, init); =20 spin_lock(&init_mm.page_table_lock); if (pgtable_l5_enabled()) @@ -761,15 +783,22 @@ __kernel_physical_mapping_init(unsigned long paddr_st= art, else p4d_populate_init(&init_mm, p4d_offset(pgd, vaddr), (pud_t *) p4d, init); - spin_unlock(&init_mm.page_table_lock); + + /* + * Bail only after updating pgd/p4d to keep progress from p4d + * across retries. + */ + if (ret) + return ret; + pgd_changed =3D true; } =20 if (pgd_changed) sync_global_pgds(vaddr_start, vaddr_end - 1); =20 - return; + return 0; } =20 =20 @@ -779,13 +808,13 @@ __kernel_physical_mapping_init(unsigned long paddr_st= art, * The virtual and physical addresses have to be aligned on PMD level * down. */ -void __meminit +int __meminit kernel_physical_mapping_init(unsigned long paddr_start, unsigned long paddr_end, unsigned long page_size_mask, pgprot_t prot) { - __kernel_physical_mapping_init(paddr_start, paddr_end, - page_size_mask, prot, true); + return __kernel_physical_mapping_init(paddr_start, paddr_end, + page_size_mask, prot, true); } =20 /* @@ -794,14 +823,14 @@ kernel_physical_mapping_init(unsigned long paddr_star= t, * when updating the mapping. The caller is responsible to flush the TLBs = after * the function returns. */ -void __meminit +int __meminit kernel_physical_mapping_change(unsigned long paddr_start, unsigned long paddr_end, unsigned long page_size_mask) { - __kernel_physical_mapping_init(paddr_start, paddr_end, - page_size_mask, PAGE_KERNEL, - false); + return __kernel_physical_mapping_init(paddr_start, paddr_end, + page_size_mask, PAGE_KERNEL, + false); } =20 #ifndef CONFIG_NUMA @@ -980,8 +1009,11 @@ int arch_add_memory(int nid, u64 start, u64 size, { unsigned long start_pfn =3D start >> PAGE_SHIFT; unsigned long nr_pages =3D size >> PAGE_SHIFT; + int ret; =20 - init_memory_mapping(start, start + size, params->pgprot); + ret =3D init_memory_mapping(start, start + size, params->pgprot); + if (ret) + return ret; =20 return add_pages(nid, start_pfn, nr_pages, params); } diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index 7490ff6d83b1..04e0b92eb9ad 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -444,9 +444,11 @@ static int __init early_set_memory_enc_dec(unsigned lo= ng vaddr, * kernel_physical_mapping_change() does not flush the TLBs, so * a TLB flush is required after we exit from the for loop. */ - kernel_physical_mapping_change(__pa(vaddr & pmask), - __pa((vaddr_end & pmask) + psize), - split_page_size_mask); + ret =3D kernel_physical_mapping_change(__pa(vaddr & pmask), + __pa((vaddr_end & pmask) + psize), + split_page_size_mask); + if (ret) + return ret; } =20 ret =3D 0; diff --git a/arch/x86/mm/mm_internal.h b/arch/x86/mm/mm_internal.h index 6fea5f7edd48..dacf3c924fbd 100644 --- a/arch/x86/mm/mm_internal.h +++ b/arch/x86/mm/mm_internal.h @@ -12,10 +12,10 @@ void early_ioremap_page_table_range_init(void); =20 void add_paddr_range_mapped(unsigned long start_paddr, unsigned long end_p= addr); =20 -void kernel_physical_mapping_init(unsigned long start, unsigned long end, - unsigned long page_size_mask, pgprot_t prot); -void kernel_physical_mapping_change(unsigned long start, unsigned long end, - unsigned long page_size_mask); +int kernel_physical_mapping_init(unsigned long start, unsigned long end, + unsigned long page_size_mask, pgprot_t prot); +int kernel_physical_mapping_change(unsigned long start, unsigned long end, + unsigned long page_size_mask); void zone_sizes_init(void); =20 extern int after_bootmem; --=20 2.39.5