From nobody Mon Apr 13 21:42:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2A6739B978; Wed, 4 Mar 2026 14:04:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772633056; cv=none; b=AbWITIOhDWryZyOhGrGYXjS99VWYz+Y46T3jS+WqSNISFD8zZaccsMdVJNlabOU7ngHqbLdNuu39mSagNot0Jn2T5/iSROudoqrrfzazVS9XgkaC2iR77XQE88r3XBEB657lqixTw4emV9zg9EJEbIsU2ABbeCBIKpb9/3Jic2M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772633056; c=relaxed/simple; bh=GkBJw/OUo0Oa+IzoSIatQ7hMK7OHe6CVg7wKYrKwZHs=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=Mg3jWnEC6U7r7qosNlHpiEz7igdEKmf7PBVcPdhJlqv2ZmGgKLtyg3NMahUp8CsJV0Xuqg3GvDV1OunGx66iMzSNTiaqPo480AfwZbwRJKdBC30ex4xh/utFKU6L/0O5hX5Fdm4s1Y2qdQ2QzZwPb7YSAofU4BakUq5gSvTgQIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95097C4CEF7; Wed, 4 Mar 2026 14:04:14 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH] dt-bindings: interrupt-controller: arm,gic-v3: Fix EPPI range Date: Wed, 4 Mar 2026 15:04:10 +0100 Message-ID: <107183629106ad392e17fdf539a3d79873024377.1772632987.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to the "Arm Generic Interrupt Controller (GIC) Architecture Specification, v3 and v3", revision H.b[1], there can be only 64 Extended PPI interrupts. [1] https://developer.arm.com/documentation/ihi0069/hb/ Fixes: 4b049063e0bcbfd3 ("dt-bindings: interrupt-controller: arm,gic-v3: De= scribe EPPI range support") Signed-off-by: Geert Uytterhoeven Acked-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= -v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v= 3.yaml index bfd30aae682bf3f7..360a0643a0b567a4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -50,7 +50,7 @@ properties: The 2nd cell contains the interrupt number for the interrupt type. SPI interrupts are in the range [0-987]. PPI interrupts are in the range [0-15]. Extended SPI interrupts are in the range [0-1023]. - Extended PPI interrupts are in the range [0-127]. + Extended PPI interrupts are in the range [0-63]. =20 The 3rd cell is the flags, encoded as follows: bits[3:0] trigger type and level flags. --=20 2.43.0