From nobody Thu Apr 9 15:03:54 2026 Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 909283FD15F for ; Mon, 2 Mar 2026 15:35:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772465704; cv=none; b=LS1vRyykKzxGLFpZj5/xbi61bSUg6rp9Xkl58R9sfHk8VLpQYhcBW3g++exZjH7Lll4WwazZdTGSKcYOL0Uhrn7kTVIIcf9ThIKqqLLLlVU910xgrPDd8mHTHLzRdOljwIUiJdIX1AlT4fKt4dPzWZDnBKz2cwtQbxNCbUsBWVY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772465704; c=relaxed/simple; bh=m9hKwZPyuEzZ8uN5Kiu7EUVvRypg4VjLdMDA4EOO38M=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Yi4gMw+1JuyI2d82LjzF6mRR90Pp6ewtATzBw+xnBD6ByHRRma+WdIi3+adXnFigb2D55dDQPobP8Gc+tfQckO1HyZI9+BPOq4tlT87vqIlTH00viN5l/it7aa3q/kNabstL13UpT70qjwRdtsQSM+atLMtA9G5OzNidtKNQlbo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=a3MstSuK; arc=none smtp.client-ip=185.70.43.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="a3MstSuK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1772465701; x=1772724901; bh=I52Q+KEeiiDsU8FQqfmtTt6VSyBmS0haSG3uGXRUd04=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=a3MstSuKgKqnbSz5w7rT1m2R9aitU7JnDFwPaeOWXcddo+dvko1gcsFao8oXxNtIN JBhDkef8+iGIILXAmMz69H5DEaRKGIhh6QmxmbGP+t+w5jKmMEzo9XKljcQJJ7OiBo 0np1GFKuSnqrz5LyQ83WuRL1QhvbW4Wjt+BphY8U0f5gXydfG3bQy5pi1u4QbJ6+tO 9xDAtNU28sz3a7oAy8RRMJBzdiPFu+WY4yGnUcEoNdYrIABsECcqyT/mPXz6VlK6Lg 5a5H+/dtC9fPXXPM9K67F/3lM3Yk/4QSQEuketR15B7v8WqUo11f/2I6lGzTN0IKjY Q5u/g9yAGoZAw== Date: Mon, 02 Mar 2026 15:34:56 +0000 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Maciej Wieczor-Retman , linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] x86/mm: Cleanup comments where LAM_U48 is mentioned Message-ID: <0fb7ee92e073b76fa51960ba94dd3215c7155d51.1772465456.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 369533781bbd62e3cd36edb2c144b1b0db403c91 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman For simplicity only the LAM_U57 mode is implemented in the kernel. No matter whether the enabled paging mode is 5-level or 4-level the masked tag bits are the same as on a 5-level system. Remove two mentions of LAM_U48 which implied that it could be enabled. Signed-off-by: Maciej Wieczor-Retman --- arch/x86/include/asm/mmu.h | 2 +- arch/x86/include/asm/tlbflush.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 0fe9c569d171..9dcfce439c19 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -49,7 +49,7 @@ typedef struct { unsigned long flags; =20 #ifdef CONFIG_ADDRESS_MASKING - /* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */ + /* Active LAM mode: X86_CR3_LAM_U57 or 0 (disabled) */ unsigned long lam_cr3_mask; =20 /* Significant bits of the virtual address. Excludes tag bits. */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 5a3cdc439e38..94c5ca1febaf 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -110,7 +110,7 @@ struct tlb_state { /* * Active LAM mode. * - * X86_CR3_LAM_U57/U48 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM + * X86_CR3_LAM_U57 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM * disabled. */ u8 lam; --=20 2.53.0