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Mon, 30 Jun 2025 14:54:02 -0700 (PDT) Received: from geday ([2804:7f2:800b:4851::dead:c001]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4a81b8ea2a4sm21766721cf.75.2025.06.30.14.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jun 2025 14:54:02 -0700 (PDT) Date: Mon, 30 Jun 2025 18:53:55 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , Neil Armstrong , Valmantas Paliksa , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v9 2/4] PCI: rockchip: Set Target Link Speed before retraining Message-ID: <0afa6bc47b7f50e2e81b0b47d51c66feb0fb565f.1751320056.git.geraldogabriel@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current code may fail 5.0GT/s retraining if Target Link Speed is set to 2.5 GT/s in Link Control and Status Register 2. Set it to 5.0 GT/s accordingly. Tested-by: Robin Murphy Signed-off-by: Geraldo Nascimento --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index 65653218b9ab..25890f6c0e17 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -341,6 +341,10 @@ static int rockchip_pcie_host_init_port(struct rockchi= p_pcie *rockchip) * Enable retrain for gen2. This should be configured only after * gen1 finished. */ + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL2); + status &=3D ~PCI_EXP_LNKCTL2_TLS; + status |=3D PCI_EXP_LNKCTL2_TLS_5_0GT; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= 2);=09 status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL); status |=3D PCI_EXP_LNKCTL_RL; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= ); --=20 2.49.0