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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:24:31.7216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: afdf6543-2e21-4047-0bb2-08ddc5edaaaf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9728 Content-Type: text/plain; charset="utf-8" The kit is using k24 SOM by default and it is used for motor control and DSP applications. K24 SOM is also possible to used with kv260 and kr260 CC which are also wired in Makefile. Signed-off-by: Michal Simek --- https://www.amd.com/en/products/system-on-modules/kria/k24/k24i-industrial.= html https://www.amd.com/en/products/system-on-modules/kria/k24/kd240-drives-sta= rter-kit.html --- arch/arm64/boot/dts/xilinx/Makefile | 15 + .../boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso | 390 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-sm-k24-revA.dts | 23 ++ .../boot/dts/xilinx/zynqmp-smk-k24-revA.dts | 21 + 4 files changed, 449 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xili= nx/Makefile index 5e84e3c725e2..70fac0b276df 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -39,4 +39,19 @@ dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-k= r-g-revA.dtb zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs :=3D zynqmp-smk-k26-revA.dtb zynqmp= -sck-kr-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-kr-g-revB.dtb =20 +zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs :=3D zynqmp-sm-k24-revA.dtb zynqmp-s= ck-kd-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k24-revA-sck-kd-g-revA.dtb +zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs :=3D zynqmp-smk-k24-revA.dtb zynqmp= -sck-kd-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k24-revA-sck-kd-g-revA.dtb + +zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs :=3D zynqmp-sm-k24-revA.dtb zynqmp-s= ck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k24-revA-sck-kv-g-revB.dtb +zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs :=3D zynqmp-smk-k24-revA.dtb zynqmp= -sck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k24-revA-sck-kv-g-revB.dtb + +zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs :=3D zynqmp-sm-k24-revA.dtb zynqmp-s= ck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k24-revA-sck-kr-g-revB.dtb +zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs :=3D zynqmp-smk-k24-revA.dtb zynqmp= -sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k24-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) +=3D versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/ar= m64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso new file mode 100644 index 000000000000..02be5e1e8686 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KD240 revA Carrier Card + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible =3D "xlnx,zynqmp-sk-kd240-rev1", + "xlnx,zynqmp-sk-kd240-revB", + "xlnx,zynqmp-sk-kd240-revA", + "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; + model =3D "ZynqMP KD240 revA/B/1"; + + aliases { + ethernet0 =3D "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u3 { + compatible =3D "iio-hwmon"; + io-channels =3D <&u3 0>, <&u3 1>, <&u3 2>; + }; + + clk_26: clock2 { /* u17 - USB */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; +}; + +&can0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can0_default>; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1_default>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + scl-gpios =3D <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u3: ina260@40 { /* u3 */ + compatible =3D "ti,ina260"; + #io-channel-cells =3D <1>; + label =3D "ina260-u14"; + reg =3D <0x40>; + }; + + slg7xl45106: gpio@11 { /* u13 - reset logic */ + compatible =3D "dlg,slg7xl45106"; + reg =3D <0x11>; + label =3D "resetchip"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "USB0_PHY_RESET_B", "", + "SD_RESET_B", "USB0_HUB_RESET_B", + "", "PS_GEM0_RESET_B", + "", ""; + }; + + hub: usb-hub@2d { /* u36 */ + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; +}; + +/* USB 3.0 */ +&psgtr { + status =3D "okay"; + /* usb */ + clocks =3D <&clk_26>; + clock-names =3D "ref2"; +}; + +&usb0 { /* mio52 - mio63 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb0_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios =3D <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_0 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + i2c-bus =3D <&hub>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + i2c-bus =3D <&hub>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&gem1 { /* mdio mio50/51 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gem1_default>; + assigned-clock-rates =3D <250000000>; + + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + phy0: ethernet-phy@8 { /* Adin u31 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id0283.bc30"; + reg =3D <8>; + adi,rx-internal-delay-ps =3D <2000>; + adi,tx-internal-delay-ps =3D <2000>; + adi,fifo-depth-bits =3D <8>; + reset-assert-us =3D <10>; + reset-deassert-us =3D <5000>; + reset-gpios =3D <&gpio 77 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* 2 more ethernet phys u32@2 and u34@3 */ + +&pinctrl0 { /* required by spec */ + status =3D "okay"; + + pinctrl_can0_default: can0-default { + mux { + function =3D "can0"; + groups =3D "can0_16_grp"; + }; + + conf { + groups =3D "can0_16_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO66"; + bias-pull-up; + }; + + conf-tx { + pins =3D "MIO67"; + bias-pull-up; + drive-strength =3D <4>; + }; + }; + + pinctrl_uart0_default: uart0-default { + conf { + groups =3D "uart0_17_grp"; + slew-rate =3D ; + power-source =3D ; + drive-strength =3D <12>; + }; + + conf-rx { + pins =3D "MIO70"; + bias-high-impedance; + }; + + conf-tx { + pins =3D "MIO71"; + bias-disable; + }; + + mux { + groups =3D "uart0_17_grp"; + function =3D "uart0"; + }; + }; + + pinctrl_uart1_default: uart1-default { + conf { + groups =3D "uart1_9_grp"; + slew-rate =3D ; + power-source =3D ; + drive-strength =3D <12>; + }; + + conf-rx { + pins =3D "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins =3D "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups =3D "uart1_9_grp"; + function =3D "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups =3D "i2c1_6_grp"; + bias-pull-up; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "i2c1_6_grp"; + function =3D "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + function =3D "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups =3D "ethernet1_0_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO45", "MIO46", "MIO47", "MIO48"; + bias-disable; + low-power-disable; + }; + + conf-bootstrap { + pins =3D "MIO44", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins =3D "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups =3D "mdio1_0_grp"; + slew-rate =3D ; + power-source =3D ; + bias-disable; + output-enable; + }; + + mux-mdio { + function =3D "mdio1"; + groups =3D "mdio1_0_grp"; + }; + + mux { + function =3D "ethernet1"; + groups =3D "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups =3D "usb0_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb0_0_grp"; + function =3D "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups =3D "usb1_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb1_0_grp"; + function =3D "usb1"; + }; + }; +}; + +&uart0 { + status =3D "okay"; + rts-gpios =3D <&gpio 72 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay =3D <10 10>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart0_default>; + assigned-clock-rates =3D <100000000>; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1_default>; +}; + +&zynqmp_dpsub { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-sm-k24-revA.dts new file mode 100644 index 000000000000..653bd9362264 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SM-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "zynqmp-sm-k26-revA.dts" + +/ { + model =3D "ZynqMP SM-K24 RevA/B/1"; + compatible =3D "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", + "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", + "xlnx,zynqmp"; + + memory@0 { + device_type =3D "memory"; /* 2GB */ + reg =3D <0 0 0 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts b/arch/arm6= 4/boot/dts/xilinx/zynqmp-smk-k24-revA.dts new file mode 100644 index 000000000000..7308983b15a0 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SMK-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "zynqmp-sm-k24-revA.dts" + +/ { + model =3D "ZynqMP SMK-K24 RevA"; + compatible =3D "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", + "xlnx,zynqmp"; +}; + +&sdhci0 { + status =3D "disabled"; +}; --=20 2.43.0