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From: <Ryan.Wanner@microchip.com>
To: <andrew+netdev@lunn.ch>, <davem@davemloft.net>, <edumazet@google.com>,
<kuba@kernel.org>, <pabeni@redhat.com>, <robh@kernel.org>,
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<Ryan.Wanner@microchip.com>
Subject: [PATCH 2/6] ARM: dts: microchip: sama7d65: Add gmac interfaces for
sama7d65 SoC
Date: Tue, 1 Apr 2025 09:13:18 -0700
Message-ID:
<05b107796b6f3a173d0dd0a5b2107b675cfd994e.1743523114.git.Ryan.Wanner@microchip.com>
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From: Ryan Wanner <Ryan.Wanner@microchip.com>
Add support for GMAC interfaces on SAMA7D65 SoC.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
arch/arm/boot/dts/microchip/sama7d65.dtsi | 32 +++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/=
microchip/sama7d65.dtsi
index b6710ccd4c36..cd17b838e179 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -169,6 +169,38 @@ dma1: dma-controller@e1614000 {
status =3D "disabled";
};
=20
+ gmac0: ethernet@e1618000 {
+ compatible =3D "microchip,sama7d65-gem", "microchip,sama7g5-gem";
+ reg =3D <0xe1618000 0x2000>;
+ interrupts =3D <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks =3D <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>=
, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>;
+ clock-names =3D "pclk", "hclk", "tx_clk", "tsu_clk";
+ assigned-clocks =3D <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>;
+ assigned-clock-rates =3D <125000000>, <200000000>;
+ status =3D "disabled";
+ };
+
+ gmac1: ethernet@e161c000 {
+ compatible =3D "microchip,sama7d65-gem", "microchip,sama7g5-gem";
+ reg =3D <0xe161c000 0x2000>;
+ interrupts =3D <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks =3D <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>=
,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>;
+ clock-names =3D "pclk", "hclk", "tx_clk", "tsu_clk";
+ assigned-clocks =3D <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>;
+ assigned-clock-rates =3D <125000000>, <200000000>;
+ status =3D "disabled";
+ };
+
pit64b0: timer@e1800000 {
compatible =3D "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
reg =3D <0xe1800000 0x100>;
--=20
2.43.0