From nobody Mon Apr 6 09:12:34 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF7EB2DE6FF for ; Sat, 21 Mar 2026 10:14:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774088043; cv=none; b=PapyfEr4Ytk5k9mfq8jkrC9PUWOCe9+eCJdQnO7JYJiOec9FJHAhPGuTsLH3mEqIVj4xZJIFPubu5t3EnwJKrSEtfyXiMsVaqcQ006MfF4JQQlZGsqJTbAxNQaZRnUq1csPGeiE6dZEwUtqRf5BLo231uXQCBFAfYhm0yBhWCAM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774088043; c=relaxed/simple; bh=frihfCmQzIanWsGaTNFRfE2QMRNSkUDCsJaH143VVzc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Xa8x7gxL2ZdlR5QO4L61mupUCUSHhjpbtAgK9yCMoixusOHcPf5D576WR/uGVi7LJt0Y45nbYPXw2cwdVRKF/RblIzPsBNXW8xj5ysAjYz5ox+6+U61tjSrkJYviNY0e0WpP6dH9IOfgCDB5U62JaP2WtMCLcQ7/s08c25BjNwI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=OmTFv8Va; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OmTFv8Va" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-486507134e4so32496165e9.0 for ; Sat, 21 Mar 2026 03:14:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1774088040; x=1774692840; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=ZyCrfc/ZXBBtX/vytpgp8YE9CQadwN05k6xP+vhF1Ho=; b=OmTFv8Vacd91aiP9aLkE2H7zWi+9qXAYNKaK8G0g/PbPXlsixlITFI5Je3mUMd5MPE Z37qPzByarp5IVh3ZerXA3FY7eIzH8URSKKKJibBNoNk1Bw5kDyeGiwz8xCBE/yVjSEh PNlYFr5iK1vjuIM4KkW6oEQw/IjPZkNG/0Nc+W6/4KhN4Qimb09KQ3s8X9koMyTGUhri GM7xgiQlGuOMf1hoRVXHx1/f7fnp5zmBWwZj3d5fzRbyykW2eSEB1qWR3sGMtmonI0Hf EMSWsvBcro7gblXV0VADq5k0F81/Qhmi6fl6vkTkmW/R22kl5ISS+Q73Fc2KaolHMhXU lH8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774088040; x=1774692840; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-gg:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZyCrfc/ZXBBtX/vytpgp8YE9CQadwN05k6xP+vhF1Ho=; b=hUzYMD03Q/LnYhX6CgcLSGew87GeYf2idk0CqO8oxVzwjseiMXUZ8YR8UXoKnALeSF LJWjClPc8vTtaZgPyWEGiLMD4e21Zo4DexkpybXYIpzr2MEuAKRciyowcSh+0MuBTzE/ ER46IustiNtveTln7uA7Wqapdwk8VxNLW3SISQl9vJTJ8dr7R8xYmVrypOMlBGcNW0Jz xt1/osWviiEPlj59PVbkCU4uSW9Y6PXSgKdG2hA0CPhjVENp+Q4J69Az/GM0ltB8hW7H VAadr2TSVInFesZKdr0PSOMNqGtwmrMRSxiOhKWTp9Y4HrwK95YQ568D1FUgLuKdJWGT CRkA== X-Forwarded-Encrypted: i=1; AJvYcCXRjl9lJnMlK38jjs7gBfNe3lcx6nGMezZDuhJRuSQeJt/FYgzkKJ9lrRV0o81yRp2O7n+rXY8HAtn516g=@vger.kernel.org X-Gm-Message-State: AOJu0YyJWmIsJaw/5j3MCETV0DtYAiLsn6ftCDuBiy3PGx6ZCfXX0jES c5G/UQPm3BoB3rHwOa5bLftEYdtKDl0FONTbzDN/42M8ldekYlf2yfCUAnxPEIkNP+c= X-Gm-Gg: ATEYQzzzrax8dvTBdyZoSbiMZotd2sWZTtIztY47MaoNGaJhAVO8BoZQaTI+UADbLqv zaLbCmY2VmMsXibUidRs7B/p1I3aAzmgvqd1FiBbEM0BQSjk83USvId/SQ5TcvmpzF3ZkmwGKh4 Pc0vpApUvehiTqPegmlgZJPQG1S9fbnZ4+2cQehwb6X/NdNtHlEGiqEj5HZnTMnRY/BDV/SHmOE ZK3NRoDXkEPBX89tlNFw0/B/MWye40TyvLI34g1Wb6HrdNowrkacEyLlIn0lQTcEBFbcQIiOHa9 7hgbynRTi3pEb/0Iq25xhSS94cH7dzGs+2a+d8Xki2hC20tRiw8owchFAcpfRfI94q/i77okED1 DSiTetYHfnsUkfD9V8DoswteE8ZwNFQgufsXBXXx3H0/uigUaR6ypMFcz+/RoExlq51ET4V27Z4 zzAnhkq76GBHHVsybKky+zB6Gop4If X-Received: by 2002:a05:600c:1f0e:b0:486:5f71:5829 with SMTP id 5b1f17b1804b1-486fedab740mr84674065e9.5.1774088040301; Sat, 21 Mar 2026 03:14:00 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b6470393fsm14161545f8f.17.2026.03.21.03.13.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Mar 2026 03:13:59 -0700 (PDT) Date: Sat, 21 Mar 2026 13:13:57 +0300 From: Dan Carpenter To: Linus Walleij , AKASHI Takahiro Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dan Carpenter , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , arm-scmi@vger.kernel.org, Vincent Guittot , Khaled Ali Ahmed , Michal Simek Subject: [PATCH v5 6/7] gpio: dt-bindings: Add bindings for pinctrl based generic gpio driver Message-ID: <047c75a48d76a0f11f9fcd156ace3b5fdaab10ed.1774087290.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: AKASHI Takahiro Traditionally, firmware will provide a GPIO interface or a pin control interface. However, the SCMI protocol provides a generic pin control interface and the GPIO support is built on top of that using the normal pin control interfaces. Potentially other firmware will adopt a similar generic approach in the future. Document how to configure the GPIO device. Signed-off-by: AKASHI Takahiro Signed-off-by: Dan Carpenter Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski --- v5: Fix subsystem prefix Re-word the commit message I removed all references to the driver. I also removed the reference to pin muxing because that's described in the pin control spec file. Fix 3 vs 4 typo in the example. v4: Changed additionalProperties: true to false. Add gpio-line-names. Deleted one example. Add r-b tags v3: Forward port and update .../bindings/gpio/pin-control-gpio.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/pin-control-gpio= .yaml diff --git a/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml b= /Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml new file mode 100644 index 000000000000..9d20b5f23cdc --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/pin-control-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin control based generic GPIO controller + +description: + The pin control-based GPIO will facilitate a pin controller's ability + to drive electric lines high/low and other generic properties of a + pin controller to perform general-purpose one-bit binary I/O. + +maintainers: + - Dan Carpenter + +properties: + compatible: + const: scmi-pinctrl-gpio + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-line-names: true + + gpio-ranges: true + + ngpios: true + +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + + required: + - gpio-hog + +required: + - compatible + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - ngpios + +additionalProperties: false + +examples: + - | + gpio { + compatible =3D "scmi-pinctrl-gpio"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <4>; + gpio-line-names =3D "gpio_5_17", "gpio_5_20", "gpio_5_22", "gpio_2= _1"; + gpio-ranges =3D <&scmi_pinctrl 0 30 4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&keys_pins>; + }; --=20 2.51.0