From nobody Sat Apr 18 10:52:11 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29558C43334 for ; Thu, 14 Jul 2022 05:32:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234571AbiGNFc4 (ORCPT ); Thu, 14 Jul 2022 01:32:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234625AbiGNFcv (ORCPT ); Thu, 14 Jul 2022 01:32:51 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BC2C20BEF; Wed, 13 Jul 2022 22:32:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657776771; x=1689312771; h=date:from:to:cc:subject:message-id:mime-version; bh=g3JhouRCSU7SAPZqa1QXPR7km+MMP1OzGRbcWLjGIBc=; b=dm+rkUwdHg6rTyd0I88Bo2IPQD8Cee74n1wssixFf0D2t65ULZHien0j zZFqBgm9P5eYoNhJ2Gl6vk0BZo5VIQ3MLDTCD8hEseXjCOWch8Cw4A4Hv QerlxhbgG9QRcmXZoOJA2uS+9BtWgTGz0DcziJRQKcuC31fJI4dOIoe3d N1ItER9joqNW8lRDKxrMXIiADx4olGj8jcHS1ITP8URs2H4yb1Yo4DvkH ItmApJXhsx5qihu69TRJb/MeRMUE3AaBbKgQbDkDSt1CV+bD2zDBlEpll G/fl/BWIJZ4Ue3nttxdvXNyMIu5bEDIMZ25vSBLlf7KF/wdzB+1TT+Uq+ A==; X-IronPort-AV: E=McAfee;i="6400,9594,10407"; a="265208550" X-IronPort-AV: E=Sophos;i="5.92,269,1650956400"; d="scan'208";a="265208550" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2022 22:32:38 -0700 X-IronPort-AV: E=Sophos;i="5.92,269,1650956400"; d="scan'208";a="653719713" Received: from pfische1-mobl1.amr.corp.intel.com (HELO desk) ([10.251.18.51]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2022 22:32:38 -0700 Date: Wed, 13 Jul 2022 22:32:37 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, Daniel Sneddon , antonio.gomez.iglesias@linux.intel.com, Josh Poimboeuf Subject: [PATCH] x86/bugs: Switch to "auto" when "ibrs" selected on Enhanced IBRS parts Message-ID: <0456b35fb9ef957d9a9138e0913fb1a3fd445dff.1657747493.git.pawan.kumar.gupta@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently spectre_v2=3Dibrs forces write to MSR_IA32_SPEC_CTRL at every entry and exit. On Enhanced IBRS parts setting MSR_IA32_SPEC_CTRL[IBRS] only once at bootup is sufficient. MSR write at every kernel entry/exit incur unnecessary penalty that can be avoided. When Enhanced IBRS feature is present, switch from "ibrs" to "auto" mode so that appropriate mitigation is selected. Fixes: 7c693f54c873 ("x86/speculation: Add spectre_v2=3Dibrs option to supp= ort Kernel IBRS") Cc: stable@vger.kernel.org # 5.10+ Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/bugs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 0dd04713434b..7d7ebfdfbeda 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1303,6 +1303,12 @@ static enum spectre_v2_mitigation_cmd __init spectre= _v2_parse_cmdline(void) return SPECTRE_V2_CMD_AUTO; } =20 + if (cmd =3D=3D SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_IBRS_ENHAN= CED)) { + pr_err("%s selected but CPU supports Enhanced IBRS. Switching to AUTO se= lect\n", + mitigation_options[i].option); + return SPECTRE_V2_CMD_AUTO; + } + spec_v2_print_cond(mitigation_options[i].option, mitigation_options[i].secure); return cmd; base-commit: 72a8e05d4f66b5af7854df4490e3135168694b6b --=20 2.35.3