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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D9.mail.protection.outlook.com (10.167.241.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Tue, 30 Jan 2024 03:19:12 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 29 Jan 2024 21:19:08 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 3/8] tools/power x86_energy_perf_policy: rename get_msr() and put_msr() with intel prefix Date: Tue, 30 Jan 2024 11:18:31 +0800 Message-ID: <03a45b3d1b5969f8c86ac40297be96228cb21392.1706583551.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|BL1PR12MB5109:EE_ X-MS-Office365-Filtering-Correlation-Id: 081564d1-049b-41c0-630d-08dc21423b78 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2024 03:19:12.7977 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 081564d1-049b-41c0-630d-08dc21423b78 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5109 Content-Type: text/plain; charset="utf-8" From: Perry Yuan Rename the get_msr() and put_msr() function with Intel prefix,that will better help to differentiate with other processor msr operation. No functional impact. Signed-off-by: Perry Yuan Suggested-by: Fontenot Nathan --- .../x86_energy_perf_policy.c | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.= c b/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c index da9087873915..3f09c12f24fa 100644 --- a/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c +++ b/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c @@ -679,7 +679,7 @@ void err_on_hypervisor(void) "not supported on this virtual machine"); } =20 -int get_msr(int cpu, int offset, unsigned long long *msr) +int intel_get_msr(int cpu, int offset, unsigned long long *msr) { int retval; char pathname[32]; @@ -697,13 +697,13 @@ int get_msr(int cpu, int offset, unsigned long long *= msr) } =20 if (debug > 1) - fprintf(stderr, "get_msr(cpu%d, 0x%X, 0x%llX)\n", cpu, offset, *msr); + fprintf(stderr, "intel_get_msr(cpu%d, 0x%X, 0x%llX)\n", cpu, offset, *ms= r); =20 close(fd); return 0; } =20 -int put_msr(int cpu, int offset, unsigned long long new_msr) +int intel_put_msr(int cpu, int offset, unsigned long long new_msr) { char pathname[32]; int retval; @@ -721,7 +721,7 @@ int put_msr(int cpu, int offset, unsigned long long new= _msr) close(fd); =20 if (debug > 1) - fprintf(stderr, "put_msr(cpu%d, 0x%X, 0x%llX)\n", cpu, offset, new_msr); + fprintf(stderr, "intel_put_msr(cpu%d, 0x%X, 0x%llX)\n", cpu, offset, new= _msr); =20 return 0; } @@ -829,7 +829,7 @@ void read_hwp_cap(int cpu, struct msr_hwp_cap *cap, uns= igned int msr_offset) int ret; =20 if (genuine_intel) { - get_msr(cpu, msr_offset, &msr); + intel_get_msr(cpu, msr_offset, &msr); cap->highest =3D msr_perf_2_ratio(HWP_HIGHEST_PERF(msr)); cap->guaranteed =3D msr_perf_2_ratio(HWP_GUARANTEED_PERF(msr)); cap->efficient =3D msr_perf_2_ratio(HWP_MOSTEFFICIENT_PERF(msr)); @@ -872,7 +872,7 @@ void read_hwp_request(int cpu, struct msr_hwp_request *= hwp_req, unsigned int msr int ret; =20 if (genuine_intel) { - get_msr(cpu, msr_offset, &msr); + intel_get_msr(cpu, msr_offset, &msr); =20 hwp_req->hwp_min =3D msr_perf_2_ratio((((msr) >> 0) & 0xff)); hwp_req->hwp_max =3D msr_perf_2_ratio((((msr) >> 8) & 0xff)); @@ -909,7 +909,7 @@ void write_hwp_request(int cpu, struct msr_hwp_request = *hwp_req, unsigned int ms msr |=3D HWP_ENERGY_PERF_PREFERENCE(hwp_req->hwp_epp); msr |=3D HWP_ACTIVITY_WINDOW(hwp_req->hwp_window); msr |=3D HWP_PACKAGE_CONTROL(hwp_req->hwp_use_pkg); - put_msr(cpu, msr_offset, msr); + intel_put_msr(cpu, msr_offset, msr); } else if (authentic_amd) { /* AMD EPP need to set desired perf with zero */ hwp_req->hwp_desired =3D 0; @@ -1011,14 +1011,14 @@ int print_pkg_msrs(int pkg) print_hwp_request_pkg(pkg, &req, ""); =20 if (has_hwp_notify) { - get_msr(first_cpu_in_pkg[pkg], MSR_HWP_INTERRUPT, &msr); + intel_get_msr(first_cpu_in_pkg[pkg], MSR_HWP_INTERRUPT, &msr); fprintf(stderr, "pkg%d: MSR_HWP_INTERRUPT: 0x%08llx (Excursion_Min-%sabled, Guaranteed_P= erf_Change-%sabled)\n", pkg, msr, ((msr) & 0x2) ? "EN" : "Dis", ((msr) & 0x1) ? "EN" : "Dis"); } - get_msr(first_cpu_in_pkg[pkg], MSR_HWP_STATUS, &msr); + intel_get_msr(first_cpu_in_pkg[pkg], MSR_HWP_STATUS, &msr); fprintf(stderr, "pkg%d: MSR_HWP_STATUS: 0x%08llx (%sExcursion_Min, %sGuaranteed_Perf_Cha= nge)\n", pkg, msr, @@ -1274,8 +1274,8 @@ int enable_hwp_on_cpu(int cpu) int ret; =20 if (genuine_intel) { - get_msr(cpu, MSR_PM_ENABLE, &msr); - put_msr(cpu, MSR_PM_ENABLE, 1); + intel_get_msr(cpu, MSR_PM_ENABLE, &msr); + intel_put_msr(cpu, MSR_PM_ENABLE, 1); } else if (authentic_amd) { ret =3D amd_get_msr(cpu, MSR_AMD_CPPC_ENABLE, (unsigned long *)(&msr)); if (ret < 0) @@ -1312,14 +1312,14 @@ int update_cpu_msrs(int cpu) if (update_turbo) { int turbo_is_present_and_disabled; =20 - get_msr(cpu, MSR_IA32_MISC_ENABLE, &msr); + intel_get_msr(cpu, MSR_IA32_MISC_ENABLE, &msr); =20 turbo_is_present_and_disabled =3D ((msr & MSR_IA32_MISC_ENABLE_TURBO_DIS= ABLE) !=3D 0); =20 if (turbo_update_value =3D=3D 1) { if (turbo_is_present_and_disabled) { msr &=3D ~MSR_IA32_MISC_ENABLE_TURBO_DISABLE; - put_msr(cpu, MSR_IA32_MISC_ENABLE, msr); + intel_put_msr(cpu, MSR_IA32_MISC_ENABLE, msr); if (verbose) printf("cpu%d: turbo ENABLE\n", cpu); } @@ -1330,7 +1330,7 @@ int update_cpu_msrs(int cpu) * but cpu may be in a different package, so we always write. */ msr |=3D MSR_IA32_MISC_ENABLE_TURBO_DISABLE; - put_msr(cpu, MSR_IA32_MISC_ENABLE, msr); + intel_put_msr(cpu, MSR_IA32_MISC_ENABLE, msr); if (verbose) printf("cpu%d: turbo DISABLE\n", cpu); } @@ -1455,7 +1455,7 @@ void verify_hwp_is_enabled(void) =20 /* MSR_PM_ENABLE[1] =3D=3D 1 if HWP is enabled and MSRs visible */ if (genuine_intel) - get_msr(base_cpu, MSR_PM_ENABLE, &msr); + intel_get_msr(base_cpu, MSR_PM_ENABLE, &msr); else if (authentic_amd) { ret =3D amd_get_msr(base_cpu, MSR_AMD_CPPC_ENABLE, (unsigned long *)(&ms= r)); if (ret < 0) @@ -1561,7 +1561,7 @@ void early_cpuid(void) if (model =3D=3D 0x4F) { unsigned long long msr; =20 - get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); + intel_get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); =20 bdx_highest_ratio =3D msr & 0xFF; } --=20 2.34.1