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Thu, 15 Sep 2022 00:56:14 -0700 From: Nicolin Chen To: , , , , , , CC: , , , , Subject: [PATCH v3 1/6] iommu/msm: Add missing __disable_clocks calls Date: Thu, 15 Sep 2022 00:56:08 -0700 Message-ID: <031c4ec032025a299d72665118d58dd48aa936ac.1663227492.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT062:EE_|SA0PR12MB4527:EE_ X-MS-Office365-Filtering-Correlation-Id: fc126afe-969f-4e97-b831-08da96efc848 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fa00DKS/Oj6/RioFyY8K171XJoFv6l42ykQhyi0Lxu2qmAdWEGgWwALZJM8RYRlRlidSmKqL6GqZKr6+FdrPDTos7SaGCAqTlB0W+/XgT49F3xDXMDBe5omB22dUUJzczVcT9jqIdS9RMPFgd0OeyhcpigizVDO1/gDbjTIB31gUB6KlJEzQ7BfGF51oz4ISxx5fFrZz2Tc50fMPxVkd0EnVa3OS9g27MwRyndlLkf/aEpHbsay+UGephBt4XPhidybuGsc2LHrZvowuP2BvtCFbdheYwPcPhQ84PcmtfNQ/vxfy+BY0OlKAZKb3thOtCTrQyWDwIXJ4YMgE+LwSIPAzo5cQARVsqmtomUNDB/6lQn9tmFUcE/KstEJqscr8qCQ/+cGQIauVnqo1geSWrCfeKYX3Ns72f65dByJiEZ5PKLkxvzlupBH/EM/HHne6ZB9PkZGdhgAFHRPdertAgt/dGCCqCLI2KzsWiUr6253I+mj/sSf3hwUUwFrS1HCUx6FtsdXsmTafucInN9AXBcA0rjBvA0+Y1XJXElSUCFrxe3dotd0fDwpM5uJHTnYgKynIzgkxvBFQR/KgXLDAS3XHnxN46CDZQQdfS9TGC0fi5HhE+5p13qzrdGaAFdSAaRGPh+Gs04RtbAmUBmo4D1RvKEIJH+ooRR04/2bbkEW615ICfOqdek7KMoTUH58j2VfoiC3wjYbFGCpG0YH2sqFiCGPjNGe7ekpRVP6cR0JBi294YRR52WUtO68k0tstSTM4c8+1uGiUh6WLjpvdpw== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199015)(40470700004)(46966006)(36840700001)(6666004)(47076005)(41300700001)(478600001)(2616005)(426003)(186003)(336012)(83380400001)(26005)(7696005)(2906002)(7416002)(40460700003)(70586007)(316002)(70206006)(40480700001)(82310400005)(4326008)(5660300002)(110136005)(54906003)(8936002)(8676002)(86362001)(7636003)(356005)(36860700001)(82740400003)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2022 07:56:22.6499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc126afe-969f-4e97-b831-08da96efc848 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT062.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4527 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The clock is not symmetrically disabled in the error-out routines. Fixes: 109bd48ea2e1 ("iommu/msm: Add DT adaptation") Cc: stable@vger.kernel.org Cc: Sricharan R Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Signed-off-by: Nicolin Chen --- drivers/iommu/msm_iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 6a24aa804ea3..a7d41ba4a47b 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -418,6 +418,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *do= main, struct device *dev) list_for_each_entry(master, &iommu->ctx_list, list) { if (master->num) { dev_err(dev, "domain already attached"); + __disable_clocks(iommu); ret =3D -EEXIST; goto fail; } @@ -425,6 +426,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *do= main, struct device *dev) msm_iommu_alloc_ctx(iommu->context_map, 0, iommu->ncb); if (IS_ERR_VALUE(master->num)) { + __disable_clocks(iommu); ret =3D -ENODEV; goto fail; } --=20 2.17.1