From nobody Mon Sep 15 23:17:49 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04B97C67871 for ; Mon, 9 Jan 2023 19:10:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237555AbjAITJh (ORCPT ); Mon, 9 Jan 2023 14:09:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237618AbjAITJQ (ORCPT ); Mon, 9 Jan 2023 14:09:16 -0500 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87B333B937 for ; Mon, 9 Jan 2023 11:09:15 -0800 (PST) Received: by mail-ed1-x52d.google.com with SMTP id i15so14060709edf.2 for ; Mon, 09 Jan 2023 11:09:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=ZI4QNYHAsoqJCIbKwCF4KbxUOqKXYFqsYQ+1I8J7L9A=; b=KeuCh0wCp6/fkrCV+b7lipshXbHWdWeLJLV+uyA0HVd7egVd5zzRkZ1LUeB7lJnW5b JyktUsLZClLwML0jvBrLvMhX1gdZivmQ7lCz6cZZH19klIyoU9W7qtDivZXa9n47tbpp ALMjq7YQp/pPoE4jrtGIEk+N5UTTdoF/YUnvSJYWC1hlK9IM3wjiaekqU8mqsIuAcezP oXdYDlHShjkWLHwKF8pXchC+8ZDADZct4XAR9na8JLiovrjknRAYkJJ7ZCK2w1qpvJK2 iKZ0SUzhQLT9bccYgK8cl81sAeKbRWP+EzSf4d2Nlydjof3/QNXt3ObZJGmgu6IX8XVg uBQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=ZI4QNYHAsoqJCIbKwCF4KbxUOqKXYFqsYQ+1I8J7L9A=; b=kZBbmaDrtJqdMTJzxjAb2v7q1QSSLiEKv51OuDEqbdu6MEMwYohyNJI8H+NGBFiBQb BiCXT3/p7NhuEHdoi38aGLv+NbYCOBUgbl5ousgwjMtjezUgOkXGEedWg9SnBUvIFonZ TqkXA99BSdJOoQ5vtCSySNY2Z+t1kmQFdmSBC86pzoycl+ZzlFKOZ89TXL/eXTXdMx/x 8sTMvM9reXijMwfTh3Yq1pbdlRZNK3HEgHVAe0HH3EbhJGXwXYxi8tbb2SgL5Dn/9X5V rQODUOCnuSWiZ79bRasOnI4L3t2aTKatR6NDuBkMH0w0EziDUlObsrMHVPJocgfEHaqb XUkA== X-Gm-Message-State: AFqh2kqORtI2vikcTDrWQbPVLSPmC22a4H3mZy9F6NxnaHXRN0AZaNQT oQtmIWZDEOC5N6jePqi5na8= X-Google-Smtp-Source: AMrXdXuD4MlMKwuEwJVAD+D5BX/tAz1GAS6ckQ8kHmmpf93LnSQ8Q2N6IECunQt8abziuA7mJ+Bzlw== X-Received: by 2002:a05:6402:207c:b0:490:ff75:7aa with SMTP id bd28-20020a056402207c00b00490ff7507aamr3522527edb.1.1673291354140; Mon, 09 Jan 2023 11:09:14 -0800 (PST) Received: from matrix-ESPRIMO-P710 (p54a07888.dip0.t-ipconnect.de. [84.160.120.136]) by smtp.gmail.com with ESMTPSA id p9-20020aa7d309000000b0046776f98d0csm4062977edq.79.2023.01.09.11.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 11:09:13 -0800 (PST) Date: Mon, 9 Jan 2023 20:09:11 +0100 From: Philipp Hortmann To: Greg Kroah-Hartman , linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] staging: rtl8192e: Rename SetRFPowerSta.., RfReg0Value and bTXPowerDa.. Message-ID: <01ff54a2c135ba6e3d06255102679d496fd2aef1.1673290428.git.philipp.g.hortmann@gmail.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename variable SetRFPowerStateInProgress to set_rf_pwr_state_in_progress, RfReg0Value to rf_reg_0value and bTXPowerDataReadFromEEPORM to tx_pwr_data_read_from_eeprom to avoid CamelCase which is not accepted by checkpatch. Signed-off-by: Philipp Hortmann --- .../staging/rtl8192e/rtl8192e/r8192E_dev.c | 4 +- .../staging/rtl8192e/rtl8192e/r8192E_phy.c | 40 +++++++++---------- drivers/staging/rtl8192e/rtl8192e/rtl_core.c | 2 +- drivers/staging/rtl8192e/rtl8192e/rtl_core.h | 6 +-- 4 files changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c b/drivers/stagi= ng/rtl8192e/rtl8192e/r8192E_dev.c index 06ab02230125..ebf1fa5ec295 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c @@ -345,9 +345,9 @@ static void _rtl92e_read_eeprom_info(struct net_device = *dev) } =20 if (priv->card_8192_version > VERSION_8190_BD) - priv->bTXPowerDataReadFromEEPORM =3D true; + priv->tx_pwr_data_read_from_eeprom =3D true; else - priv->bTXPowerDataReadFromEEPORM =3D false; + priv->tx_pwr_data_read_from_eeprom =3D false; =20 priv->rf_type =3D RTL819X_DEFAULT_RF_TYPE; =20 diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c b/drivers/stagi= ng/rtl8192e/rtl8192e/r8192E_phy.c index cc7e72f2a52c..2e9932a26382 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c @@ -101,17 +101,17 @@ static u32 _rtl92e_phy_rf_read(struct net_device *dev, if (priv->rf_chip =3D=3D RF_8256) { rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); if (Offset >=3D 31) { - priv->RfReg0Value[eRFPath] |=3D 0x140; + priv->rf_reg_0value[eRFPath] |=3D 0x140; rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath]<<16)); + (priv->rf_reg_0value[eRFPath] << 16)); NewOffset =3D Offset - 30; } else if (Offset >=3D 16) { - priv->RfReg0Value[eRFPath] |=3D 0x100; - priv->RfReg0Value[eRFPath] &=3D (~0x40); + priv->rf_reg_0value[eRFPath] |=3D 0x100; + priv->rf_reg_0value[eRFPath] &=3D (~0x40); rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath]<<16)); + (priv->rf_reg_0value[eRFPath] << 16)); =20 NewOffset =3D Offset - 15; } else @@ -130,10 +130,10 @@ static u32 _rtl92e_phy_rf_read(struct net_device *dev, bLSSIReadBackData); =20 if (priv->rf_chip =3D=3D RF_8256) { - priv->RfReg0Value[eRFPath] &=3D 0xebf; + priv->rf_reg_0value[eRFPath] &=3D 0xebf; =20 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + (priv->rf_reg_0value[eRFPath] << 16)); =20 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); } @@ -156,17 +156,17 @@ static void _rtl92e_phy_rf_write(struct net_device *d= ev, rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); =20 if (Offset >=3D 31) { - priv->RfReg0Value[eRFPath] |=3D 0x140; + priv->rf_reg_0value[eRFPath] |=3D 0x140; rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + (priv->rf_reg_0value[eRFPath] << 16)); NewOffset =3D Offset - 30; } else if (Offset >=3D 16) { - priv->RfReg0Value[eRFPath] |=3D 0x100; - priv->RfReg0Value[eRFPath] &=3D (~0x40); + priv->rf_reg_0value[eRFPath] |=3D 0x100; + priv->rf_reg_0value[eRFPath] &=3D (~0x40); rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + (priv->rf_reg_0value[eRFPath] << 16)); NewOffset =3D Offset - 15; } else NewOffset =3D Offset; @@ -179,14 +179,14 @@ static void _rtl92e_phy_rf_write(struct net_device *d= ev, rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); =20 if (Offset =3D=3D 0x0) - priv->RfReg0Value[eRFPath] =3D Data; + priv->rf_reg_0value[eRFPath] =3D Data; =20 if (priv->rf_chip =3D=3D RF_8256) { if (Offset !=3D 0) { - priv->RfReg0Value[eRFPath] &=3D 0xebf; + priv->rf_reg_0value[eRFPath] &=3D 0xebf; rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + (priv->rf_reg_0value[eRFPath] << 16)); } rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); } @@ -306,7 +306,7 @@ void rtl92e_config_mac(struct net_device *dev) u32 *pdwArray =3D NULL; struct r8192_priv *priv =3D rtllib_priv(dev); =20 - if (priv->bTXPowerDataReadFromEEPORM) { + if (priv->tx_pwr_data_read_from_eeprom) { dwArrayLen =3D MACPHY_Array_PGLength; pdwArray =3D Rtl819XMACPHY_Array_PG; =20 @@ -1309,9 +1309,9 @@ static bool _rtl92e_set_rf_power_state(struct net_dev= ice *dev, u8 i =3D 0, QueueID =3D 0; struct rtl8192_tx_ring *ring =3D NULL; =20 - if (priv->SetRFPowerStateInProgress) + if (priv->set_rf_pwr_state_in_progress) return false; - priv->SetRFPowerStateInProgress =3D true; + priv->set_rf_pwr_state_in_progress =3D true; =20 switch (priv->rf_chip) { case RF_8256: @@ -1331,7 +1331,7 @@ static bool _rtl92e_set_rf_power_state(struct net_dev= ice *dev, netdev_err(dev, "%s(): Failed to initialize Adapter.\n", __func__); - priv->SetRFPowerStateInProgress =3D false; + priv->set_rf_pwr_state_in_progress =3D false; return false; } =20 @@ -1438,7 +1438,7 @@ static bool _rtl92e_set_rf_power_state(struct net_dev= ice *dev, } } =20 - priv->SetRFPowerStateInProgress =3D false; + priv->set_rf_pwr_state_in_progress =3D false; return bResult; } =20 diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging= /rtl8192e/rtl8192e/rtl_core.c index 92260d098eaa..050f0435ab6d 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -872,7 +872,7 @@ static void _rtl92e_init_priv_variable(struct net_devic= e *dev) priv->rtllib->rf_off_reason =3D 0; priv->rf_change_in_progress =3D false; priv->hw_rf_off_action =3D 0; - priv->SetRFPowerStateInProgress =3D false; + priv->set_rf_pwr_state_in_progress =3D false; priv->rtllib->pwr_save_ctrl.bLeisurePs =3D true; priv->rtllib->LPSDelayCnt =3D 0; priv->rtllib->sta_sleep =3D LPS_IS_WAKE; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h b/drivers/staging= /rtl8192e/rtl8192e/rtl_core.h index cc3e2816e657..ad34bef5660c 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h @@ -444,18 +444,18 @@ struct r8192_priv { =20 u8 nCur40MhzPrimeSC; =20 - u32 RfReg0Value[4]; + u32 rf_reg_0value[4]; u8 num_total_rf_path; bool brfpath_rxenable[4]; =20 - bool bTXPowerDataReadFromEEPORM; + bool tx_pwr_data_read_from_eeprom; =20 u16 reg_chnl_plan; u16 chnl_plan; u8 hw_rf_off_action; =20 bool rf_change_in_progress; - bool SetRFPowerStateInProgress; + bool set_rf_pwr_state_in_progress; bool bdisable_nic; =20 u8 DM_Type; --=20 2.39.0