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[218.215.224.126]) by smtp.gmail.com with ESMTPSA id ij11-20020a170902ab4b00b001853e6d6179sm2254819plb.162.2022.11.05.18.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Nov 2022 18:11:53 -0700 (PDT) From: Jacob Bai To: gregkh@linuxfoundation.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Jacob Bai Subject: [PATCH v2 1/3] staging: rtl8192e: rename tables in r8192e_hwimg.c Date: Sun, 6 Nov 2022 12:11:43 +1100 Message-Id: <01eb4d9cb22be5f76aa39eedd406577cdfd9f486.1667694826.git.jacob.bai.au@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" fix camel case issue. Signed-off-by: Jacob Bai --- .../staging/rtl8192e/rtl8192e/r8192E_hwimg.c | 18 +++++----- .../staging/rtl8192e/rtl8192e/r8192E_hwimg.h | 36 +++++++++---------- .../staging/rtl8192e/rtl8192e/r8192E_phy.h | 36 +++++++++---------- 3 files changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.c b/drivers/sta= ging/rtl8192e/rtl8192e/r8192E_hwimg.c index e6fce749e65b..8920283f340e 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.c @@ -6,9 +6,9 @@ */ #include "r8192E_hwimg.h" =20 -u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE] =3D {0x0,}; +u32 RTL8192E_PHY_REG_ARRAY[RTL8192E_PHY_REG_ARRAY_LEN] =3D {0x0,}; =20 -u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE] =3D { +u32 RTL8192E_PHY_REG_1T2R_ARRAY[RTL8192E_PHY_REG_1T2R_ARRAY_LEN] =3D { 0x800, 0x00000000, 0x804, 0x00000001, 0x808, 0x0000fc00, @@ -159,7 +159,7 @@ u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengt= hPciE] =3D { 0xe1c, 0x12121416, }; =20 -u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] =3D { +u32 RTL8192E_RADIOA_ARRAY[RTL8192E_RADIOA_ARRAY_LEN] =3D { 0x019, 0x00000003, 0x000, 0x000000bf, 0x001, 0x00000ee0, @@ -285,7 +285,7 @@ u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] =3D= { 0x007, 0x00000700, }; =20 -u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] =3D { +u32 RTL8192E_RADIOB_ARRAY[RTL8192E_RADIOB_ARRAY_LEN] =3D { 0x019, 0x00000003, 0x000, 0x000000bf, 0x001, 0x000006e0, @@ -327,13 +327,13 @@ u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] = =3D { 0x007, 0x00000700, }; =20 -u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE] =3D { +u32 RTL8192E_RADIOC_ARRAY[RTL8192E_RADIOC_ARRAY_LEN] =3D { 0x0, }; =20 -u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE] =3D { +u32 RTL8192E_RADIOD_ARRAY[RTL8192E_RADIOD_ARRAY_LEN] =3D { 0x0, }; =20 -u32 Rtl8192PciEMACPHY_Array[] =3D { +u32 RTL8192E_MAC_ARRAY[RTL8192E_MAC_ARRAY_LEN] =3D { 0x03c, 0xffff0000, 0x00000f0f, 0x340, 0xffffffff, 0x161a1a1a, 0x344, 0xffffffff, 0x12121416, @@ -342,7 +342,7 @@ u32 Rtl8192PciEMACPHY_Array[] =3D { 0x318, 0x00000fff, 0x00000100, }; =20 -u32 Rtl8192PciEMACPHY_Array_PG[] =3D { +u32 RTL8192E_MAC_ARRAY_PG[RTL8192E_MAC_ARRAY_PG_LEN] =3D { 0x03c, 0xffff0000, 0x00000f0f, 0xe00, 0xffffffff, 0x06090909, 0xe04, 0xffffffff, 0x00030306, @@ -355,7 +355,7 @@ u32 Rtl8192PciEMACPHY_Array_PG[] =3D { 0x318, 0x00000fff, 0x00000800, }; =20 -u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE] =3D { +u32 RTL8192E_AGC_TAB_ARRAY[RTL8192E_AGC_TAB_ARRAY_LEN] =3D { 0xc78, 0x7d000001, 0xc78, 0x7d010001, 0xc78, 0x7d020001, diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.h b/drivers/sta= ging/rtl8192e/rtl8192e/r8192E_hwimg.h index 7d63f5a5c1b7..a436c089a779 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.h +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.h @@ -11,23 +11,23 @@ =20 #include =20 -#define PHY_REGArrayLengthPciE 1 -extern u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE]; -#define PHY_REG_1T2RArrayLengthPciE 296 -extern u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE]; -#define RadioA_ArrayLengthPciE 246 -extern u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE]; -#define RadioB_ArrayLengthPciE 78 -extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE]; -#define RadioC_ArrayLengthPciE 2 -extern u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE]; -#define RadioD_ArrayLengthPciE 2 -extern u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE]; -#define MACPHY_ArrayLengthPciE 18 -extern u32 Rtl8192PciEMACPHY_Array[MACPHY_ArrayLengthPciE]; -#define MACPHY_Array_PGLengthPciE 30 -extern u32 Rtl8192PciEMACPHY_Array_PG[MACPHY_Array_PGLengthPciE]; -#define AGCTAB_ArrayLengthPciE 384 -extern u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE]; +#define RTL8192E_PHY_REG_ARRAY_LEN 1 +extern u32 RTL8192E_PHY_REG_ARRAY[RTL8192E_PHY_REG_ARRAY_LEN]; +#define RTL8192E_PHY_REG_1T2R_ARRAY_LEN 296 +extern u32 RTL8192E_PHY_REG_1T2R_ARRAY[RTL8192E_PHY_REG_1T2R_ARRAY_LEN]; +#define RTL8192E_RADIOA_ARRAY_LEN 246 +extern u32 RTL8192E_RADIOA_ARRAY[RTL8192E_RADIOA_ARRAY_LEN]; +#define RTL8192E_RADIOB_ARRAY_LEN 78 +extern u32 RTL8192E_RADIOB_ARRAY[RTL8192E_RADIOB_ARRAY_LEN]; +#define RTL8192E_RADIOC_ARRAY_LEN 2 +extern u32 RTL8192E_RADIOC_ARRAY[RTL8192E_RADIOC_ARRAY_LEN]; +#define RTL8192E_RADIOD_ARRAY_LEN 2 +extern u32 RTL8192E_RADIOD_ARRAY[RTL8192E_RADIOD_ARRAY_LEN]; +#define RTL8192E_MAC_ARRAY_LEN 18 +extern u32 RTL8192E_MAC_ARRAY[RTL8192E_MAC_ARRAY_LEN]; +#define RTL8192E_MAC_ARRAY_PG_LEN 30 +extern u32 RTL8192E_MAC_ARRAY_PG[RTL8192E_MAC_ARRAY_PG_LEN]; +#define RTL8192E_AGC_TAB_ARRAY_LEN 384 +extern u32 RTL8192E_AGC_TAB_ARRAY[RTL8192E_AGC_TAB_ARRAY_LEN]; =20 #endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h b/drivers/stagi= ng/rtl8192e/rtl8192e/r8192E_phy.h index 75629f5df954..e1c1f19b71a3 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.h @@ -9,25 +9,25 @@ =20 #define MAX_DOZE_WAITING_TIMES_9x 64 =20 -#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE -#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE -#define RadioA_ArrayLength RadioA_ArrayLengthPciE -#define RadioB_ArrayLength RadioB_ArrayLengthPciE -#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE -#define RadioC_ArrayLength RadioC_ArrayLengthPciE -#define RadioD_ArrayLength RadioD_ArrayLengthPciE -#define PHY_REGArrayLength PHY_REGArrayLengthPciE -#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE +#define AGCTAB_ArrayLength RTL8192E_AGC_TAB_ARRAY_LEN +#define MACPHY_ArrayLength RTL8192E_MAC_ARRAY_LEN +#define RadioA_ArrayLength RTL8192E_RADIOA_ARRAY_LEN +#define RadioB_ArrayLength RTL8192E_RADIOB_ARRAY_LEN +#define MACPHY_Array_PGLength RTL8192E_MAC_ARRAY_PG_LEN +#define RadioC_ArrayLength RTL8192E_RADIOC_ARRAY_LEN +#define RadioD_ArrayLength RTL8192E_RADIOD_ARRAY_LEN +#define PHY_REGArrayLength RTL8192E_PHY_REG_ARRAY_LEN +#define PHY_REG_1T2RArrayLength RTL8192E_PHY_REG_1T2R_ARRAY_LEN =20 -#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG -#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array -#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array -#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array -#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array -#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array -#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array -#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray -#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray +#define Rtl819XMACPHY_Array_PG RTL8192E_MAC_ARRAY_PG +#define Rtl819XMACPHY_Array RTL8192E_MAC_ARRAY +#define Rtl819XRadioA_Array RTL8192E_RADIOA_ARRAY +#define Rtl819XRadioB_Array RTL8192E_RADIOB_ARRAY +#define Rtl819XRadioC_Array RTL8192E_RADIOC_ARRAY +#define Rtl819XRadioD_Array RTL8192E_RADIOD_ARRAY +#define Rtl819XAGCTAB_Array RTL8192E_AGC_TAB_ARRAY +#define Rtl819XPHY_REGArray RTL8192E_PHY_REG_ARRAY +#define Rtl819XPHY_REG_1T2RArray RTL8192E_PHY_REG_1T2R_ARRAY =20 extern u32 rtl819XAGCTAB_Array[]; =20 --=20 2.34.1