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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:54.7140 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba50f75d-921b-4ec6-9f56-08de59550c67 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6618 Content-Type: text/plain; charset="utf-8" Now ASID/VMID are stored in the arm_smmu_master. These are dead code now. Remove all. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 20 +------ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 3 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 58 ------------------- 4 files changed, 1 insertion(+), 88 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 8365660282d5..c7b054eb062a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -784,10 +784,6 @@ static inline bool arm_smmu_ssids_in_use(struct arm_sm= mu_ctx_desc_cfg *cd_table) return cd_table->used_ssids; } =20 -struct arm_smmu_s2_cfg { - u16 vmid; -}; - struct arm_smmu_strtab_cfg { union { struct { @@ -964,10 +960,6 @@ struct arm_smmu_domain { atomic_t nr_ats_masters; =20 enum arm_smmu_domain_stage stage; - union { - struct arm_smmu_ctx_desc cd; - struct arm_smmu_s2_cfg s2_cfg; - }; =20 struct iommu_domain domain; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 461ccf4bdb03..7f7f147327bd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -295,14 +295,6 @@ static void arm_smmu_sva_domain_free(struct iommu_doma= in *domain) */ arm_smmu_domain_inv(smmu_domain); =20 - /* - * Notice that the arm_smmu_mm_arch_invalidate_secondary_tlbs op can - * still be called/running at this point. We allow the ASID to be - * reused, and if there is a race then it just suffers harmless - * unnecessary invalidation. - */ - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); - /* * Actual free is defered to the SRCU callback * arm_smmu_mmu_notifier_free() @@ -321,7 +313,6 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); struct arm_smmu_device *smmu =3D master->smmu; struct arm_smmu_domain *smmu_domain; - u32 asid; int ret; =20 if (!(master->smmu->features & ARM_SMMU_FEAT_SVA)) @@ -340,22 +331,13 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct= device *dev, smmu_domain->domain.pgsize_bitmap =3D PAGE_SIZE; smmu_domain->stage =3D ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu =3D smmu; - - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); - if (ret) - goto err_free; - - smmu_domain->cd.asid =3D asid; smmu_domain->mmu_notifier.ops =3D &arm_smmu_mmu_notifier_ops; ret =3D mmu_notifier_register(&smmu_domain->mmu_notifier, mm); if (ret) - goto err_asid; + goto err_free; =20 return &smmu_domain->domain; =20 -err_asid: - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); err_free: arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d66931b56b46..4ad26046fab6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -461,9 +461,6 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_cd= *cd, unsigned int asid) struct io_pgtable io_pgtable =3D {}; struct arm_smmu_domain smmu_domain =3D { .pgtbl_ops =3D &io_pgtable.ops, - .cd =3D { - .asid =3D asid, - }, }; struct arm_smmu_inv tag =3D { .type =3D INV_TYPE_S1_ASID, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 6d3da3f82ec8..19437ee6f4e1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2784,66 +2784,17 @@ struct arm_smmu_domain *arm_smmu_domain_alloc(void) static void arm_smmu_domain_free_paging(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - struct arm_smmu_device *smmu =3D smmu_domain->smmu; =20 free_io_pgtable_ops(smmu_domain->pgtbl_ops); - - /* Free the ASID or VMID */ - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - /* Prevent SVA from touching the CD while we're freeing it */ - mutex_lock(&arm_smmu_asid_lock); - xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); - mutex_unlock(&arm_smmu_asid_lock); - } else { - struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; - if (cfg->vmid) - ida_free(&smmu->vmid_map, cfg->vmid); - } - arm_smmu_domain_free(smmu_domain); } =20 -static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain) -{ - int ret; - u32 asid =3D 0; - struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; - - /* Prevent SVA from modifying the ASID until it is written to the CD */ - mutex_lock(&arm_smmu_asid_lock); - ret =3D xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); - cd->asid =3D (u16)asid; - mutex_unlock(&arm_smmu_asid_lock); - return ret; -} - -static int arm_smmu_domain_finalise_s2(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain) -{ - int vmid; - struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; - - /* Reserve VMID 0 for stage-2 bypass STEs */ - vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, - GFP_KERNEL); - if (vmid < 0) - return vmid; - - cfg->vmid =3D (u16)vmid; - return 0; -} - static int arm_smmu_domain_finalise(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, u32 flags) { - int ret; enum io_pgtable_fmt fmt; struct io_pgtable_cfg pgtbl_cfg; struct io_pgtable_ops *pgtbl_ops; - int (*finalise_stage_fn)(struct arm_smmu_device *smmu, - struct arm_smmu_domain *smmu_domain); bool enable_dirty =3D flags & IOMMU_HWPT_ALLOC_DIRTY_TRACKING; =20 pgtbl_cfg =3D (struct io_pgtable_cfg) { @@ -2863,7 +2814,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_d= omain *smmu_domain, if (enable_dirty) pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_ARM_HD; fmt =3D ARM_64_LPAE_S1; - finalise_stage_fn =3D arm_smmu_domain_finalise_s1; break; } case ARM_SMMU_DOMAIN_S2: @@ -2872,7 +2822,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_d= omain *smmu_domain, pgtbl_cfg.ias =3D smmu->ias; pgtbl_cfg.oas =3D smmu->oas; fmt =3D ARM_64_LPAE_S2; - finalise_stage_fn =3D arm_smmu_domain_finalise_s2; if ((smmu->features & ARM_SMMU_FEAT_S2FWB) && (flags & IOMMU_HWPT_ALLOC_NEST_PARENT)) pgtbl_cfg.quirks |=3D IO_PGTABLE_QUIRK_ARM_S2FWB; @@ -2890,13 +2839,6 @@ static int arm_smmu_domain_finalise(struct arm_smmu_= domain *smmu_domain, smmu_domain->domain.geometry.force_aperture =3D true; if (enable_dirty && smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) smmu_domain->domain.dirty_ops =3D &arm_smmu_dirty_ops; - - ret =3D finalise_stage_fn(smmu, smmu_domain); - if (ret < 0) { - free_io_pgtable_ops(pgtbl_ops); - return ret; - } - smmu_domain->pgtbl_ops =3D pgtbl_ops; smmu_domain->smmu =3D smmu; return 0; --=20 2.43.0