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Tue, 9 Dec 2025 18:45:50 -0800 From: Nicolin Chen To: , , CC: , , , , , , Subject: [PATCH rc v3 2/4] iommu/arm-smmu-v3: Ignore STE MEV when computing the update sequence Date: Tue, 9 Dec 2025 18:45:17 -0800 Message-ID: <0066c711b12af33b39a078ce0d0367e2b692f590.1765334526.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|BY5PR12MB4210:EE_ X-MS-Office365-Filtering-Correlation-Id: 15a84c2d-0071-482a-d708-08de37963be7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0Wshuuy37xKxVhrHG+vX8psUkMlQt+3DI+nuwEO23xoEPo0wExRV87KgRr1T?= =?us-ascii?Q?sF4zcg8W9PIWkKQJKJFpX2QXbddYJha0X51DHUcpZtrG83/hNLAPNY5IvVmh?= =?us-ascii?Q?p/FMS39gVmgGUT9QiYB2lh4LyNKgHPWPTZj+J+QFDRfmw6HE+iDJZSisvVTa?= =?us-ascii?Q?+Dd/BOUOHo8+YWzX50xUXHWYRsYCwREgNR1/X7wnuW142S10CUkJDYlrjuNB?= =?us-ascii?Q?SttOb+KCa+M2bz+KeZAR3WpYCGZc3XjguffrLdo0SsUre9vnjrrXIPzQ1lFy?= =?us-ascii?Q?RIrAxVkhw1Sv21WzySKfllZQ/hSbh/iagoHGG3QR2BgqArW8z8ek7vyAbRxs?= =?us-ascii?Q?O8604ufn1BoUTklj8LN6112ZvGff02XgtnzmLKcaQ36llrtuW9WJnPVxbQsZ?= =?us-ascii?Q?fQV7tSFG1XPkScPwLw7QhOijWRHFaK8b8b3GF9NQiLYzit+ipq8btIMvzbP6?= =?us-ascii?Q?fxBTup1TAn1SVfQYy7EvWC6C1gjCELqEcAOdInYAOTx75jv63fd3wPVnO/cI?= =?us-ascii?Q?Kt+9vQdy3aDz7kSM1uKn9OfalSAbSemx12AMt3jZUg2dzXEeKGjal9q5w/IK?= =?us-ascii?Q?2xMAWWUjU+irqw52ag34jXvDGC3drRANqHvfaqK/JXjgbpOqkwsSbyNuhDdG?= =?us-ascii?Q?UUdrgV31TkwKtXZsHTiZFhxxUN1l3q1+tMkhGKZczrgu1ic1ZcEViCU3ROMj?= =?us-ascii?Q?epXWaretSOMD/Ok0/h1/9jWVOT7p0Jdmj/DCyBBmHertgHojXTEpgSgL5kLm?= =?us-ascii?Q?QfxD7TG3sptV8TrjVIg8/GwXRf10Kt1fsGwKJxTr7UGNijesHNpJO5dyrKXh?= =?us-ascii?Q?hBbKWTBe6/utEJ79MW8i1XNepFBwj1mylRhgOd3ptud1nTR0pUBeT+T6qMMW?= =?us-ascii?Q?ATVNSa9qTheTWRBdsgeulho4Yzgjp+n4JkxsOKiu+iT+Y+oT6q6csTN3h8IX?= =?us-ascii?Q?MfgherVafP0bK5vQTg3RIvf+gBUsdm7EJysJ+BoiDUuBrzT3truWLQhLD1/I?= =?us-ascii?Q?o2Gxn2gd44FH4XG9u3wvNmL+vDo3Col3hMh7Cg8H0nBrB++xDi4VT5WtBZj7?= =?us-ascii?Q?/n4kcr7UWMKA9TpRMRI2h0xwUrYF8+2jGzvISAp3/KEQZKLVqsucsDNupiDY?= =?us-ascii?Q?rnYUQyI1dOijqWZBuk3CneeZFiWSm78LzJGhtwCr/rASnTq/osxcav1kCaWx?= =?us-ascii?Q?A3hPNWvm6bfbIvvj7F5Hx5lnRoJjxFFXKyTTqZcnu6jZjdCTC+sBuAuWwakh?= =?us-ascii?Q?eHXcYn86LY2SFTj22Nq+daKxt+hhpeLr+3oEb7uSSZyXQsVQNfs0J/OqazuS?= =?us-ascii?Q?WopiD6GdrXbdlg+lDh0eB6VkrbooN8H46RLoE2oOR3rcIMdn8eZ6CFLv6fCw?= =?us-ascii?Q?+Zz6ztF4asNuI0I6HW2XKo4vNrKEoFp4hvibTn7TQpEYkFotTpyaHMFWmWTN?= =?us-ascii?Q?jnGle4mFcJEQ38U//uRyWTQaS4kD135sIzn95oYg+xMIrJyqqXyxoOfoEmSQ?= =?us-ascii?Q?Ig/5R3kqhJ7ed7w1dC0CBvSLU3/OhRgehzUakobE18kPQK+6FNLCQQhW1nlk?= =?us-ascii?Q?4O7n9SZivrGwCTx4D/A=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 02:45:52.1078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15a84c2d-0071-482a-d708-08de37963be7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4210 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Nested CD tables set the MEV bit to try to reduce multi-fault spamming on the hypervisor. Since MEV is in STE word 1 this causes a breaking update sequence that is not required and impacts real workloads. For the purposes of STE updates the value of MEV doesn't matter, if it is set/cleared early or late it just results in a change to the fault reports that must be supported by the kernel anyhow. The spec says: Note: Software must expect, and be able to deal with, coalesced fault records even when MEV =3D=3D 0. So ignore MEV when computing the update sequence to avoid creating a breaking update. Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS = mitigations") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index e22c0890041b..3e161d8298d9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); VISIBLE_IF_KUNIT void arm_smmu_get_ste_ignored(__le64 *ignored_bits) { + /* + * MEV does not meaningfully impact the operation of the HW, it only + * changes how many fault events are generated, thus we can ignore it + * when computing the ordering. The spec notes the device can act like + * MEV=3D1 anyhow: + * + * Note: Software must expect, and be able to deal with, coalesced + * fault records even when MEV =3D=3D 0. + */ + ignored_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_ignored); =20 --=20 2.43.0