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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4887e80a6ebsm66704905e9.6.2026.03.31.12.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 12:04:30 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774983871; x=1775588671; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vDr/6yFSh7ffXnt3TkKTvjWGoxscpXmm0MBYPU21APE=; b=jwglvYkOa8yor6zYJiFKat5QPlNjTC16G8W+EpXhi+HVhRkNtNZlO3+NAk7XrChKTy sCZTw4GdsF1yPLqwrlUpnSBAMhASyHmZM5am0FD/68Jd4QqgUkId01cpMrNEPN2qq9m7 xX/IepbPoUlvK1iDz5xdBy4jO5cXyu51uc/EbX4tthFJwUqWj/1TYnrNiZhLtwTBLv5B yLoodGo7LZguwsR3TDIX+s9zrUewooeYSliUclKprMGxYv0JaQH+n1uWGNp77HITb1Zu u/tEH+f94alscN+Gojs8OqtitXmlL4ITsYzs+MT+9667inbSvtr6xgVMDZXGndrJa+WB o8xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774983871; x=1775588671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=vDr/6yFSh7ffXnt3TkKTvjWGoxscpXmm0MBYPU21APE=; b=fCA2jIIKjA5731ORlS+9JTN4piD4rfxH6awggSvTOG8fAoLtqhLHq1Hryq04qWtZtc waWkWHfeQwRUJjGg6Yjguy+N1Qk7KRI5U1pjVXg177OHhKAa6knWfJcrr9Ognxi3KUnp wQsg2PS5zlO8LfwT7s2wTm5Vwc4EotiLbL6z4jzyiwFKY2yvciVpAv3QcVoZQxCDXUnE A9012H8NTUQeGUtHw1KprorMFxNQfXLGaq2mWWjt0P0ZBhoDAnUuWzsl+is4jW0Q+tMq LKQLUpmZRyfjk1QXeZ2rlM07R1dlyjekPcfNeXNqDXBIlcisqgHSkE2mafkwk097d+36 fYIQ== X-Gm-Message-State: AOJu0YzakHEuLhquetsR2TZjHxOX+B8r/c4gs1yUs04dg/PMOY1mhJg9 pIo4KwsQamk5XGVUNOVxuf3LtAWh5pyvIfLxRe4ViGHZSSapKgJTjWniF6DztQ== X-Gm-Gg: ATEYQzyF78otg2WscSwA0Art8QgTyWuDeU1CakiUVXtSNyd5fmbxkLfP1lTXHIEhYxD NNQZzhwZUXvfD4nVvEnYFv0Oh27hs2szE8CYb956rQ5gUD9rZsySI2le5zF3BjhKNCG4IrSH4vs q0PnsvzvcuH/6Pzdd+MlRMhy8MXY2NiMUzivusDbcgHL5etT494CqjYS6BcVKQOPGxpj4tRulvk eHdr/C4W2pZZ8IPjYGHpRw7bAR42Vl4mov3L4iTv4oTcm6sW/BZQHZqZWOd33Ud0V2Gbpb2pMtH A1BntGjbgc+VhLCFGquKNFJh0VIPDC7c/1mNXvVZmraK4+SVlra3ilg6qXtQnUr8Cutz6nzrEwK SXF5ppcdGKv2UN9wUdd1rt1z6r0uX01FjrJh1ZbIs79CO1uHVME5KRghjVCDhBYs0Gxn/GWmxzD dSmDLgO8ETGyCnbM4BZ8rpm+AyftZ6gYu2fksu3WX2SjP+a6rr65LKGuvcUApWXNWm0A== X-Received: by 2002:a05:600c:c04a:b0:485:fbd2:f72 with SMTP id 5b1f17b1804b1-4888356610dmr7617095e9.1.1774983870625; Tue, 31 Mar 2026 12:04:30 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v2 3/4] xen/riscv: allow Xen to use SSTC while hiding it from guests Date: Tue, 31 Mar 2026 21:04:18 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-42698a/1774983871-9A2B0112-CA7E9819/10/73395122804 X-purgate-type: spam X-purgate-size: 8423 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1774983895753154100 Content-Type: text/plain; charset="utf-8" OpenSBI currently does not advertise the SSTC extension via the device tree. Additionally, SSTC can no longer be reliably disabled by removing the "sstc" string from riscv,isa, as OpenSBI probes support by attempting to access CSR_STIMECMP. Introduce a runtime probe in Xen to determine whether SSTC is available. The probe attempts to read CSR_STIMECMP using csr_read_safe(). If the access succeeds, SSTC is considered available; if a trap occurs, it is treated as unsupported. When SSTC is detected, Xen may use it internally to program timers. However, the extension is not exposed to guests because the required context switch handling for the SSTC CSRs is not yet implemented. To prevent guests from using SSTC, RISCV_ISA_EXT_sstc is cleared from the riscv_isa bitmap and in future patches from riscv_isa DTS property. As a result, the corresponding HENVCFG bit is not set and guests fall back to the SBI timer interface. Timer requests are then handled by Xen via the usual SBI interception path. Introduce set_xen_timer() to abstract how the timer is programmed, either via the SSTC extension or an SBI call. This also reduces the number of if statements in reprogram_timer(). The set_xen_timer function pointer is selected based on csr_read_safe() rather than riscv_isa_extension(). The latter reflects features supported by both Xen and the guest, while SSTC is currently only supported for Xen. Therefore, relying solely on riscv_isa_extension() would not reliably determine whether SSTC can be used. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/cpufeature.c | 33 ++++++++++++++++++++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/riscv_encoding.h | 2 ++ xen/arch/riscv/time.c | 34 ++++++++++++--------- xen/arch/riscv/vtimer.c | 7 ++++- 5 files changed, 62 insertions(+), 15 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 03e27b037be0..823af53ca18e 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -17,6 +17,7 @@ #include =20 #include +#include =20 #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -139,6 +140,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_e= xt[] =3D { RISCV_ISA_EXT_DATA(smaia), RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), + RISCV_ISA_EXT_DATA(sstc), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), }; @@ -483,6 +485,7 @@ void __init riscv_fill_hwcap(void) unsigned int i; const size_t req_extns_amount =3D ARRAY_SIZE(required_extensions); bool all_extns_available =3D true; + unsigned long tmp; =20 riscv_fill_hwcap_from_isa_string(); =20 @@ -495,6 +498,36 @@ void __init riscv_fill_hwcap(void) panic("HW capabilities parsing failed: %s\n", failure_msg); } =20 + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) + { + printk("SSTC is detected but is supported only for Xen usage not f= or " + "a guest\n"); + + /* + * As SSTC for guest isn't supported it is needed temprorary to: + * + * 1. Clear bit RISCV_ISA_EXT_sstc in riscv_isa as theoretuically = it + * could be that OpenSBI (it doesn't pass it now) or whatever r= an + * before Xen will add SSTC to riscv,isa string. This bit clear + * won't allow guest to use SSTC extension as vtimer context + * switch and restore isn't ready for that. + */ + __clear_bit(RISCV_ISA_EXT_sstc, riscv_isa); + + /* + * 2. A VS-timer interrupt becomes pending whenever the value of + * (time + htimedelta) is greater than or equal to vstimecmp CS= R. + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to + * ULONG_MAX. + * + * It should be dropped when SSTC for guests will be supported. + */ + csr_write(CSR_VSTIMECMP, ULONG_MAX); +#ifdef CONFIG_RISCV_32 + csr_write(CSR_VSTIMECMPH, ULONG_MAX); +#endif + } + for ( i =3D 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext =3D required_extensions[i]; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index ef02a3e26d2c..0c48d57a03bb 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -38,6 +38,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_smaia, RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, + RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index dd15731a86fa..d0d60ba15e62 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -396,6 +396,8 @@ #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSTIMECMPH 0x25d =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ #define CSR_HVIEN 0x608 diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 7efa76fdbcb1..42d547a03e0f 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -13,6 +13,18 @@ unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 +static int cf_check sstc_set_xen_timer(uint64_t deadline) +{ + csr_write(CSR_STIMECMP, deadline); +#ifdef CONFIG_RISCV_32 + csr_write(CSR_STIMECMPH, deadline >> 32); +#endif + + return 0; +} + +static int (* __ro_after_init set_xen_timer)(uint64_t deadline); + s_time_t get_s_time(void) { uint64_t ticks =3D get_cycles() - boot_clock_cycles; @@ -61,20 +73,7 @@ int reprogram_timer(s_time_t timeout) if ( deadline <=3D now ) return 0; =20 - /* - * TODO: When the SSTC extension is supported, it would be preferable = to - * use the supervisor timer registers directly here for better - * performance, since an SBI call and mode switch would no longer - * be required. - * - * This would also reduce reliance on a specific SBI implementat= ion. - * For example, it is not ideal to panic() if sbi_set_timer() re= turns - * a non-zero value. Currently it can return 0 or -ENOSUPP, and - * without SSTC we still need an implementation because only the - * M-mode timer is available, and it can only be programmed in - * M-mode. - */ - if ( (rc =3D sbi_set_timer(deadline)) ) + if ( (rc =3D set_xen_timer(deadline)) ) panic("%s: timer wasn't set because: %d\n", __func__, rc); =20 /* Enable timer interrupt */ @@ -85,10 +84,17 @@ int reprogram_timer(s_time_t timeout) =20 void __init preinit_xen_time(void) { + unsigned long tmp; + if ( acpi_disabled ) preinit_dt_xen_time(); else panic("%s: ACPI isn't supported\n", __func__); =20 boot_clock_cycles =3D get_cycles(); + + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) + set_xen_timer =3D sstc_set_xen_timer; + else + set_xen_timer =3D sbi_set_timer; } diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index afd8a53a7387..c065052afeb7 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -4,6 +4,7 @@ #include #include =20 +#include #include =20 static void vtimer_expired(void *data) @@ -75,12 +76,16 @@ void vtimer_ctxt_switch_from(struct vcpu *p) { ASSERT(!is_idle_vcpu(p)); =20 - /* Nothing to do at the moment as SSTC isn't supported now. */ + BUG_ON(riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc)); + + /* Nothing to do at the moment as SSTC for guests isn't supported now = */ } =20 void vtimer_ctxt_switch_to(struct vcpu *n) { ASSERT(!is_idle_vcpu(n)); =20 + BUG_ON(riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc)); + migrate_timer(&n->arch.vtimer.timer, n->processor); } --=20 2.53.0