From nobody Sun Feb 8 21:48:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1669910740993331.2766006662456; Thu, 1 Dec 2022 08:05:40 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.450918.708440 (Exim 4.92) (envelope-from ) id 1p0m3R-0001Um-CJ; Thu, 01 Dec 2022 16:04:53 +0000 Received: by outflank-mailman (output) from mailman id 450918.708440; Thu, 01 Dec 2022 16:04:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p0m3R-0001Uf-9D; Thu, 01 Dec 2022 16:04:53 +0000 Received: by outflank-mailman (input) for mailman id 450918; Thu, 01 Dec 2022 16:04:52 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p0m3Q-0001UO-2L for xen-devel@lists.xenproject.org; Thu, 01 Dec 2022 16:04:52 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id e29d28b4-7191-11ed-91b6-6bf2151ebd3b; Thu, 01 Dec 2022 17:04:50 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AFF53ED1; Thu, 1 Dec 2022 08:04:56 -0800 (PST) Received: from e109506.cambridge.arm.com (e109506.cambridge.arm.com [10.1.199.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4D6D43F67D; Thu, 1 Dec 2022 08:04:49 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e29d28b4-7191-11ed-91b6-6bf2151ebd3b From: Rahul Singh To: xen-devel@lists.xenproject.org Cc: Bertrand Marquis , Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [RFC PATCH 02/21] xen/arm: smmuv3: Add support for stage-1 and nested stage translation Date: Thu, 1 Dec 2022 16:02:26 +0000 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1669910744626100001 Content-Type: text/plain; charset="utf-8" Xen SMMUv3 driver only supports stage-2 translation. Add support for Stage-1 translation that is required to support nested stage translation. In true nested mode, both s1_cfg and s2_cfg will coexist. Let's remove the union. When nested stage translation is setup, both s1_cfg and s2_cfg are valid. We introduce a new smmu_domain abort field that will be set upon guest stage-1 configuration passing. If no guest stage-1 config has been attached, it is ignored when writing the STE. arm_smmu_write_strtab_ent() is modified to write both stage fields in the STE and deal with the abort field. Signed-off-by: Rahul Singh --- xen/drivers/passthrough/arm/smmu-v3.c | 94 +++++++++++++++++++++++---- xen/drivers/passthrough/arm/smmu-v3.h | 9 +++ 2 files changed, 92 insertions(+), 11 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index cbef3f8b36..866fe8de4d 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -686,8 +686,10 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_= master *master, u32 sid, * 3. Update Config, sync */ u64 val =3D le64_to_cpu(dst[0]); - bool ste_live =3D false; + bool s1_live =3D false, s2_live =3D false, ste_live =3D false; + bool abort, translate =3D false; struct arm_smmu_device *smmu =3D NULL; + struct arm_smmu_s1_cfg *s1_cfg =3D NULL; struct arm_smmu_s2_cfg *s2_cfg =3D NULL; struct arm_smmu_domain *smmu_domain =3D NULL; struct arm_smmu_cmdq_ent prefetch_cmd =3D { @@ -702,30 +704,54 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, smmu =3D master->smmu; } =20 - if (smmu_domain) - s2_cfg =3D &smmu_domain->s2_cfg; + if (smmu_domain) { + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_NESTED: + s1_cfg =3D &smmu_domain->s1_cfg; + fallthrough; + case ARM_SMMU_DOMAIN_S2: + s2_cfg =3D &smmu_domain->s2_cfg; + break; + default: + break; + } + translate =3D !!s1_cfg || !!s2_cfg; + } =20 if (val & STRTAB_STE_0_V) { switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { case STRTAB_STE_0_CFG_BYPASS: break; + case STRTAB_STE_0_CFG_S1_TRANS: + s1_live =3D true; + break; case STRTAB_STE_0_CFG_S2_TRANS: - ste_live =3D true; + s2_live =3D true; + break; + case STRTAB_STE_0_CFG_NESTED: + s1_live =3D true; + s2_live =3D true; break; case STRTAB_STE_0_CFG_ABORT: - BUG_ON(!disable_bypass); break; default: BUG(); /* STE corruption */ } } =20 + ste_live =3D s1_live || s2_live; + /* Nuke the existing STE_0 value, as we're going to rewrite it */ val =3D STRTAB_STE_0_V; =20 /* Bypass/fault */ - if (!smmu_domain || !(s2_cfg)) { - if (!smmu_domain && disable_bypass) + if (!smmu_domain) + abort =3D disable_bypass; + else + abort =3D smmu_domain->abort; + + if (abort || !translate) { + if (abort) val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -743,8 +769,39 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_= master *master, u32 sid, return; } =20 + if (ste_live) { + /* First invalidate the live STE */ + dst[0] =3D cpu_to_le64(STRTAB_STE_0_CFG_ABORT); + arm_smmu_sync_ste_for_sid(smmu, sid); + } + + if (s1_cfg) { + BUG_ON(s1_live); + dst[1] =3D cpu_to_le64( + FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | + FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1)); + + if (smmu->features & ARM_SMMU_FEAT_STALLS && + !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) + dst[1] |=3D cpu_to_le64(STRTAB_STE_1_S1STALLD); + + val |=3D (s1_cfg->s1ctxptr & STRTAB_STE_0_S1CTXPTR_MASK) | + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | + FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | + FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); + } + if (s2_cfg) { - BUG_ON(ste_live); + u64 vttbr =3D s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK; + + if (s2_live) { + u64 s2ttb =3D le64_to_cpu(dst[3]) & STRTAB_STE_3_S2TTB_MASK; + BUG_ON(s2ttb !=3D vttbr); + } + dst[2] =3D cpu_to_le64( FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | @@ -754,9 +811,12 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_= master *master, u32 sid, STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2R); =20 - dst[3] =3D cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); + dst[3] =3D cpu_to_le64(vttbr); =20 val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); + } else { + dst[2] =3D 0; + dst[3] =3D 0; } =20 if (master->ats_enabled) @@ -1259,6 +1319,15 @@ static int arm_smmu_domain_finalise(struct iommu_dom= ain *domain, { int ret; struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_NESTED && + (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) || + !(smmu->features & ARM_SMMU_FEAT_TRANS_S2))) { + dev_info(smmu_domain->smmu->dev, + "does not implement two stages\n"); + return -EINVAL; + } =20 /* Restrict the stage to what we can actually support */ smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2; @@ -2307,11 +2376,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu= _device *smmu) smmu->features |=3D ARM_SMMU_FEAT_STALLS; } =20 + if (reg & IDR0_S1P) + smmu->features |=3D ARM_SMMU_FEAT_TRANS_S1; + if (reg & IDR0_S2P) smmu->features |=3D ARM_SMMU_FEAT_TRANS_S2; =20 - if (!(reg & IDR0_S2P)) { - dev_err(smmu->dev, "no stage-2 translation support!\n"); + if (!(reg & (IDR0_S1P | IDR0_S2P))) { + dev_err(smmu->dev, "no translation support!\n"); return -ENXIO; } =20 diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug= h/arm/smmu-v3.h index b3bc7d64c7..e270fe05e0 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -197,6 +197,7 @@ #define STRTAB_STE_0_CFG_BYPASS 4 #define STRTAB_STE_0_CFG_S1_TRANS 5 #define STRTAB_STE_0_CFG_S2_TRANS 6 +#define STRTAB_STE_0_CFG_NESTED 7 =20 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) #define STRTAB_STE_0_S1FMT_LINEAR 0 @@ -547,6 +548,12 @@ struct arm_smmu_strtab_l1_desc { dma_addr_t l2ptr_dma; }; =20 +struct arm_smmu_s1_cfg { + u64 s1ctxptr; + u8 s1fmt; + u8 s1cdmax; +}; + struct arm_smmu_s2_cfg { u16 vmid; u64 vttbr; @@ -667,7 +674,9 @@ struct arm_smmu_domain { atomic_t nr_ats_masters; =20 enum arm_smmu_domain_stage stage; + struct arm_smmu_s1_cfg s1_cfg; struct arm_smmu_s2_cfg s2_cfg; + bool abort; =20 /* Xen domain associated with this SMMU domain */ struct domain *d; --=20 2.25.1