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Thu, 09 Apr 2026 08:06:11 -0700 (PDT) Message-ID: Date: Thu, 9 Apr 2026 17:06:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 08/16] x86/CPUID: enable AVX10.2 sub-leaf From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1775747172-1294941E-AC730DAA/0/0 X-purgate-type: clean X-purgate-size: 5324 X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1775747192762154100 Content-Type: text/plain; charset="utf-8" The logic is modeled as closely as possible after that of leaf 7 sub-leaf handling. Signed-off-by: Jan Beulich --- While the "AVX10" infix is necessary everywhere, the "avx10" prefix on the bitfield name is redundant with the containing structure's field name (see "x86emul: support AVX10.2 media insns" for how this looks like in actual use). Do we want to special-case this in gen-cpuid.py? --- v4: New. --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -343,6 +343,7 @@ int libxl_cpuid_parse_config(libxl_cpuid MSR_ENTRY(0x10a, CPUID_REG_EAX), MSR_ENTRY(0x10a, CPUID_REG_EDX), CPUID_ENTRY(0x80000021, NA, CPUID_REG_ECX), + CPUID_ENTRY(0x00000024, 1, CPUID_REG_ECX), #undef MSR_ENTRY #undef CPUID_ENTRY }; --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -38,6 +38,7 @@ static const struct { { "MSR_ARCH_CAPS.lo", "m10Al" }, { "MSR_ARCH_CAPS.hi", "m10Ah" }, { "CPUID 0x80000021.ecx", "e21c" }, + { "CPUID 0x00000024:1.ecx", "24c1" }, }; =20 #define COL_ALIGN "24" --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -547,6 +547,17 @@ void identify_cpu(struct cpuinfo_x86 *c) &c->x86_capability[FEATURESET_Da1], &tmp, &tmp, &tmp); =20 + if (cpu_has(c, X86_FEATURE_AVX10) && c->cpuid_level >=3D 0x24) { + uint32_t max_subleaf; + + cpuid_count(0x24, 0, &max_subleaf, &tmp, &tmp, &tmp); + if (max_subleaf >=3D 1) + cpuid_count(0x24, 1, + &tmp, &tmp, + &c->x86_capability[FEATURESET_24c1], + &tmp); + } + if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) { val =3D rdmsr(MSR_ARCH_CAPABILITIES); c->x86_capability[FEATURESET_m10Al] =3D val; --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -277,6 +277,9 @@ static void recalculate_misc(struct cpu_ p->avx10.raw[0].b &=3D 0x000700ff; p->avx10.raw[0].c =3D 0; p->avx10.raw[0].d =3D 0; + p->avx10.raw[1].a =3D 0; + p->avx10.raw[1].b =3D 0; + p->avx10.raw[1].d =3D 0; if ( !p->feat.avx10 || !p->avx10.version || !p->avx10.vsz512 || !p->avx10.vsz256 || !p->avx10.vsz128 ) { --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -409,6 +409,9 @@ XEN_CPUFEATURE(ITS_NO, 16*32 XEN_CPUFEATURE(TSA_SQ_NO, 18*32+ 1) /*A No Store Queue Transitiv= e Scheduler Attacks */ XEN_CPUFEATURE(TSA_L1_NO, 18*32+ 2) /*A No L1D Transitive Schedu= ler Attacks */ =20 +/* Intel-defined CPU features, CPUID level 0x00000024:1.ecx, word 19 */ +XEN_CPUFEATURE(AVX10_V1_AUX, 19*32+ 2) /* AVX10 V1 Auxiliary Instr= uctions */ + #endif /* XEN_CPUFEATURE */ =20 /* Clean up from a default include. Close the enum (for C). */ --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -23,6 +23,7 @@ #define FEATURESET_m10Al 16 /* 0x0000010a.eax */ #define FEATURESET_m10Ah 17 /* 0x0000010a.edx */ #define FEATURESET_e21c 18 /* 0x80000021.ecx */ +#define FEATURESET_24c1 19 /* 0x00000024:1.ecx */ =20 struct cpuid_leaf { @@ -64,7 +65,7 @@ const char *x86_cpuid_vendor_to_str(unsi #define CPUID_GUEST_NR_FEAT (2u + 1) #define CPUID_GUEST_NR_TOPO (1u + 1) #define CPUID_GUEST_NR_XSTATE (62u + 1) -#define CPUID_GUEST_NR_AVX10 (0u + 1) +#define CPUID_GUEST_NR_AVX10 (1u + 1) #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1) #define CPUID_GUEST_NR_EXTD_AMD (0x21u + 1) #define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \ @@ -275,6 +276,14 @@ struct cpu_policy bool vsz128:1, vsz256:1, vsz512:1; uint32_t :13; uint32_t /* c */:32, /* d */:32; + + /* Subleaf 1. */ + uint32_t /* a */:32, /* b */:32; + union { + uint32_t _24c1; + struct { DECL_BITFIELD(24c1); }; + }; + uint32_t /* d */:32; }; } avx10; =20 --- a/xen/arch/x86/lib/cpu-policy/cpuid.c +++ b/xen/arch/x86/lib/cpu-policy/cpuid.c @@ -82,6 +82,7 @@ void x86_cpu_policy_to_featureset( fs[FEATURESET_m10Al] =3D p->arch_caps.lo; fs[FEATURESET_m10Ah] =3D p->arch_caps.hi; fs[FEATURESET_e21c] =3D p->extd.e21c; + fs[FEATURESET_24c1] =3D p->avx10._24c1; } =20 void x86_cpu_featureset_to_policy( @@ -106,6 +107,7 @@ void x86_cpu_featureset_to_policy( p->arch_caps.lo =3D fs[FEATURESET_m10Al]; p->arch_caps.hi =3D fs[FEATURESET_m10Ah]; p->extd.e21c =3D fs[FEATURESET_e21c]; + p->avx10._24c1 =3D fs[FEATURESET_24c1]; } =20 void x86_cpu_policy_recalc_synth(struct cpu_policy *p) --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -310,6 +310,9 @@ def crunch_numbers(state): AVX512BW: [AVX512_VBMI, AVX512_VBMI2, AVX512_BITALG, AVX512_BF16, AVX512_FP16, AVX512_BMM], =20 + # AVX10 discrete features. + AVX10: [AVX10_V1_AUX], + # Extensions with VEX/EVEX encodings keyed to a separate feature # flag are made dependents of their respective legacy feature. PCLMULQDQ: [VPCLMULQDQ],