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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abf1d1a84b7sm267586566b.19.2025.02.28.12.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 12:08:16 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c0006bce-f60f-11ef-9898-31a8f345e629 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740773297; x=1741378097; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I0ad6jhwpwcRJBhT3VG+8OUVGsufT7ZaP0GbwgV+mRc=; b=YtQw6oqb7yZIvfpvBX/EzQtIfXo+w2dKNwXNW0CbOnrtHrr3qiiQAbU55rx5wkdKeY W+T09QGF+JGvoWKlZeAZC4DcWQUegmjO3cWZP41nkN1dzLwYRb21telMH8PIZ74eM3Ga Tl4Qa+TkODx+NuyOyBmBn+nVtV98Bfxihk6qLggMwfiMrtWpBrva2/HOSbLxbFIZMGPv 3phcmfQX5XPB4kz7Aci+9jmov1ynihWPf86j4uwMPwHu0nqtV8MQ4xjfLUlrXYRahmD6 xxjQ1uaN5C0Y2VLV/WgYh4I0vGJP0UXhrrXcDKOYj5J0unvOp1kVjuRETaXIhiBdX6Ab Mn0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740773297; x=1741378097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I0ad6jhwpwcRJBhT3VG+8OUVGsufT7ZaP0GbwgV+mRc=; b=XNWadI/unzg6rv37DosPTJojQOYLN2No7MY384fY8wTY0AhWY+ZbXXHh/8GbQU8iRW TqsXxuBJ4LcENsfmBGJdNcJtMcslqb5uZKSHlkqa10MNmtfWj2s0rAtmjvX3NlMgp/dR KQpaR/t08U+iNV4kwR4uvWYOzt2eVVf9EG1MtkA3TwEc0RcPmXZTyY74bsTIouihgJTR GjHY1M+7WBfU0gpzE46dEiJKH7NpxJCx+6aZZQo8JOKSGAtAAMrtFI2EFZu5XGzqVRBK UGfl5bL3dNXQ2LkB3zF5dCv2XOlEyD1TTd8UqLmpQEyaBQhcDeqj58Kz++UDgb/99xdi 5Lcw== X-Gm-Message-State: AOJu0YyDUvvtiXQ5+2MyyYeOgQ2SzhCbQcUyFNPe3UpFifBarmIRJPfV jSCK/3e+tlR2w8G4Dmdx88MCG7fQBXD5lSkyfLS8RhZDG4PU173Pf657XQ== X-Gm-Gg: ASbGncu8W15xAvEJkkasiT0HBxD3d3pzewJeLaR0Z/vnLSaD0d71of02p3A2ADtfNjY OeJjP34FhCBnweaxOqkFl4qQxBAFMu7ryA96YywfK0IBb+C9f47dB5yzT6ovTHNIaBdxQhfUqeF Qkcn2Z2+AFQbF9owspVaxQD5dMLBP0OSW1j+DSl6Qu5RstQYpnbWdckxNsDgzOGtFjtIHrLProH LePFEjn9BUpsv+5LmeuQrEOUYitibmN4YvqWTjW0Z7FUgCb8xzwlzZ5FnfpZfOyAlzA9v7qlhvL 9oyLgeTRkXKzyJZ4q+bhaXNxEy4= X-Google-Smtp-Source: AGHT+IG8VtXzNLqpAWR0oV+hViXGiXfJTaKvGPZjehMEzBp7Le/PfQKujtcjTv9erG23UKg74tMnfA== X-Received: by 2002:a17:907:988:b0:abe:f613:bd0b with SMTP id a640c23a62f3a-abf261d3bcamr554690966b.32.1740773296903; Fri, 28 Feb 2025 12:08:16 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Andrew Cooper , Alistair Francis , Bob Eshleman , Connor Davis , Oleksii Kurochko , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v8 6/6] RISCV/bitops: Use Zbb to provide arch-optimised bitops Date: Fri, 28 Feb 2025 21:07:44 +0100 Message-ID: X-Mailer: git-send-email 2.48.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1740773352316019000 Content-Type: text/plain; charset="utf-8" From: Andrew Cooper Signed-off-by: Andrew Cooper Signed-off-by: Oleksii Kurochko --- Changes in v8: - New patch. It was taken from https://lore.kernel.org/xen-devel/50cd2332-1= 1b7-4b64-85ea-489c416098f9@citrix.com/T/#t with applying the comments: - Introduce BITS_PER_INT. - s/arch_heightl/arch_hweightl --- xen/arch/riscv/include/asm/bitops.h | 7 +++++++ xen/arch/riscv/include/asm/config.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/a= sm/bitops.h index d22eec1e87..72a4a8c155 100644 --- a/xen/arch/riscv/include/asm/bitops.h +++ b/xen/arch/riscv/include/asm/bitops.h @@ -125,6 +125,13 @@ static inline void clear_bit(int nr, volatile void *p) #undef NOT #undef __AMO =20 +#define arch_ffs(x) ((x) ? 1 + __builtin_ctz(x) : 0) +#define arch_ffsl(x) ((x) ? 1 + __builtin_ctzl(x) : 0) +#define arch_fls(x) ((x) ? BITS_PER_INT - __builtin_clz(x) : 0) +#define arch_flsl(x) ((x) ? BITS_PER_LONG - __builtin_clzl(x) : 0) + +#define arch_hweightl(x) __builtin_popcountl(x) + #endif /* ASM__RISCV__BITOPS_H */ =20 /* diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/a= sm/config.h index 826e5c7172..7141bd9e46 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -119,6 +119,7 @@ #define HYPERVISOR_VIRT_START XEN_VIRT_START =20 #if defined(CONFIG_RISCV_64) +# define INT_BYTEORDER 2 # define LONG_BYTEORDER 3 # define ELFSIZE 64 # define MAX_VIRT_CPUS 128u @@ -126,6 +127,9 @@ # error "Unsupported RISCV variant" #endif =20 +#define BYTES_PER_INT (1 << INT_BYTEORDER) +#define BITS_PER_INT (BYTES_PER_INT << 3) + #define BYTES_PER_LONG (1 << LONG_BYTEORDER) #define BITS_PER_LONG (BYTES_PER_LONG << 3) #define POINTER_ALIGN BYTES_PER_LONG --=20 2.48.1