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charset="utf-8" From: Artem Bityutskiy On Sapphire Rapids Xeon (SPR) the C1 and C1E states are basically mutually exclusive - only one of them can be enabled. By default, 'intel_idle' driver enables C1 and disables C1E. However, some users prefer to use C1E instead = of C1, because it saves more energy. This patch adds a new module parameter ('preferred_cstates') for enabling C= 1E and disabling C1. Here is the idea behind it. 1. This option has effect only for "mutually exclusive" C-states like C1 and C1E on SPR. 2. It does not have any effect on independent C-states, which do not require other C-states to be disabled (most states on most platforms as of today= ). 3. For mutually exclusive C-states, the 'intel_idle' driver always has a reasonable default, such as enabling C1 on SPR by default. On other platforms, the default may be different. 4. Users can override the default using the 'preferred_cstates' parameter. 5. The parameter accepts the preferred C-states bit-mask, similarly to the existing 'states_off' parameter. 6. This parameter is not limited to C1/C1E, and leaves room for supporting other mutually exclusive C-states, if they come in the future. Today 'intel_idle' can only be compiled-in, which means that on SPR, in ord= er to disable C1 and enable C1E, users should boot with the following kernel argument: intel_idle.preferred_cstates=3D4 Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git da= 0e58c038e6 Enable C1E (if requested) not only on the BSP's socket / package. Alter command line option to fit our model, and extend it to also accept string form arguments. Signed-off-by: Jan Beulich --- v2: Also accept string form arguments for command line option. Restore C1E-control related enum from Linux, despite our somewhat different use (and bigger code churn). --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1885,6 +1885,12 @@ paging controls access to usermode addre ### ple_window (Intel) > `=3D ` =20 +### preferred-cstates (x86) +> `=3D ( | List of ( C1 | C1E | C2 | ... )` + +This is a mask of C-states which are to be used preferably. This option is +applicable only on hardware were certain C-states are exclusive of one ano= ther. + ### psr (Intel) > `=3D List of ( cmt: | rmid_max: | cat: | cos_= max: | cdp: )` =20 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -82,10 +82,29 @@ boolean_param("mwait-idle", opt_mwait_id =20 static unsigned int mwait_substates; =20 +/* + * Some platforms come with mutually exclusive C-states, so that if one is + * enabled, the other C-states must not be used. Example: C1 and C1E on + * Sapphire Rapids platform. This parameter allows for selecting the + * preferred C-states among the groups of mutually exclusive C-states - the + * selected C-states will be registered, the other C-states from the mutua= lly + * exclusive group won't be registered. If the platform has no mutually + * exclusive C-states, this parameter has no effect. + */ +static unsigned int __ro_after_init preferred_states_mask; +static char __initdata preferred_states[64]; +string_param("preferred-cstates", preferred_states); + #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF /* Reliable LAPIC Timer States, bit 1 for C1 etc. Default to only C1. */ static unsigned int lapic_timer_reliable_states =3D (1 << 1); =20 +enum c1e_promotion { + C1E_PROMOTION_PRESERVE, + C1E_PROMOTION_ENABLE, + C1E_PROMOTION_DISABLE +}; + struct idle_cpu { const struct cpuidle_state *state_table; =20 @@ -95,7 +114,7 @@ struct idle_cpu { */ unsigned long auto_demotion_disable_flags; bool byt_auto_demotion_disable_flag; - bool disable_promotion_to_c1e; + enum c1e_promotion c1e_promotion; }; =20 static const struct idle_cpu *icpu; @@ -924,6 +943,15 @@ static void cf_check byt_auto_demotion_d wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); } =20 +static void cf_check c1e_promotion_enable(void *dummy) +{ + uint64_t msr_bits; + + rdmsrl(MSR_IA32_POWER_CTL, msr_bits); + msr_bits |=3D 0x2; + wrmsrl(MSR_IA32_POWER_CTL, msr_bits); +} + static void cf_check c1e_promotion_disable(void *dummy) { u64 msr_bits; @@ -936,7 +964,7 @@ static void cf_check c1e_promotion_disab static const struct idle_cpu idle_cpu_nehalem =3D { .state_table =3D nehalem_cstates, .auto_demotion_disable_flags =3D NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_atom =3D { @@ -954,64 +982,64 @@ static const struct idle_cpu idle_cpu_li =20 static const struct idle_cpu idle_cpu_snb =3D { .state_table =3D snb_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_byt =3D { .state_table =3D byt_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, .byt_auto_demotion_disable_flag =3D true, }; =20 static const struct idle_cpu idle_cpu_cht =3D { .state_table =3D cht_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, .byt_auto_demotion_disable_flag =3D true, }; =20 static const struct idle_cpu idle_cpu_ivb =3D { .state_table =3D ivb_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_ivt =3D { .state_table =3D ivt_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_hsw =3D { .state_table =3D hsw_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_bdw =3D { .state_table =3D bdw_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_skl =3D { .state_table =3D skl_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_skx =3D { .state_table =3D skx_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_icx =3D { .state_table =3D icx_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static struct idle_cpu __read_mostly idle_cpu_spr =3D { .state_table =3D spr_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_avn =3D { .state_table =3D avn_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_knl =3D { @@ -1020,17 +1048,17 @@ static const struct idle_cpu idle_cpu_kn =20 static const struct idle_cpu idle_cpu_bxt =3D { .state_table =3D bxt_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_dnv =3D { .state_table =3D dnv_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 static const struct idle_cpu idle_cpu_snr =3D { .state_table =3D snr_cstates, - .disable_promotion_to_c1e =3D true, + .c1e_promotion =3D C1E_PROMOTION_DISABLE, }; =20 #define ICPU(model, cpu) \ @@ -1241,6 +1269,25 @@ static void __init skx_idle_state_table_ } =20 /* + * spr_idle_state_table_update - Adjust Sapphire Rapids idle states table. + */ +static void __init spr_idle_state_table_update(void) +{ + /* Check if user prefers C1E over C1. */ + if (preferred_states_mask & BIT(2, U)) { + if (preferred_states_mask & BIT(1, U)) + /* Both can't be enabled, stick to the defaults. */ + return; + + spr_cstates[0].flags |=3D CPUIDLE_FLAG_DISABLED; + spr_cstates[1].flags &=3D ~CPUIDLE_FLAG_DISABLED; + + /* Request enabling C1E using the "C1E promotion" bit. */ + idle_cpu_spr.c1e_promotion =3D C1E_PROMOTION_ENABLE; + } +} + +/* * mwait_idle_state_table_update() * * Update the default state_table for this CPU-id @@ -1261,6 +1308,9 @@ static void __init mwait_idle_state_tabl case INTEL_FAM6_SKYLAKE_X: skx_idle_state_table_update(); break; + case INTEL_FAM6_SAPPHIRERAPIDS_X: + spr_idle_state_table_update(); + break; } } =20 @@ -1268,6 +1318,7 @@ static int __init mwait_idle_probe(void) { unsigned int eax, ebx, ecx; const struct x86_cpu_id *id =3D x86_match_cpu(intel_idle_ids); + const char *str; =20 if (!id) { pr_debug(PREFIX "does not run on family %d model %d\n", @@ -1309,6 +1360,39 @@ static int __init mwait_idle_probe(void) pr_debug(PREFIX "lapic_timer_reliable_states %#x\n", lapic_timer_reliable_states); =20 + str =3D preferred_states; + if (isdigit(str[0])) + preferred_states_mask =3D simple_strtoul(str, &str, 0); + else if (str[0]) + { + const char *ss; + + do { + const struct cpuidle_state *state =3D icpu->state_table; + unsigned int bit =3D 1; + + ss =3D strchr(str, ','); + if (!ss) + ss =3D strchr(str, '\0'); + + for (; state->name[0]; ++state) { + bit <<=3D 1; + if (!cmdline_strcmp(str, state->name)) { + preferred_states_mask |=3D bit; + break; + } + } + if (!state->name[0]) + break; + + str =3D ss + 1; + } while (*ss); + + str -=3D str =3D=3D ss + 1; + } + if (str[0]) + printk("unrecognized \"preferred-cstates=3D%s\"\n", str); + mwait_idle_state_table_update(); =20 return 0; @@ -1400,8 +1484,18 @@ static int cf_check mwait_idle_cpu_init( if (icpu->byt_auto_demotion_disable_flag) on_selected_cpus(cpumask_of(cpu), byt_auto_demotion_disable, NULL, 1); =20 - if (icpu->disable_promotion_to_c1e) + switch (icpu->c1e_promotion) { + case C1E_PROMOTION_DISABLE: on_selected_cpus(cpumask_of(cpu), c1e_promotion_disable, NULL, 1); + break; + + case C1E_PROMOTION_ENABLE: + on_selected_cpus(cpumask_of(cpu), c1e_promotion_enable, NULL, 1); + break; + + case C1E_PROMOTION_PRESERVE: + break; + } =20 return NOTIFY_DONE; } From nobody Mon Feb 9 12:47:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=fail (BodyHash is different from the expected one); dmarc=pass(p=quarantine dis=none) header.from=suse.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1654165655667698.7646709599719; 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Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: [PATCH v2 2/2] x86/mwait-idle: add core C6 optimization for SPR Content-Language: en-US From: Jan Beulich To: "xen-devel@lists.xenproject.org" CC: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: In-Reply-To: Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AS9P251CA0002.EURP251.PROD.OUTLOOK.COM (2603:10a6:20b:50f::10) To VE1PR04MB6560.eurprd04.prod.outlook.com (2603:10a6:803:122::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: de202ba3-6516-4e0a-3153-08da448272b0 X-MS-TrafficTypeDiagnostic: DB7PR04MB4377:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zflh8+zr6wYbBBtvW7lIgoK3jAayhSLbn1je0cjQToSG1M6+d4HjrgDPlGj/bk4cWsP9p0SEVuA65as9pdM/CjeWikqgVKFd61IWBJmVfuGUaMPS+OZykb6ERj1qIiuctJ1viPn62d6BrzCS9Vmp5F3hZJD8D1XWDqbsbBahrzX3vpOqmTiLWav5oHYqg1BB8mScy1G69AGgUE31VDPwlnmcx1f9ONY+/08tXQ4OrHOwLIaR1MHQM2hU74YLF4mhSTALEjvh+cpPWOBfzDbBhwsN3oFM/eKHsMEapY2XyRV80K2+MuR5aDpkTK23GXbp5R8NthMxQKAhrG3Y75ij52XS58D/OYNlG5N3hPQpIK/gYfNH6W4eIfCtrI8vLgHaSY53Hyp6+I2oO03D+jZzlKG+9GV00JLmHJ9WDLcNuOCp7Om/T6ko8yVQ4YkwzEODesP276QGSzfheYXv4hXy5ZXO+IpjSzeDjYl01QhPEvuTPMwaTPS/KO0xDfkGGcKi4vnXGXhtV00we+D82qdbcw2fdDISWqPpSz4Gi9fYrMskTTSWT5sc2//B0TVlPF5pGCmtUZQVrLVClkKnXXfcc3u4lkKOgahfLBs89CmxpPSipuw8bGh6X5gKzzSwMjyyeUyl2eC0ZkkuVjnv1suNo/5gCJms6MV08opP3DCCNIKyCMN4vdDg3wgLoN9DWqk7DMnWxTy4HcXrDnTpDU8P6TJUu6ghVo7vmBUl+FSCIdJzgMSAoORfckBb6Fp7E9L2 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VE1PR04MB6560.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(366004)(31686004)(8676002)(4326008)(66946007)(8936002)(66556008)(66476007)(31696002)(86362001)(5660300002)(6486002)(83380400001)(2906002)(54906003)(316002)(36756003)(508600001)(38100700002)(2616005)(6506007)(6512007)(26005)(186003)(6916009)(43740500002)(45980500001);DIR:OUT;SFP:1101; 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charset="utf-8" From: Artem Bityutskiy Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky= Lake Xeon: if package C6 is disabled, adjust C6 exit latency and target residenc= y to match core C6 values, instead of using the default package C6 values. Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 3a= 9cf77b60dc Make sure a contradictory "preferred-cstates" wouldn't cause bypassing of the added logic. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- v2: Sync with the Linux side fix to the noticed issue. Re-base over change to earlier patch. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1273,18 +1273,31 @@ static void __init skx_idle_state_table_ */ static void __init spr_idle_state_table_update(void) { - /* Check if user prefers C1E over C1. */ - if (preferred_states_mask & BIT(2, U)) { - if (preferred_states_mask & BIT(1, U)) - /* Both can't be enabled, stick to the defaults. */ - return; + uint64_t msr; =20 + /* Check if user prefers C1E over C1. */ + if (preferred_states_mask & BIT(2, U) && + !(preferred_states_mask & BIT(1, U))) { + /* Disable C1 and enable C1E. */ spr_cstates[0].flags |=3D CPUIDLE_FLAG_DISABLED; spr_cstates[1].flags &=3D ~CPUIDLE_FLAG_DISABLED; =20 /* Request enabling C1E using the "C1E promotion" bit. */ idle_cpu_spr.c1e_promotion =3D C1E_PROMOTION_ENABLE; } + + /* + * By default, the C6 state assumes the worst-case scenario of package + * C6. However, if PC6 is disabled, we update the numbers to match + * core C6. + */ + rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); + + /* Limit value 2 and above allow for PC6. */ + if ((msr & 0x7) < 2) { + spr_cstates[2].exit_latency =3D 190; + spr_cstates[2].target_residency =3D 600; + } } =20 /*