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Mon, 24 Nov 2025 04:29:56 -0800 (PST) Message-ID: Date: Mon, 24 Nov 2025 13:29:58 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 2/4] x86/MCE: restrict allocation of thermal and CMCI vector to BSP From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <5ac2e9b1-81f2-41d9-8f05-d546a49c43a7@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5ac2e9b1-81f2-41d9-8f05-d546a49c43a7@suse.com> Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1763987418925019200 Content-Type: text/plain; charset="utf-8" There's no need to do this for every AP; just do it once when setting up the BSP. Then both vector variables can also validly become ro-after-init. While touching intel_init_thermal(), constify its 1st parameter, which in turn requires touching intel_thermal_supported() as well. Signed-off-by: Jan Beulich --- This contextually (but not functionally) collides with "x86/MCE: adjust S3 resume handling". --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -37,7 +37,7 @@ bool is_mc_panic; DEFINE_PER_CPU_READ_MOSTLY(unsigned int, nr_mce_banks); unsigned int __read_mostly firstbank; unsigned int __read_mostly ppin_msr; -uint8_t __read_mostly cmci_apic_vector; +uint8_t __ro_after_init cmci_apic_vector; bool __read_mostly cmci_support; =20 /* If mce_force_broadcast =3D=3D 1, lmce_support will be disabled forcibly= . */ --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -87,7 +87,7 @@ static void cf_check intel_thermal_inter } =20 /* Thermal monitoring depends on APIC, ACPI and clock modulation */ -static bool intel_thermal_supported(struct cpuinfo_x86 *c) +static bool intel_thermal_supported(const struct cpuinfo_x86 *c) { if ( !cpu_has_apic ) return false; @@ -110,13 +110,13 @@ static void __init mcheck_intel_therm_in } =20 /* P4/Xeon Thermal regulation detect and init */ -static void intel_init_thermal(struct cpuinfo_x86 *c) +static void intel_init_thermal(const struct cpuinfo_x86 *c, bool bsp) { uint64_t msr_content; uint32_t val; int tm2 =3D 0; unsigned int cpu =3D smp_processor_id(); - static uint8_t thermal_apic_vector; + static uint8_t __ro_after_init thermal_apic_vector; =20 if ( !intel_thermal_supported(c) ) return; /* -ENODEV */ @@ -160,7 +160,8 @@ static void intel_init_thermal(struct cp return; /* -EBUSY */ } =20 - alloc_direct_apic_vector(&thermal_apic_vector, intel_thermal_interrupt= ); + if ( bsp ) + alloc_direct_apic_vector(&thermal_apic_vector, intel_thermal_inter= rupt); =20 /* The temperature transition interrupt handler setup */ val =3D thermal_apic_vector; /* our delivery vector */ @@ -667,7 +668,7 @@ static void cf_check cmci_interrupt(void mctelem_dismiss(mctc); } =20 -static void intel_init_cmci(struct cpuinfo_x86 *c) +static void intel_init_cmci(struct cpuinfo_x86 *c, bool bsp) { u32 l, apic; int cpu =3D smp_processor_id(); @@ -687,7 +688,8 @@ static void intel_init_cmci(struct cpuin return; } =20 - alloc_direct_apic_vector(&cmci_apic_vector, cmci_interrupt); + if ( bsp ) + alloc_direct_apic_vector(&cmci_apic_vector, cmci_interrupt); =20 apic =3D cmci_apic_vector; apic |=3D (APIC_DM_FIXED | APIC_LVT_MASKED); @@ -993,9 +995,9 @@ enum mcheck_type intel_mcheck_init(struc =20 intel_init_mce(bsp); =20 - intel_init_cmci(c); + intel_init_cmci(c, bsp); =20 - intel_init_thermal(c); + intel_init_thermal(c, bsp); =20 intel_init_ppin(c);