From nobody Sat May 18 23:55:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1697634924731476.94034131238925; Wed, 18 Oct 2023 06:15:24 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.618560.962341 (Exim 4.92) (envelope-from ) id 1qt6Nx-0006NM-4A; Wed, 18 Oct 2023 13:14:53 +0000 Received: by outflank-mailman (output) from mailman id 618560.962341; Wed, 18 Oct 2023 13:14:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qt6Nx-0006NF-1b; Wed, 18 Oct 2023 13:14:53 +0000 Received: by outflank-mailman (input) for mailman id 618560; Wed, 18 Oct 2023 13:14:51 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qt6Nv-0006N9-BP for xen-devel@lists.xenproject.org; Wed, 18 Oct 2023 13:14:51 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 50c0155c-6db8-11ee-9b0e-b553b5be7939; Wed, 18 Oct 2023 15:14:49 +0200 (CEST) Received: from Dell.bugseng.com (unknown [37.161.127.233]) by support.bugseng.com (Postfix) with ESMTPSA id E96784EE0739; Wed, 18 Oct 2023 15:14:46 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 50c0155c-6db8-11ee-9b0e-b553b5be7939 From: Federico Serafini To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Federico Serafini , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [XEN PATCH v2] arm/gic: add missing parameter names and uniform function declarations Date: Wed, 18 Oct 2023 15:14:39 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1697634925422100001 Content-Type: text/plain; charset="utf-8" Add missing parameter names and remove inconsistencies between GICv3 and GICv2. No functional change. Signed-off-by: Federico Serafini Reviewed-by: Stefano Stabellini --- Changes in v2: - switched parameter names of gicv3_write_lr(). --- xen/arch/arm/gic-v3.c | 22 +++++++++++----------- xen/arch/arm/include/asm/gic.h | 12 ++++++------ 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 95e4f020fe..172ff8c005 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1086,29 +1086,29 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr= _reg) } } =20 -static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) +static void gicv3_write_lr(int lr, const struct gic_lr *lr_reg) { uint64_t lrv =3D 0; const enum gic_version vgic_version =3D current->domain->arch.vgic.ver= sion; =20 =20 - lrv =3D ( ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SH= IFT) | - ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHI= FT) ); + lrv =3D ( ((u64)(lr_reg->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUA= L_SHIFT) | + ((u64)(lr_reg->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY= _SHIFT) ); =20 - if ( lr->active ) + if ( lr_reg->active ) lrv |=3D ICH_LR_STATE_ACTIVE; =20 - if ( lr->pending ) + if ( lr_reg->pending ) lrv |=3D ICH_LR_STATE_PENDING; =20 - if ( lr->hw_status ) + if ( lr_reg->hw_status ) { lrv |=3D ICH_LR_HW; - lrv |=3D (uint64_t)lr->hw.pirq << ICH_LR_PHYSICAL_SHIFT; + lrv |=3D (uint64_t)lr_reg->hw.pirq << ICH_LR_PHYSICAL_SHIFT; } else { - if ( lr->virt.eoi ) + if ( lr_reg->virt.eoi ) lrv |=3D ICH_LR_MAINTENANCE_IRQ; /* Source is only set in GICv2 compatible mode */ if ( vgic_version =3D=3D GIC_V2 ) @@ -1117,8 +1117,8 @@ static void gicv3_write_lr(int lr_reg, const struct g= ic_lr *lr) * Source is only valid for SGIs, the caller should make * sure the field virt.source is always 0 for non-SGI. */ - ASSERT(!lr->virt.source || lr->virq < NR_GIC_SGI); - lrv |=3D (uint64_t)lr->virt.source << ICH_LR_CPUID_SHIFT; + ASSERT(!lr_reg->virt.source || lr_reg->virq < NR_GIC_SGI); + lrv |=3D (uint64_t)lr_reg->virt.source << ICH_LR_CPUID_SHIFT; } } =20 @@ -1129,7 +1129,7 @@ static void gicv3_write_lr(int lr_reg, const struct g= ic_lr *lr) if ( vgic_version =3D=3D GIC_V3 ) lrv |=3D ICH_LR_GRP1; =20 - gicv3_ich_write_lr(lr_reg, lrv); + gicv3_ich_write_lr(lr, lrv); } =20 static void gicv3_hcr_status(uint32_t flag, bool status) diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h index f1ef347edc..03f209529b 100644 --- a/xen/arch/arm/include/asm/gic.h +++ b/xen/arch/arm/include/asm/gic.h @@ -246,7 +246,7 @@ void gic_set_irq_type(struct irq_desc *desc, unsigned i= nt type); =20 /* Program the GIC to route an interrupt */ extern void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int prior= ity); -extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, +extern int gic_route_irq_to_guest(struct domain *d, unsigned int virq, struct irq_desc *desc, unsigned int priority); =20 @@ -330,11 +330,11 @@ struct gic_hw_operations { /* Initialize the GIC and the boot CPU */ int (*init)(void); /* Save GIC registers */ - void (*save_state)(struct vcpu *); + void (*save_state)(struct vcpu *v); /* Restore GIC registers */ - void (*restore_state)(const struct vcpu *); + void (*restore_state)(const struct vcpu *v); /* Dump GIC LR register information */ - void (*dump_state)(const struct vcpu *); + void (*dump_state)(const struct vcpu *v); =20 /* hw_irq_controller to enable/disable/eoi host irq */ hw_irq_controller *gic_host_irq_type; @@ -369,9 +369,9 @@ struct gic_hw_operations { /* Clear LR register */ void (*clear_lr)(int lr); /* Read LR register and populate gic_lr structure */ - void (*read_lr)(int lr, struct gic_lr *); + void (*read_lr)(int lr, struct gic_lr *lr_reg); /* Write LR register from gic_lr structure */ - void (*write_lr)(int lr, const struct gic_lr *); + void (*write_lr)(int lr, const struct gic_lr *lr_reg); /* Read VMCR priority */ unsigned int (*read_vmcr_priority)(void); /* Read APRn register */ --=20 2.34.1