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charset="utf-8" Signed-off-by: Teddy Astie --- xen/arch/x86/cpu/common.c | 2 ++ xen/arch/x86/include/asm/cpufeature.h | 4 ++++ xen/include/public/arch-x86/cpufeatureset.h | 5 +++++ xen/include/xen/lib/x86/cpu-policy.h | 9 ++++++++- 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index e8d4ca3203..a610b0f513 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -481,6 +481,8 @@ static void generic_identify(struct cpuinfo_x86 *c) c->x86_capability[FEATURESET_e8b] =3D cpuid_ebx(0x80000008); if (c->extended_cpuid_level >=3D 0x80000021) c->x86_capability[FEATURESET_e21a] =3D cpuid_eax(0x80000021); + if (c->extended_cpuid_level >=3D 0x8000001f) + c->x86_capability[FEATURESET_e1fa] =3D cpuid_eax(0x8000001f); =20 /* Intel-defined flags: level 0x00000007 */ if (c->cpuid_level >=3D 7) { diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index 397a04af41..bded70231c 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -233,6 +233,10 @@ static inline bool boot_cpu_has(unsigned int feat) =20 #define cpu_has_msr_tsc_aux (cpu_has_rdtscp || cpu_has_rdpid) =20 +#define cpu_has_sme boot_cpu_has(X86_FEATURE_SME) +#define cpu_has_sev boot_cpu_has(X86_FEATURE_SEV) +#define cpu_has_sev_es boot_cpu_has(X86_FEATURE_SEV_ES) + /* Bugs. */ #define cpu_bug_fpu_ptrs boot_cpu_has(X86_BUG_FPU_PTRS) #define cpu_bug_null_seg boot_cpu_has(X86_BUG_NULL_SEG) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index a6d4a0cba7..2a67bcc6a4 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -394,6 +394,11 @@ XEN_CPUFEATURE(MON_UMON_MITG, 16*32+30) /* MCU_= OPT_CTRL.MON_UMON_MITG */ /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.edx, word 17 (express i= n terms of word 16) */ XEN_CPUFEATURE(ITS_NO, 16*32+62) /*!A No Indirect Target Selec= tion */ =20 +/* AMD-defined CPU features, CPUID level 0x8000001f.eax, word 18 */ +XEN_CPUFEATURE(SME, 18*32+ 0) /* Secure Memory Encryption= */ +XEN_CPUFEATURE(SEV, 18*32+ 1) /* Secure Encrypted Virtual= ization */ +XEN_CPUFEATURE(SEV_ES, 18*32+ 3) /* SEV Encrypted State */ + #endif /* XEN_CPUFEATURE */ =20 /* Clean up from a default include. Close the enum (for C). */ diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86= /cpu-policy.h index f43e1a3b21..a5b22b34d8 100644 --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -22,6 +22,7 @@ #define FEATURESET_7d1 15 /* 0x00000007:1.edx */ #define FEATURESET_m10Al 16 /* 0x0000010a.eax */ #define FEATURESET_m10Ah 17 /* 0x0000010a.edx */ +#define FEATURESET_e1fa 18 /* 0x8000001f.eax */ =20 struct cpuid_leaf { @@ -317,7 +318,13 @@ struct cpu_policy uint64_t :64, :64; /* Leaf 0x8000001c. */ uint64_t :64, :64; /* Leaf 0x8000001d - Cache properties. */ uint64_t :64, :64; /* Leaf 0x8000001e - Extd APIC/Core/Node ID= s. */ - uint64_t :64, :64; /* Leaf 0x8000001f - AMD Secure Encryption.= */ + /* Leaf 0x8000001f - AMD Secure Memory Encryption. */ + union { + uint32_t e1fa; + struct { DECL_BITFIELD(e1fa); }; + }; + uint32_t c_bit_pos:6, physaddr_red:6, num_vmpl:4, :16; + uint32_t max_sev_guests:32, min_no_es_asid; uint64_t :64, :64; /* Leaf 0x80000020 - Platform QoS. */ =20 /* Leaf 0x80000021 - Extended Feature 2 */ --=20 2.49.0 Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech