From nobody Mon Feb 9 22:05:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1607531725; cv=none; d=zohomail.com; s=zohoarc; b=ENzibpzctAsn4NcmQXMLNTU1x6iBKuCYegFT52yts+6mvoQsUMd5pLBpFKEbodQqVThGTmbNrx8TDu3a4rBtlU1LGlfnB8PaAgEEnrVbxF1gaMnR/MlAACHT7z1D6PRdXpTyR3nK1+Xk0Kk3NaJp1MeBB51MTJ7Vl+XDfH+HDjQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607531725; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=8fPrMd84mQEg/KjO+0n3mkndqIHZnYBdJK0I3DaxC3o=; b=ST2O+nEVfrE/6D8oF9dwVesOOps4EzR5V2/a/Tfe+IKrGBb8ZUwi+z/QgChGU0qpZQEMeDTlm9vkAU3LowYzdHayVeggc8O2PozQi9BA5qtTU90p0GjBWDFtndkUWkMJvcLId/St5fbjPXz+AkWrK9BdZ2dEa19GCx54QBYRPB4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1607531725926566.5139185778875; Wed, 9 Dec 2020 08:35:25 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.48543.85922 (Exim 4.92) (envelope-from ) id 1kn2Qr-0007Xv-GT; Wed, 09 Dec 2020 16:35:13 +0000 Received: by outflank-mailman (output) from mailman id 48543.85922; Wed, 09 Dec 2020 16:35:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qr-0007Xh-By; Wed, 09 Dec 2020 16:35:13 +0000 Received: by outflank-mailman (input) for mailman id 48543; Wed, 09 Dec 2020 16:35:11 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qp-0007Ej-Ov for xen-devel@lists.xenproject.org; Wed, 09 Dec 2020 16:35:11 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id b11871d3-465d-40c5-a2f5-4589f0a988cb; Wed, 09 Dec 2020 16:34:58 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6728C1FB; Wed, 9 Dec 2020 08:34:58 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B6EBB3F68F; Wed, 9 Dec 2020 08:34:57 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b11871d3-465d-40c5-a2f5-4589f0a988cb From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 4/7] xen/arm: Add handler for ID registers on arm64 Date: Wed, 9 Dec 2020 16:30:57 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add vsysreg emulation for registers trapped when TID3 bit is activated in HSR. The emulation is returning the value stored in cpuinfo_guest structure for know registers and is handling reserved registers as RAZ. Signed-off-by: Bertrand Marquis --- Changes in V2: Rebase Changes in V3: Fix commit message Fix code style for GENERATE_TID3_INFO declaration Add handling of reserved registers as RAZ. --- xen/arch/arm/arm64/vsysreg.c | 53 ++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 8a85507d9d..ef7a11dbdd 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -69,6 +69,14 @@ TVM_REG(CONTEXTIDR_EL1) break; \ } =20 +/* Macro to generate easily case for ID co-processor emulation */ +#define GENERATE_TID3_INFO(reg, field, offset) \ + case HSR_SYSREG_##reg: \ + { \ + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, \ + 1, guest_cpuinfo.field.bits[offset]); \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -259,6 +267,51 @@ void do_sysreg(struct cpu_user_regs *regs, */ return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); =20 + /* + * HCR_EL2.TID3 + * + * This is trapping most Identification registers used by a guest + * to identify the processor features + */ + GENERATE_TID3_INFO(ID_PFR0_EL1, pfr32, 0) + GENERATE_TID3_INFO(ID_PFR1_EL1, pfr32, 1) + GENERATE_TID3_INFO(ID_PFR2_EL1, pfr32, 2) + GENERATE_TID3_INFO(ID_DFR0_EL1, dbg32, 0) + GENERATE_TID3_INFO(ID_DFR1_EL1, dbg32, 1) + GENERATE_TID3_INFO(ID_AFR0_EL1, aux32, 0) + GENERATE_TID3_INFO(ID_MMFR0_EL1, mm32, 0) + GENERATE_TID3_INFO(ID_MMFR1_EL1, mm32, 1) + GENERATE_TID3_INFO(ID_MMFR2_EL1, mm32, 2) + GENERATE_TID3_INFO(ID_MMFR3_EL1, mm32, 3) + GENERATE_TID3_INFO(ID_MMFR4_EL1, mm32, 4) + GENERATE_TID3_INFO(ID_MMFR5_EL1, mm32, 5) + GENERATE_TID3_INFO(ID_ISAR0_EL1, isa32, 0) + GENERATE_TID3_INFO(ID_ISAR1_EL1, isa32, 1) + GENERATE_TID3_INFO(ID_ISAR2_EL1, isa32, 2) + GENERATE_TID3_INFO(ID_ISAR3_EL1, isa32, 3) + GENERATE_TID3_INFO(ID_ISAR4_EL1, isa32, 4) + GENERATE_TID3_INFO(ID_ISAR5_EL1, isa32, 5) + GENERATE_TID3_INFO(ID_ISAR6_EL1, isa32, 6) + GENERATE_TID3_INFO(MVFR0_EL1, mvfr, 0) + GENERATE_TID3_INFO(MVFR1_EL1, mvfr, 1) + GENERATE_TID3_INFO(MVFR2_EL1, mvfr, 2) + GENERATE_TID3_INFO(ID_AA64PFR0_EL1, pfr64, 0) + GENERATE_TID3_INFO(ID_AA64PFR1_EL1, pfr64, 1) + GENERATE_TID3_INFO(ID_AA64DFR0_EL1, dbg64, 0) + GENERATE_TID3_INFO(ID_AA64DFR1_EL1, dbg64, 1) + GENERATE_TID3_INFO(ID_AA64ISAR0_EL1, isa64, 0) + GENERATE_TID3_INFO(ID_AA64ISAR1_EL1, isa64, 1) + GENERATE_TID3_INFO(ID_AA64MMFR0_EL1, mm64, 0) + GENERATE_TID3_INFO(ID_AA64MMFR1_EL1, mm64, 1) + GENERATE_TID3_INFO(ID_AA64MMFR2_EL1, mm64, 2) + GENERATE_TID3_INFO(ID_AA64AFR0_EL1, aux64, 0) + GENERATE_TID3_INFO(ID_AA64AFR1_EL1, aux64, 1) + GENERATE_TID3_INFO(ID_AA64ZFR0_EL1, zfr64, 0) + + HSR_SYSREG_TID3_RESERVED_CASE: + /* Handle all reserved registers as RAZ */ + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); + /* * HCR_EL2.TIDCP * --=20 2.17.1