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[109.243.144.234]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493cce03fa1sm284910325e9.11.2026.07.06.08.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2026 08:58:30 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1783353511; x=1783958311; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PMUxY16+EjQiunTHmrdOH7xzPAM+NcHF5gtkkVq7+74=; b=Ycbog57HnGLQpKPY0FJBgCPUJkIfFFDS9NQlxihMMiGuqvKj3c8CHzJW9YhQ+ZOhSG O7sKQyPzHOlT6FI8vTyZowSpve/NhUK1CcYCDBIes0qhZ4oYutBvTAWAr/iQ5i0Xhkfp z7qwHT4DyKNrU3LSAXaNmYud3I6RNEVmSe0QH10XZb+5V1qToGvtdvj2daAtC5VfU26/ sGlXchqPU9Bpet9md938u/C6xAJRUHljFHd3mXIQBu2l49TF2DDFuj5bVcZwZ/T8xQoe tD50KM9FyQHBLaRDEFl+q2saxl/2C/xruhVM/vHy8w9pxAFfLLZ69ojFq2GJjkIrccOM jzGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783353511; x=1783958311; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=PMUxY16+EjQiunTHmrdOH7xzPAM+NcHF5gtkkVq7+74=; b=iM2cd1gLtdrrc0AiGB49xWFGcRMMJoX5tD4eLrabSSnqwrbNpN7uR2seUr/AKXGgNQ 0vGCPDbt9SQS8i5hyjvRUkf6GUaCAAzjtxfLcz4ryUGeXQQvTQu98YlVHpUW9y9oXC8b hzBFc26gKic5NP6QMBNIJg51Rnhncnq/ocbIvaz5O7QR131vMW+Slg672h6gzR/YY3m+ TYdTpPcQpLEwArCGq2hny+V+Ic7mS2+pTZ3SrDPPsBxjnaueGUTUanEZOdrnA4Y7YA6T 7zqGXMphqEjAGlRtRTLfef0+aKjG5F4XpFHd6bhKGGRyQ/W1fH3AGKzVTrgvA2oDpf0i Eudw== X-Gm-Message-State: AOJu0YxyKjcDVg8Vedyqf33fjy0puzYvrJnKOnlt/BkR4zKOe00pov58 knlI3R48As0yZ2FVe+sIEZIGmcWy5Vqsw7/Gn7EiIyEk0Q5VBAc8z+15EAWh9w== X-Gm-Gg: AfdE7cmpgWKX8h7LPkwvvkbaebVjruvYdJUVhDz0RLMfDDnJOvvI81LnSUnUkxweRTu SxDao/9z2YBzUTbUk9E7TtaqvXIiy1sqLA5ZWIZnAN8eAYbhopU1QJxmbiCobiX7mtBbxv7Zca9 QzxIfyKIVodV1lQ9gg77RAURAYnlCJxq6dedAIGgJqxj5lmIiZ7l8Weh3HXpIsiRJQ/UqhjeAMg Dhr6zWKxO+EgAi1apSj4nhLt2t27ix8J+v/UaMQ4U3tDbXfvNlbC3XJ4UEjisv6ZTZW91yF+nbQ /GHf4BVqKwGdvx3LWTFCb6mblD/O5HJi3BbZc1Y1fD3KiAjOOOLEiegQG1CBKRiSjQXR/lZjrBD 6yCncCyUUs9WCqfPlpHI89/TFArV/rU8Zq7nnncqU9He+BeTw7D7gXArUjstKbaPf7Sadgg37T3 gOST7CLVQEX+9Uk69CoIz+XYKbU5LhW69K91fcYZKSqaKMVROCbwDgqvq0bg== X-Received: by 2002:a7b:cc81:0:b0:493:cc01:807b with SMTP id 5b1f17b1804b1-493df0a0861mr10499455e9.38.1783353510795; Mon, 06 Jul 2026 08:58:30 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Baptiste Le Duc , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v5 09/26] xen/riscv: introduce guest riscv,isa string Date: Mon, 6 Jul 2026 17:57:50 +0200 Message-ID: X-Mailer: git-send-email 2.54.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-42698a/1783353511-A5523220-BF0D7000/10/73395122804 X-purgate-type: spam X-purgate-size: 11522 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1783353546858158500 Content-Type: text/plain; charset="utf-8" Introduce build_guest_isa_str() to generate the riscv,isa string to be passed to the guest via the Device Tree riscv,isa property. Introduce the per-domain guest ISA bitmap, populated during domain creation by calling init_guest_isa(). Introduce struct riscv_isa_ext_entry with a new guest_supported field to filter out ISA extensions that should not be exposed to guests: - f/d/q/v: FPU and vector context save/restore are not yet implemented for guests. - Z*inx are not exposed either: they aren't in riscv_isa_ext[], so they can never be set in riscv_isa and thus never reach a guest, and no current hardware/guest-OS advertises or expects them. Supporting them would be cheaper than F/D/Q (FP values stay in integer registers Xen already context-switches), but is left as future work. - h: Nested virtualisation is not supported. - sstc: Xen owns the supervisor timer; guests must use SBI. - svade: Xen manages hardware A/D bit updates in stage-2 page tables. - svpbmt: Page-based memory types are not yet wired up in stage-2 code. Drop __initconst for riscv_isa_ext[] as it can be used after init stage by init_guest_isa(). Signed-off-by: Oleksii Kurochko --- Changes in v5: - Introduce struct riscv_isa_ext_entry with a guest_supported field and RISCV_ISA_EXT_ENTRY(name, guest_supp) macro for riscv_isa_ext[], replacing the ad-hoc guest_unsupp bitmap and init_guest_unsupp(). Every entry now carries an explicit true/false decision, enforced at compile time. - init_guest_isa() builds d->arch.isa by iterating riscv_isa_ext[] directly instead of using bitmap_andnot() against guest_unsupp. - init_guest_isa() changed to void as it can no longer fail. - Drop isa_str from struct arch_domain; the ISA string does not need to persist over the domain lifetime. build_guest_isa_str() is made non-static and declared in cpufeature.h for use when building the guest device tree. - Updated the fix of underflow in build_guest_isa_str(). - Drop unnecessary empty line in cpufeature.h before enum riscv_isa_ext_id. --- Changes in v4: - Add an explicit overflow guard in build_guest_isa_str(): return -ENOSPC when buf is non-NULL and total >=3D size, to avoid the size - total underflow being passed to snprintf(). - Expand the commit message to explain why Zfinx/Zdinx/Zqinx are not added to guest_unsupp (not in riscv_isa_ext[], so never set in riscv_isa nor exposed to a guest; left as future work) --- Changes in v3: - s/set_bit/__set_bit in init_guest_unsupp() as atomicity isn't needed at init time. - Drop RISCV_GUEST_ISA_STR_MAX; allocate isa_str dynamically with xvmalloc_array(). - Drop "guest" prefix from d->arch.guest_isa and d->arch.guest_isa_str. - Introduce build_guest_isa_str() using snprintf(NULL, 0, ...) to determine the needed buffer size; init_guest_isa() calls it once for sizing and on= ce to fill, keeping both in a single function so they can't go out of sync. - Scope ret inside the loop; initialize total directly from the prefix snprintf(). - Merge "_" separator and extension name into a single snprintf() with "%s%s". - Replace ASSERT with an explicit error check: if the fill call returns a different length, free isa_str and return -EINVAL. --- Changes in v2: - s/guest_unsupp_bmp/guest_unsupp. - Drop guest_isa_str. - Provide init_guest_isa() instead of polluting match_isa_ext(). - Drop xlen. - Add the comment about guest_unsupp. - Update the way how guest_unsupp is init-ed. - Drop __initconst for riscv_isa_ext[] as it is used in init_guest_isa() which isn't marked as __init as it could be used after init stage. --- --- xen/arch/riscv/cpufeature.c | 132 +++++++++++++++++++----- xen/arch/riscv/domain.c | 2 + xen/arch/riscv/include/asm/cpufeature.h | 6 ++ xen/arch/riscv/include/asm/domain.h | 3 + 4 files changed, 119 insertions(+), 24 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 92235fdfd5ab..5002ddc92a22 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 #include @@ -34,6 +35,19 @@ struct riscv_isa_ext_data { .name =3D #ext_name, \ } =20 +struct riscv_isa_ext_entry { + unsigned int id; + const char *name; + bool guest_supported; +}; + +#define RISCV_ISA_EXT_ENTRY(ext_name, guest_supp) \ +{ \ + .id =3D RISCV_ISA_EXT_ ## ext_name, \ + .name =3D #ext_name, \ + .guest_supported =3D guest_supp, \ +} + /* Host ISA bitmap */ static __ro_after_init DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX); =20 @@ -120,29 +134,30 @@ static int __init dt_get_cpuid_from_node(const struct= dt_device_node *cpu, * and strncmp() is used in match_isa_ext() to compare extension names ins= tead * of strncasecmp(). */ -const struct riscv_isa_ext_data __initconst riscv_isa_ext[] =3D { - RISCV_ISA_EXT_DATA(i), - RISCV_ISA_EXT_DATA(m), - RISCV_ISA_EXT_DATA(a), - RISCV_ISA_EXT_DATA(f), - RISCV_ISA_EXT_DATA(d), - RISCV_ISA_EXT_DATA(q), - RISCV_ISA_EXT_DATA(c), - RISCV_ISA_EXT_DATA(h), - RISCV_ISA_EXT_DATA(zicntr), - RISCV_ISA_EXT_DATA(zicsr), - RISCV_ISA_EXT_DATA(zifencei), - RISCV_ISA_EXT_DATA(zihintpause), - RISCV_ISA_EXT_DATA(zihpm), - RISCV_ISA_EXT_DATA(zba), - RISCV_ISA_EXT_DATA(zbb), - RISCV_ISA_EXT_DATA(zbs), - RISCV_ISA_EXT_DATA(smaia), - RISCV_ISA_EXT_DATA(smstateen), - RISCV_ISA_EXT_DATA(ssaia), - RISCV_ISA_EXT_DATA(sstc), - RISCV_ISA_EXT_DATA(svade), - RISCV_ISA_EXT_DATA(svpbmt), +const struct riscv_isa_ext_entry riscv_isa_ext[] =3D { + RISCV_ISA_EXT_ENTRY(i, true), + RISCV_ISA_EXT_ENTRY(m, true), + RISCV_ISA_EXT_ENTRY(a, true), + RISCV_ISA_EXT_ENTRY(f, false), + RISCV_ISA_EXT_ENTRY(d, false), + RISCV_ISA_EXT_ENTRY(q, false), + RISCV_ISA_EXT_ENTRY(c, true), + RISCV_ISA_EXT_ENTRY(v, false), + RISCV_ISA_EXT_ENTRY(h, false), + RISCV_ISA_EXT_ENTRY(zicntr, true), + RISCV_ISA_EXT_ENTRY(zicsr, true), + RISCV_ISA_EXT_ENTRY(zifencei, true), + RISCV_ISA_EXT_ENTRY(zihintpause, true), + RISCV_ISA_EXT_ENTRY(zihpm, true), + RISCV_ISA_EXT_ENTRY(zba, true), + RISCV_ISA_EXT_ENTRY(zbb, true), + RISCV_ISA_EXT_ENTRY(zbs, true), + RISCV_ISA_EXT_ENTRY(smaia, true), + RISCV_ISA_EXT_ENTRY(smstateen, true), + RISCV_ISA_EXT_ENTRY(ssaia, true), + RISCV_ISA_EXT_ENTRY(sstc, false), + RISCV_ISA_EXT_ENTRY(svade, false), + RISCV_ISA_EXT_ENTRY(svpbmt, false), }; =20 static const struct riscv_isa_ext_data __initconst required_extensions[] = =3D { @@ -181,7 +196,7 @@ static void __init match_isa_ext(const char *name, cons= t char *name_end, =20 for ( unsigned int i =3D 0; i < riscv_isa_ext_count; i++ ) { - const struct riscv_isa_ext_data *ext =3D &riscv_isa_ext[i]; + const struct riscv_isa_ext_entry *ext =3D &riscv_isa_ext[i]; =20 /* * `ext->name` (according to initialization of riscv_isa_ext[] @@ -480,6 +495,74 @@ bool riscv_isa_extension_available(const unsigned long= *isa_bitmap, return test_bit(id, isa_bitmap); } =20 +int build_guest_isa_str(char *buf, size_t size, + const unsigned long *isa_bitmap) +{ + char *p =3D buf; + size_t left =3D size; + int total; + +#if defined(CONFIG_RISCV_32) + total =3D snprintf(p, left, "rv32"); +#elif defined(CONFIG_RISCV_64) + total =3D snprintf(p, left, "rv64"); +#else +# error "Unsupported RISC-V bitness" +#endif + + if ( total < 0 ) + return total; + + if ( buf ) + { + if ( (size_t)total >=3D left ) + return -ENOSPC; + + p +=3D total; + left -=3D total; + } + + for ( unsigned int i =3D 0; i < ARRAY_SIZE(riscv_isa_ext); i++ ) + { + const struct riscv_isa_ext_entry *ext =3D &riscv_isa_ext[i]; + int ret; + + if ( !riscv_isa_extension_available(isa_bitmap, ext->id) ) + continue; + + ret =3D snprintf(p, left, "%s%s", + ext->id >=3D RISCV_ISA_EXT_BASE ? "_" : "", + ext->name); + if ( ret < 0 ) + return ret; + + total +=3D ret; + + if ( buf ) + { + if ( (size_t)ret >=3D left ) + return -ENOSPC; + + p +=3D ret; + left -=3D ret; + } + } + + return total; +} + +void init_guest_isa(struct domain *d) +{ + for ( unsigned int i =3D 0; i < ARRAY_SIZE(riscv_isa_ext); i++ ) + { + const struct riscv_isa_ext_entry *ext =3D &riscv_isa_ext[i]; + + if ( ext->guest_supported && + riscv_isa_extension_available(NULL, ext->id) ) + __set_bit(ext->id, d->arch.isa); + } +} + void __init riscv_fill_hwcap(void) { unsigned int i; @@ -527,4 +610,5 @@ void __init riscv_fill_hwcap(void) if ( !all_extns_available ) panic("Look why the extensions above are needed in " "https://xenbits.xenproject.org/docs/unstable/misc/riscv/boo= ting.txt\n"); + } diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 2819ff4e7c92..c9933147595e 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -308,6 +308,8 @@ int arch_domain_create(struct domain *d, if ( is_idle_domain(d) ) return 0; =20 + init_guest_isa(d); + if ( (rc =3D p2m_init(d, config)) !=3D 0) goto fail; =20 diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index 0c48d57a03bb..e26f5f0b66fb 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -5,6 +5,7 @@ #ifndef __ASSEMBLER__ =20 #include +#include =20 /* * These macros represent the logical IDs of each multi-letter RISC-V ISA @@ -44,7 +45,12 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_MAX }; =20 +struct domain; + void riscv_fill_hwcap(void); +void init_guest_isa(struct domain *d); +int build_guest_isa_str(char *buf, size_t size, + const unsigned long *isa_bitmap); =20 bool riscv_isa_extension_available(const unsigned long *isa_bitmap, enum riscv_isa_ext_id id); diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 6044ce0feee0..235b20f8a6ba 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -7,6 +7,7 @@ #include #include =20 +#include #include #include #include @@ -94,6 +95,8 @@ struct arch_domain { struct p2m_domain p2m; =20 struct paging_domain paging; + + DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX); }; =20 #include --=20 2.54.0