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Tue, 22 Apr 2025 15:07:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7f7a7aab-1f8b-11f0-9ffb-bf95429c2676 Authentication-Results: garm.ovh; auth=pass (GARM-105G006674ba4df-a111-49e8-8f59-2ab0d0e0c115, 7E508E014E7E7C169EB13C6E22C3C4EBF1F0FDD7) smtp.auth=sergii.dmytruk@3mdeb.com X-OVh-ClientIp: 176.111.181.178 From: Sergii Dmytruk To: xen-devel@lists.xenproject.org Cc: Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , trenchboot-devel@googlegroups.com Subject: [PATCH 07/21] x86/mtrr: expose functions for pausing caching Date: Tue, 22 Apr 2025 18:06:41 +0300 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 12730268772191679644 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgddvgeegtdehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgvrhhgihhiucffmhihthhruhhkuceoshgvrhhgihhirdgumhihthhruhhkseefmhguvggsrdgtohhmqeenucggtffrrghtthgvrhhnpefhheefheduieelieekfffgfffgfedutdevleevvdfhfffgledvgfdtuddtheefieenucfkphepuddvjedrtddrtddruddpudejiedrudduuddrudekuddrudejkedpfeejrdehledrudegvddruddtheenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepihhnvghtpeduvdejrddtrddtrddupdhmrghilhhfrhhomhepshgvrhhgihhirdgumhihthhruhhkseefmhguvggsrdgtohhmpdhnsggprhgtphhtthhopedupdhrtghpthhtohepgigvnhdquggvvhgvlheslhhishhtshdrgigvnhhprhhojhgvtghtrdhorhhgpdfovfetjfhoshhtpehmohehiedtmgdpmhhouggvpehsmhhtphhouhht DKIM-Signature: a=rsa-sha256; bh=p5/X8odYi3YN7N37QJCMftuc5hqSiV9vDM1ybqq3iiI=; c=relaxed/relaxed; d=3mdeb.com; h=From; s=ovhmo3617313-selector1; t=1745334444; v=1; b=l1vUQY5hsQn3ZgjUTDZJJXrr01X7MmNzXwCZd8f8lJEWw5Cx/7e1M/N9kRWj6XJMfCx+hQO+ kXk8/lMQSTXgwmEmmIPuvZlL8gBXMyD4X7Eqa6K3YnEZWM5uxDmJ3Aum/d+WPK4IuRWugyoLF5i fAa9hu8CfIqKaQ0CHRPKN961MQ0rDkDJitet6UxKq2w55AYbPFoqQx48FS/ZlG33yl6WHK7Ozlx i8fmzi8ebwqwPUoMje2PADCKCgFWLQmLyqR77x288GddgCSFTZzQSUa8AA6fq7s4jPvHJS6OYuE b/a7By/oOkqZDTmcUapk8+CCZwpAcHCJ9VsbTttgKRvPQ== X-ZohoMail-DKIM: pass (identity @3mdeb.com) X-ZM-MESSAGEID: 1745334472956019000 Content-Type: text/plain; charset="utf-8" This allows the functionality to be reused by other units that need to update MTRRs. This also gets rid of a static variable. Signed-off-by: Sergii Dmytruk --- xen/arch/x86/cpu/mtrr/generic.c | 51 ++++++++++++++++----------------- xen/arch/x86/include/asm/mtrr.h | 8 ++++++ 2 files changed, 33 insertions(+), 26 deletions(-) diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generi= c.c index c587e9140e..2a8dd1d8ff 100644 --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -396,9 +396,7 @@ static bool set_mtrr_var_ranges(unsigned int index, str= uct mtrr_var_range *vr) return changed; } =20 -static uint64_t deftype; - -static unsigned long set_mtrr_state(void) +static unsigned long set_mtrr_state(uint64_t *deftype) /* [SUMMARY] Set the MTRR state for this CPU. The MTRR state information to read. Some relevant CPU context. @@ -416,14 +414,12 @@ static unsigned long set_mtrr_state(void) if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) change_mask |=3D MTRR_CHANGE_MASK_FIXED; =20 - /* Set_mtrr_restore restores the old value of MTRRdefType, - so to set it we fiddle with the saved value */ - if ((deftype & 0xff) !=3D mtrr_state.def_type - || MASK_EXTR(deftype, MTRRdefType_E) !=3D mtrr_state.enabled - || MASK_EXTR(deftype, MTRRdefType_FE) !=3D mtrr_state.fixed_enabled) { - deftype =3D (deftype & ~0xcff) | mtrr_state.def_type | - MASK_INSR(mtrr_state.enabled, MTRRdefType_E) | - MASK_INSR(mtrr_state.fixed_enabled, MTRRdefType_FE); + if ((*deftype & 0xff) !=3D mtrr_state.def_type + || MASK_EXTR(*deftype, MTRRdefType_E) !=3D mtrr_state.enabled + || MASK_EXTR(*deftype, MTRRdefType_FE) !=3D mtrr_state.fixed_enabled)= { + *deftype =3D (*deftype & ~0xcff) | mtrr_state.def_type | + MASK_INSR(mtrr_state.enabled, MTRRdefType_E) | + MASK_INSR(mtrr_state.fixed_enabled, MTRRdefType_FE); change_mask |=3D MTRR_CHANGE_MASK_DEFTYPE; } =20 @@ -440,9 +436,10 @@ static DEFINE_SPINLOCK(set_atomicity_lock); * has been called. */ =20 -static bool prepare_set(void) +struct mtrr_pausing_state mtrr_pause_caching(void) { unsigned long cr4; + struct mtrr_pausing_state state; =20 /* Note that this is not ideal, since the cache is only flushed/disabled for this CPU while the MTRRs are changed, but changing this requires @@ -462,7 +459,9 @@ static bool prepare_set(void) alternative("wbinvd", "", X86_FEATURE_XEN_SELFSNOOP); =20 cr4 =3D read_cr4(); - if (cr4 & X86_CR4_PGE) + state.pge =3D cr4 & X86_CR4_PGE; + + if (state.pge) write_cr4(cr4 & ~X86_CR4_PGE); else if (use_invpcid) invpcid_flush_all(); @@ -470,27 +469,27 @@ static bool prepare_set(void) write_cr3(read_cr3()); =20 /* Save MTRR state */ - rdmsrl(MSR_MTRRdefType, deftype); + rdmsrl(MSR_MTRRdefType, state.def_type); =20 /* Disable MTRRs, and set the default type to uncached */ - mtrr_wrmsr(MSR_MTRRdefType, deftype & ~0xcff); + mtrr_wrmsr(MSR_MTRRdefType, state.def_type & ~0xcff); =20 /* Again, only flush caches if we have to. */ alternative("wbinvd", "", X86_FEATURE_XEN_SELFSNOOP); =20 - return cr4 & X86_CR4_PGE; + return state; } =20 -static void post_set(bool pge) +void mtrr_resume_caching(struct mtrr_pausing_state state) { /* Intel (P6) standard MTRRs */ - mtrr_wrmsr(MSR_MTRRdefType, deftype); + mtrr_wrmsr(MSR_MTRRdefType, state.def_type); =20 /* Enable caches */ write_cr0(read_cr0() & ~X86_CR0_CD); =20 /* Reenable CR4.PGE (also flushes the TLB) */ - if (pge) + if (state.pge) write_cr4(read_cr4() | X86_CR4_PGE); else if (use_invpcid) invpcid_flush_all(); @@ -504,15 +503,15 @@ void mtrr_set_all(void) { unsigned long mask, count; unsigned long flags; - bool pge; + struct mtrr_pausing_state pausing_state; =20 local_irq_save(flags); - pge =3D prepare_set(); + pausing_state =3D mtrr_pause_caching(); =20 /* Actually set the state */ - mask =3D set_mtrr_state(); + mask =3D set_mtrr_state(&pausing_state.def_type); =20 - post_set(pge); + mtrr_resume_caching(pausing_state); local_irq_restore(flags); =20 /* Use the atomic bitops to update the global mask */ @@ -537,12 +536,12 @@ void mtrr_set( { unsigned long flags; struct mtrr_var_range *vr; - bool pge; + struct mtrr_pausing_state pausing_state; =20 vr =3D &mtrr_state.var_ranges[reg]; =20 local_irq_save(flags); - pge =3D prepare_set(); + pausing_state =3D mtrr_pause_caching(); =20 if (size =3D=3D 0) { /* The invalid bit is kept in the mask, so we simply clear the @@ -563,7 +562,7 @@ void mtrr_set( mtrr_wrmsr(MSR_IA32_MTRR_PHYSMASK(reg), vr->mask); } =20 - post_set(pge); + mtrr_resume_caching(pausing_state); local_irq_restore(flags); } =20 diff --git a/xen/arch/x86/include/asm/mtrr.h b/xen/arch/x86/include/asm/mtr= r.h index 25d442659d..82ea427ba0 100644 --- a/xen/arch/x86/include/asm/mtrr.h +++ b/xen/arch/x86/include/asm/mtrr.h @@ -66,6 +66,14 @@ extern uint8_t pat_type_2_pte_flags(uint8_t pat_type); extern void mtrr_aps_sync_begin(void); extern void mtrr_aps_sync_end(void); =20 +struct mtrr_pausing_state { + bool pge; + uint64_t def_type; +}; + +extern struct mtrr_pausing_state mtrr_pause_caching(void); +extern void mtrr_resume_caching(struct mtrr_pausing_state state); + extern bool mtrr_var_range_msr_set(struct domain *d, struct mtrr_state *m, uint32_t msr, uint64_t msr_content); extern bool mtrr_fix_range_msr_set(struct domain *d, struct mtrr_state *m, --=20 2.49.0