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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1680753498988100003 QEMU needs to know whether clearing maskbit of a vector is really clearing, or was already cleared before. Currently Xen sends only clearing that bit to the device model, but not setting it, so QEMU cannot detect it. Because of that, QEMU is working this around by checking via /dev/mem, but that isn't the proper approach. It's just a workaround which in fact is racy. Give all necessary information to QEMU by passing all ctrl writes, including masking a vector. While this commit doesn't move the whole maskbit handling to QEMU (as discussed on xen-devel as one of the possibilities), it is a necessary first step anyway. Including telling QEMU it will get all the required information to do so. The actual implementation would need to include: - a hypercall for QEMU to control just maskbit (without (re)binding the interrupt again - a methor for QEMU to tell Xen it will actually do the work Those are not part of this series. Signed-off-by: Marek Marczykowski-G=C3=B3recki --- v3: - advertise changed behavior in XEN_DMOP_get_ioreq_server_info - make "flags" parameter IN/OUT - move len check back to msixtbl_write() - will be needed there anyway in a later patch v2: - passthrough quad writes to emulator too (Jan) - (ab)use len=3D=3D0 for write len=3D4 completion (Jan), but add descripti= ve #define for this magic value Should flags on output include only "out" values (current version), or also include those passed in by the caller unchanged? --- xen/arch/x86/hvm/vmsi.c | 18 ++++++++++++++---- xen/common/ioreq.c | 9 +++++++-- xen/include/public/hvm/dm_op.h | 12 ++++++++---- 3 files changed, 29 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/hvm/vmsi.c b/xen/arch/x86/hvm/vmsi.c index 3cd4923060c8..231253a2cbd4 100644 --- a/xen/arch/x86/hvm/vmsi.c +++ b/xen/arch/x86/hvm/vmsi.c @@ -272,6 +272,15 @@ out: return r; } =20 +/* + * This function returns X86EMUL_UNHANDLEABLE even if write is properly + * handled, to propagate it to the device model (so it can keep its intern= al + * state in sync). + * len=3D=3D0 means really len=3D=3D4, but as a write completion that will= return + * X86EMUL_OKAY on successful processing. Use WRITE_LEN4_COMPLETION to mak= e it + * less confusing. + */ +#define WRITE_LEN4_COMPLETION 0 static int msixtbl_write(struct vcpu *v, unsigned long address, unsigned int len, unsigned long val) { @@ -283,8 +292,9 @@ static int msixtbl_write(struct vcpu *v, unsigned long = address, unsigned long flags; struct irq_desc *desc; =20 - if ( (len !=3D 4 && len !=3D 8) || (address & (len - 1)) ) - return r; + if ( (len !=3D 4 && len !=3D 8 && len !=3D WRITE_LEN4_COMPLETION) || + (len && (address & (len - 1))) ) + return X86EMUL_UNHANDLEABLE; =20 rcu_read_lock(&msixtbl_rcu_lock); =20 @@ -345,7 +355,7 @@ static int msixtbl_write(struct vcpu *v, unsigned long = address, =20 unlock: spin_unlock_irqrestore(&desc->lock, flags); - if ( len =3D=3D 4 ) + if ( len =3D=3D WRITE_LEN4_COMPLETION ) r =3D X86EMUL_OKAY; =20 out: @@ -635,7 +645,7 @@ void msix_write_completion(struct vcpu *v) return; =20 v->arch.hvm.hvm_io.msix_unmask_address =3D 0; - if ( msixtbl_write(v, ctrl_address, 4, 0) !=3D X86EMUL_OKAY ) + if ( msixtbl_write(v, ctrl_address, WRITE_LEN4_COMPLETION, 0) !=3D X86= EMUL_OKAY ) gdprintk(XENLOG_WARNING, "MSI-X write completion failure\n"); } =20 diff --git a/xen/common/ioreq.c b/xen/common/ioreq.c index ecb8f545e1c4..bd6f074c1e85 100644 --- a/xen/common/ioreq.c +++ b/xen/common/ioreq.c @@ -743,7 +743,8 @@ static int ioreq_server_destroy(struct domain *d, ioser= vid_t id) static int ioreq_server_get_info(struct domain *d, ioservid_t id, unsigned long *ioreq_gfn, unsigned long *bufioreq_gfn, - evtchn_port_t *bufioreq_port) + evtchn_port_t *bufioreq_port, + uint16_t *flags) { struct ioreq_server *s; int rc; @@ -779,6 +780,9 @@ static int ioreq_server_get_info(struct domain *d, iose= rvid_t id, *bufioreq_port =3D s->bufioreq_evtchn; } =20 + /* Advertise supported features/behaviors. */ + *flags =3D XEN_DMOP_all_msix_writes; + rc =3D 0; =20 out: @@ -1374,7 +1378,8 @@ int ioreq_server_dm_op(struct xen_dm_op *op, struct d= omain *d, bool *const_op) NULL : (unsigned long *)&data->ioreq_gf= n, (data->flags & XEN_DMOP_no_gfns) ? NULL : (unsigned long *)&data->bufioreq= _gfn, - &data->bufioreq_port); + &data->bufioreq_port, &data->flags); + break; } =20 diff --git a/xen/include/public/hvm/dm_op.h b/xen/include/public/hvm/dm_op.h index acdf91693d0b..490b151c5dd7 100644 --- a/xen/include/public/hvm/dm_op.h +++ b/xen/include/public/hvm/dm_op.h @@ -70,7 +70,9 @@ typedef struct xen_dm_op_create_ioreq_server xen_dm_op_cr= eate_ioreq_server_t; * not contain XEN_DMOP_no_gfns then these pages will be made available and * the frame numbers passed back in gfns and * respectively. (If the IOREQ Server is not handling buffered emulation - * only will be valid). + * only will be valid). When Xen returns XEN_DMOP_all_msix_wri= tes + * flag set, it will notify the IOREQ server about all writes to MSI-X tab= le + * (if it's handled by this IOREQ server), not only those clearing a mask = bit. * * NOTE: To access the synchronous ioreq structures and buffered ioreq * ring, it is preferable to use the XENMEM_acquire_resource memory @@ -81,11 +83,13 @@ typedef struct xen_dm_op_create_ioreq_server xen_dm_op_= create_ioreq_server_t; struct xen_dm_op_get_ioreq_server_info { /* IN - server id */ ioservid_t id; - /* IN - flags */ + /* IN/OUT - flags */ uint16_t flags; =20 -#define _XEN_DMOP_no_gfns 0 -#define XEN_DMOP_no_gfns (1u << _XEN_DMOP_no_gfns) +#define _XEN_DMOP_no_gfns 0 /* IN */ +#define _XEN_DMOP_all_msix_writes 1 /* OUT */ +#define XEN_DMOP_no_gfns (1u << _XEN_DMOP_no_gfns) +#define XEN_DMOP_all_msix_writes (1u << _XEN_DMOP_all_msix_writes) =20 /* OUT - buffered ioreq port */ evtchn_port_t bufioreq_port; --=20 git-series 0.9.1 From nobody Thu May 16 02:35:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1680753499023100004 Add xendevicemodel_get_ioreq_server_info_ext() which additionally returns output flags that XEN_DMOP_get_ioreq_server_info can now return. Do not change signature of existing xendevicemodel_get_ioreq_server_info() so existing users will not need to be changed. This advertises behavior change of "x86/msi: passthrough all MSI-X vector ctrl writes to device model" patch. Signed-off-by: Marek Marczykowski-G=C3=B3recki --- v3: - new patch Should there be some HAVE_* #define in the header? Does this change require soname bump (I hope it doesn't...). --- tools/include/xendevicemodel.h | 23 +++++++++++++++++++++++ tools/libs/devicemodel/core.c | 16 ++++++++++++++-- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/tools/include/xendevicemodel.h b/tools/include/xendevicemodel.h index 797e0c6b2961..77a99e670551 100644 --- a/tools/include/xendevicemodel.h +++ b/tools/include/xendevicemodel.h @@ -72,6 +72,29 @@ int xendevicemodel_get_ioreq_server_info( evtchn_port_t *bufioreq_port); =20 /** + * This function retrieves the necessary information to allow an + * emulator to use an IOREQ Server, including feature flags. + * + * @parm dmod a handle to an open devicemodel interface. + * @parm domid the domain id to be serviced + * @parm id the IOREQ Server id. + * @parm ioreq_gfn pointer to a xen_pfn_t to receive the synchronous ioreq + * gfn. (May be NULL if not required) + * @parm bufioreq_gfn pointer to a xen_pfn_t to receive the buffered ioreq + * gfn. (May be NULL if not required) + * @parm bufioreq_port pointer to a evtchn_port_t to receive the buffered + * ioreq event channel. (May be NULL if not required) + * @parm flags pointer to receive flags bitmask, see hvm/dm_op.h for detai= ls. + * (May be NULL if not required) + * @return 0 on success, -1 on failure. + */ +int xendevicemodel_get_ioreq_server_info_ext( + xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, + xen_pfn_t *ioreq_gfn, xen_pfn_t *bufioreq_gfn, + evtchn_port_t *bufioreq_port, + unsigned int *flags); + +/** * This function registers a range of memory or I/O ports for emulation. * * @parm dmod a handle to an open devicemodel interface. diff --git a/tools/libs/devicemodel/core.c b/tools/libs/devicemodel/core.c index 8e619eeb0a1f..337622e608c2 100644 --- a/tools/libs/devicemodel/core.c +++ b/tools/libs/devicemodel/core.c @@ -189,10 +189,10 @@ int xendevicemodel_create_ioreq_server( return 0; } =20 -int xendevicemodel_get_ioreq_server_info( +int xendevicemodel_get_ioreq_server_info_ext( xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, xen_pfn_t *ioreq_gfn, xen_pfn_t *bufioreq_gfn, - evtchn_port_t *bufioreq_port) + evtchn_port_t *bufioreq_port, unsigned int *flags) { struct xen_dm_op op; struct xen_dm_op_get_ioreq_server_info *data; @@ -226,9 +226,21 @@ int xendevicemodel_get_ioreq_server_info( if (bufioreq_port) *bufioreq_port =3D data->bufioreq_port; =20 + if (flags) + *flags =3D data->flags; + return 0; } =20 +int xendevicemodel_get_ioreq_server_info( + xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, + xen_pfn_t *ioreq_gfn, xen_pfn_t *bufioreq_gfn, + evtchn_port_t *bufioreq_port) +{ + return xendevicemodel_get_ioreq_server_info_ext( + dmod, domid, id, ioreq_gfn, bufioreq_gfn, bufioreq_port, NULL); +} + int xendevicemodel_map_io_range_to_ioreq_server( xendevicemodel_handle *dmod, domid_t domid, ioservid_t id, int is_mmio, uint64_t start, uint64_t end) --=20 git-series 0.9.1 From nobody Thu May 16 02:35:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1680753501100100001 Some devices (notably Intel Wifi 6 AX210 card) keep auxiliary registers on the same page as MSI-X table. Device model (especially one in stubdomain) cannot really handle those, as direct writes to that page is refused (page is on the mmio_ro_ranges list). Instead, extend msixtbl_mmio_ops to handle such accesses too. Doing this, requires correlating write location with guest view of MSI-X table address. Since QEMU doesn't map MSI-X table to the guest, it requires msixtbl_entry->gtable, which is HVM-only. Similar feature for PV would need to be done separately. This will be also used to read Pending Bit Array, if it lives on the same page, making QEMU not needing /dev/mem access at all (especially helpful with lockdown enabled in dom0). If PBA lives on another page, QEMU will map it to the guest directly. If PBA lives on the same page, discard writes and log a message. Technically, writes outside of PBA could be allowed, but at this moment the precise location of PBA isn't saved, and also no known device abuses the spec in this way (at least yet). To access those registers, msixtbl_mmio_ops need the relevant page mapped. MSI handling already has infrastructure for that, using fixmap, so try to map first/last page of the MSI-X table (if necessary) and save their fixmap indexes. Note that msix_get_fixmap() does reference counting and reuses existing mapping, so just call it directly, even if the page was mapped before. Also, it uses a specific range of fixmap indexes which doesn't include 0, so use 0 as default ("not mapped") value - which simplifies code a bit. GCC gets confused about 'desc' variable: arch/x86/hvm/vmsi.c: In function =E2=80=98msixtbl_range=E2=80=99: arch/x86/hvm/vmsi.c:553:8: error: =E2=80=98desc=E2=80=99 may be used un= initialized [-Werror=3Dmaybe-uninitialized] 553 | if ( desc ) | ^ arch/x86/hvm/vmsi.c:537:28: note: =E2=80=98desc=E2=80=99 was declared h= ere 537 | const struct msi_desc *desc; | ^~~~ It's conditional initialization is actually correct (in the case where it isn't initialized, function returns early), but to avoid build failure initialize it explicitly to NULL anyway. Signed-off-by: Marek Marczykowski-G=C3=B3recki --- v3: - merge handling into msixtbl_mmio_ops - extend commit message v2: - adjust commit message - pass struct domain to msixtbl_page_handler_get_hwaddr() - reduce local variables used only once - log a warning if write is forbidden if MSI-X and PBA lives on the same page - do not passthrough unaligned accesses - handle accesses both before and after MSI-X table --- xen/arch/x86/hvm/vmsi.c | 199 ++++++++++++++++++++++++++++++++-- xen/arch/x86/include/asm/msi.h | 5 +- xen/arch/x86/msi.c | 38 ++++++- 3 files changed, 231 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/hvm/vmsi.c b/xen/arch/x86/hvm/vmsi.c index 231253a2cbd4..6f49493d3f58 100644 --- a/xen/arch/x86/hvm/vmsi.c +++ b/xen/arch/x86/hvm/vmsi.c @@ -181,15 +181,21 @@ static bool msixtbl_initialised(const struct domain *= d) } =20 static struct msixtbl_entry *msixtbl_find_entry( - struct vcpu *v, unsigned long addr) + struct vcpu *v, unsigned long addr, bool same_page) { struct msixtbl_entry *entry; struct domain *d =3D v->domain; =20 list_for_each_entry( entry, &d->arch.hvm.msixtbl_list, list ) + { + if ( same_page && + PFN_DOWN(addr) >=3D PFN_DOWN(entry->gtable) && + PFN_DOWN(addr) <=3D PFN_DOWN(entry->gtable + entry->table_len= ) ) + return entry; if ( addr >=3D entry->gtable && addr < entry->gtable + entry->table_len ) return entry; + } =20 return NULL; } @@ -213,6 +219,144 @@ static struct msi_desc *msixtbl_addr_to_desc( return NULL; } =20 +/* + * Returns: + * - UINT_MAX if no handling should be done + * - UINT_MAX-1 if write should be discarded + * - a fixmap idx to use for handling + */ +#define ADJACENT_DONT_HANDLE UINT_MAX +#define ADJACENT_DISCARD_WRITE (UINT_MAX - 1) +static unsigned int adjacent_handle( + const struct msixtbl_entry *entry, unsigned long addr, bool write) +{ + unsigned int adj_type; + + if ( !entry || !entry->pdev ) + return ADJACENT_DONT_HANDLE; + + if ( PFN_DOWN(addr) =3D=3D PFN_DOWN(entry->gtable) && addr < entry->gt= able ) + adj_type =3D ADJ_IDX_FIRST; + else if ( PFN_DOWN(addr) =3D=3D PFN_DOWN(entry->gtable + entry->table_= len - 1) && + addr >=3D entry->gtable + entry->table_len ) + adj_type =3D ADJ_IDX_LAST; + else + return ADJACENT_DONT_HANDLE; + + ASSERT(entry->pdev->msix); + + if ( !entry->pdev->msix->adj_access_table_idx[adj_type] ) + { + gprintk(XENLOG_WARNING, + "Page for adjacent(%d) MSI-X table access not initialized = for %pp (addr %#lx, gtable %#lx\n", + adj_type, &entry->pdev->sbdf, addr, entry->gtable); + + return ADJACENT_DONT_HANDLE; + } + + /* If PBA lives on the same page too, discard writes. */ + if ( write && ( + (adj_type =3D=3D ADJ_IDX_LAST && + entry->pdev->msix->table.last =3D=3D entry->pdev->msix->pba.first= ) || + (adj_type =3D=3D ADJ_IDX_FIRST && + entry->pdev->msix->table.first =3D=3D entry->pdev->msix->pba.last= )) ) + { + gprintk(XENLOG_WARNING, + "MSI-X table and PBA of %pp live on the same page, " + "writing to other registers there is not implemented\n", + &entry->pdev->sbdf); + return ADJACENT_DISCARD_WRITE; + } + + return entry->pdev->msix->adj_access_table_idx[adj_type]; +} + +static int adjacent_read( + unsigned int fixmap_idx, + uint64_t address, uint32_t len, uint64_t *pval) +{ + const void __iomem *hwaddr; + + *pval =3D ~0UL; + + if ( !IS_ALIGNED(address, len) ) + { + gdprintk(XENLOG_WARNING, + "Dropping unaligned read from MSI-X table page at %" PRIx6= 4 "\n", + address); + return X86EMUL_OKAY; + } + + ASSERT(fixmap_idx !=3D ADJACENT_DISCARD_WRITE); + + hwaddr =3D fix_to_virt(fixmap_idx) + PAGE_OFFSET(address); + + switch ( len ) + { + case 1: + *pval =3D readb(hwaddr); + break; + + case 2: + *pval =3D readw(hwaddr); + break; + + case 4: + *pval =3D readl(hwaddr); + break; + + case 8: + *pval =3D readq(hwaddr); + break; + + default: + ASSERT_UNREACHABLE(); + } + return X86EMUL_OKAY; +} + +static int adjacent_write( + unsigned int fixmap_idx, + uint64_t address, uint32_t len, uint64_t val) +{ + void __iomem *hwaddr; + + if ( !IS_ALIGNED(address, len) ) + { + gdprintk(XENLOG_WARNING, + "Dropping unaligned write to MSI-X table page at %" PRIx64= "\n", + address); + return X86EMUL_OKAY; + } + + if ( fixmap_idx =3D=3D ADJACENT_DISCARD_WRITE ) + return X86EMUL_OKAY; + + hwaddr =3D fix_to_virt(fixmap_idx) + PAGE_OFFSET(address); + + switch ( len ) { + case 1: + writeb(val, hwaddr); + break; + + case 2: + writew(val, hwaddr); + break; + + case 4: + writel(val, hwaddr); + break; + + case 8: + writeq(val, hwaddr); + break; + + default: + ASSERT_UNREACHABLE(); + } + return X86EMUL_OKAY; +} + static int cf_check msixtbl_read( const struct hvm_io_handler *handler, uint64_t address, uint32_t len, uint64_t *pval) @@ -220,16 +364,27 @@ static int cf_check msixtbl_read( unsigned long offset; struct msixtbl_entry *entry; unsigned int nr_entry, index; + unsigned int adjacent_fixmap; int r =3D X86EMUL_UNHANDLEABLE; =20 - if ( (len !=3D 4 && len !=3D 8) || (address & (len - 1)) ) + if ( !IS_ALIGNED(address, len) ) return r; =20 rcu_read_lock(&msixtbl_rcu_lock); - - entry =3D msixtbl_find_entry(current, address); + entry =3D msixtbl_find_entry(current, address, true); if ( !entry ) goto out; + + adjacent_fixmap =3D adjacent_handle(entry, address, false); + if ( adjacent_fixmap !=3D ADJACENT_DONT_HANDLE ) + { + r =3D adjacent_read(adjacent_fixmap, address, len, pval); + goto out; + } + + if ( len !=3D 4 && len !=3D 8 ) + goto out; + offset =3D address & (PCI_MSIX_ENTRY_SIZE - 1); =20 if ( offset !=3D PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET ) @@ -291,16 +446,29 @@ static int msixtbl_write(struct vcpu *v, unsigned lon= g address, int r =3D X86EMUL_UNHANDLEABLE; unsigned long flags; struct irq_desc *desc; + unsigned int adjacent_fixmap; =20 - if ( (len !=3D 4 && len !=3D 8 && len !=3D WRITE_LEN4_COMPLETION) || - (len && (address & (len - 1))) ) - return X86EMUL_UNHANDLEABLE; + if ( len && !IS_ALIGNED(address, len) ) + return r; =20 rcu_read_lock(&msixtbl_rcu_lock); =20 - entry =3D msixtbl_find_entry(v, address); + entry =3D msixtbl_find_entry(v, address, true); if ( !entry ) goto out; + + if ( len !=3D WRITE_LEN4_COMPLETION ) + { + adjacent_fixmap =3D adjacent_handle(entry, address, true); + if ( adjacent_fixmap !=3D ADJACENT_DONT_HANDLE ) + { + r =3D adjacent_write(adjacent_fixmap, address, len, val); + goto out; + } + if ( len !=3D 4 && len !=3D 8 ) + goto out; + } + nr_entry =3D array_index_nospec(((address - entry->gtable) / PCI_MSIX_ENTRY_SIZE), MAX_MSIX_TABLE_ENTRIES); @@ -375,14 +543,23 @@ static bool cf_check msixtbl_range( { struct vcpu *curr =3D current; unsigned long addr =3D r->addr; - const struct msi_desc *desc; + struct msixtbl_entry *entry; + const struct msi_desc *desc =3D NULL; + unsigned int adjacent_fixmap; + =20 ASSERT(r->type =3D=3D IOREQ_TYPE_COPY); =20 rcu_read_lock(&msixtbl_rcu_lock); - desc =3D msixtbl_addr_to_desc(msixtbl_find_entry(curr, addr), addr); + entry =3D msixtbl_find_entry(curr, addr, true); + adjacent_fixmap =3D adjacent_handle(entry, addr, false); + if ( adjacent_fixmap =3D=3D ADJACENT_DONT_HANDLE ) + desc =3D msixtbl_addr_to_desc(entry, addr); rcu_read_unlock(&msixtbl_rcu_lock); =20 + if ( adjacent_fixmap !=3D ADJACENT_DONT_HANDLE ) + return 1; + if ( desc ) return 1; =20 @@ -627,7 +804,7 @@ void msix_write_completion(struct vcpu *v) uint32_t data; =20 rcu_read_lock(&msixtbl_rcu_lock); - desc =3D msixtbl_addr_to_desc(msixtbl_find_entry(v, snoop_addr), + desc =3D msixtbl_addr_to_desc(msixtbl_find_entry(v, snoop_addr, fa= lse), snoop_addr); rcu_read_unlock(&msixtbl_rcu_lock); =20 diff --git a/xen/arch/x86/include/asm/msi.h b/xen/arch/x86/include/asm/msi.h index a53ade95c9ad..d13cf1c1f873 100644 --- a/xen/arch/x86/include/asm/msi.h +++ b/xen/arch/x86/include/asm/msi.h @@ -207,6 +207,10 @@ struct msg_address { PCI_MSIX_ENTRY_SIZE + \ (~PCI_MSIX_BIRMASK & (PAGE_SIZE - 1= ))) =20 +/* indexes in adj_access_table_idx[] below */ +#define ADJ_IDX_FIRST 0 +#define ADJ_IDX_LAST 1 + struct arch_msix { unsigned int nr_entries, used_entries; struct { @@ -214,6 +218,7 @@ struct arch_msix { } table, pba; int table_refcnt[MAX_MSIX_TABLE_PAGES]; int table_idx[MAX_MSIX_TABLE_PAGES]; + int adj_access_table_idx[2]; spinlock_t table_lock; bool host_maskall, guest_maskall; domid_t warned; diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c index d0bf63df1def..c216acbf0e5d 100644 --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -961,6 +961,34 @@ static int msix_capability_init(struct pci_dev *dev, domain_crash(d); /* XXX How to deal with existing mappings? */ } + + /* + * If the MSI-X table doesn't start at the page boundary, map the = first page for + * passthrough accesses. + */ + if ( PAGE_OFFSET(table_paddr) ) + { + int idx =3D msix_get_fixmap(msix, table_paddr, table_paddr); + + if ( idx > 0 ) + msix->adj_access_table_idx[ADJ_IDX_FIRST] =3D idx; + else + gprintk(XENLOG_ERR, "Failed to map first MSI-X table page:= %d\n", idx); + } + /* + * If the MSI-X table doesn't span full page(s), map the last page= for + * passthrough accesses. + */ + if ( PAGE_OFFSET(table_paddr + msix->nr_entries * PCI_MSIX_ENTRY_S= IZE) ) + { + uint64_t entry_paddr =3D table_paddr + msix->nr_entries * PCI_= MSIX_ENTRY_SIZE; + int idx =3D msix_get_fixmap(msix, table_paddr, entry_paddr); + + if ( idx > 0 ) + msix->adj_access_table_idx[ADJ_IDX_LAST] =3D idx; + else + gprintk(XENLOG_ERR, "Failed to map last MSI-X table page: = %d\n", idx); + } } WARN_ON(msix->table.first !=3D (table_paddr >> PAGE_SHIFT)); ++msix->used_entries; @@ -1090,6 +1118,16 @@ static void _pci_cleanup_msix(struct arch_msix *msix) WARN(); msix->table.first =3D 0; msix->table.last =3D 0; + if ( msix->adj_access_table_idx[ADJ_IDX_FIRST] ) + { + msix_put_fixmap(msix, msix->adj_access_table_idx[ADJ_IDX_FIRST= ]); + msix->adj_access_table_idx[ADJ_IDX_FIRST] =3D 0; + } + if ( msix->adj_access_table_idx[ADJ_IDX_LAST] ) + { + msix_put_fixmap(msix, msix->adj_access_table_idx[ADJ_IDX_LAST]= ); + msix->adj_access_table_idx[ADJ_IDX_LAST] =3D 0; + } =20 if ( rangeset_remove_range(mmio_ro_ranges, msix->pba.first, msix->pba.last) ) --=20 git-series 0.9.1 From nobody Thu May 16 02:35:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1680753498316100001 Some firmware/devices are found to not reset MSI-X properly, leaving MASKALL set. Jason reports on his machine MASKALL persists through a warm reboot, but is cleared on cold boot. Xen relies on initial state being MASKALL clear. Especially, pci_reset_msix_state() assumes if MASKALL is set, it was Xen setting it due to msix->host_maskall or msix->guest_maskall. Clearing just MASKALL might be unsafe if ENABLE is set, so clear them both. Reported-by: Jason Andryuk Signed-off-by: Marek Marczykowski-G=C3=B3recki Reviewed-by: Jan Beulich Tested-by: Jason Andryuk --- v3: - update comment - clear bits only when they were set --- xen/drivers/passthrough/msi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/xen/drivers/passthrough/msi.c b/xen/drivers/passthrough/msi.c index ce1a450f6f4a..c9f7eac29ebf 100644 --- a/xen/drivers/passthrough/msi.c +++ b/xen/drivers/passthrough/msi.c @@ -46,6 +46,23 @@ int pdev_msi_init(struct pci_dev *pdev) spin_lock_init(&msix->table_lock); =20 ctrl =3D pci_conf_read16(pdev->sbdf, msix_control_reg(pos)); + + if ( ctrl & (PCI_MSIX_FLAGS_MASKALL|PCI_MSIX_FLAGS_ENABLE) ) + { + /* + * pci_reset_msix_state() relies on MASKALL not being set + * initially, clear it (and ENABLE too - for safety), to meet = that + * expectation. + */ + printk(XENLOG_WARNING + "%pp: unexpected initial MSI-X state (MASKALL=3D%d, ENA= BLE=3D%d), fixing\n", + &pdev->sbdf, + (ctrl & PCI_MSIX_FLAGS_MASKALL) ? 1 : 0, + (ctrl & PCI_MSIX_FLAGS_ENABLE) ? 1 : 0); + ctrl &=3D ~(PCI_MSIX_FLAGS_ENABLE|PCI_MSIX_FLAGS_MASKALL); + pci_conf_write16(pdev->sbdf, msix_control_reg(pos), ctrl); + } + msix->nr_entries =3D msix_table_size(ctrl); =20 pdev->msix =3D msix; --=20 git-series 0.9.1