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charset="utf-8" From: Jean-Philippe Brucker Backport Linux commits cdf315f907d4 and b00d24997a11, adapted to the Xen SMMUv3 implementation. When handling faults from the event or PRI queue, we need to find the struct device associated with a SID. Add an rb_tree to keep track of SIDs. Also handle duplicate SIDs, as bridged PCI devices may have multiple streams with the same SID. The backport is adapted to Xen's SMMUv3 driver structure and types. Fixes are also included in the master insertion rollback and teardown paths to correctly handle partially inserted stream entries and avoid leaving stale rb_tree nodes. Linux commits: cdf315f907d4 ("iommu/arm-smmu-v3: Maintain a SID->device structure") b00d24997a11 ("iommu/arm-smmu-v3: Fix iommu_device_probe bug due to dupli= cated stream ids") Link: https://lore.kernel.org/r/20210401154718.307519-8-jean-philippe@linar= o.org Link: https://lore.kernel.org/r/20250415185620.504299-1-nicolinc@nvidia.com Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git cd= f315f907d4 Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git b0= 0d24997a11 Signed-off-by: Jean-Philippe Brucker Signed-off-by: Joerg Roedel Signed-off-by: Nicolin Chen Signed-off-by: Will Deacon Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/drivers/passthrough/arm/smmu-v3.c | 177 ++++++++++++++++++++++---- xen/drivers/passthrough/arm/smmu-v3.h | 13 +- 2 files changed, 163 insertions(+), 27 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index 232df2421c..d49085b38f 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -809,6 +809,27 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_dev= ice *smmu, u32 sid) return 0; } =20 +__maybe_unused +static struct arm_smmu_master * +arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid) +{ + struct rb_node *node; + struct arm_smmu_stream *stream; + + node =3D smmu->streams.rb_node; + while (node) { + stream =3D rb_entry(node, struct arm_smmu_stream, node); + if (stream->id < sid) + node =3D node->rb_right; + else if (stream->id > sid) + node =3D node->rb_left; + else + return stream->master; + } + + return NULL; +} + /* IRQ and event handlers */ static void arm_smmu_evtq_tasklet(void *dev) { @@ -1042,8 +1063,8 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_ma= ster *master, if (!master->ats_enabled) return 0; =20 - for (i =3D 0; i < master->num_sids; i++) { - cmd->atc.sid =3D master->sids[i]; + for (i =3D 0; i < master->num_streams; i++) { + cmd->atc.sid =3D master->streams[i].id; arm_smmu_cmdq_issue_cmd(master->smmu, cmd); } =20 @@ -1271,13 +1292,13 @@ static void arm_smmu_install_ste_for_dev(struct arm= _smmu_master *master) int i, j; struct arm_smmu_device *smmu =3D master->smmu; =20 - for (i =3D 0; i < master->num_sids; ++i) { - u32 sid =3D master->sids[i]; + for (i =3D 0; i < master->num_streams; ++i) { + u32 sid =3D master->streams[i].id; __le64 *step =3D arm_smmu_get_step_for_sid(smmu, sid); =20 /* Bridged PCI devices may end up with duplicated IDs */ for (j =3D 0; j < i; j++) - if (master->sids[j] =3D=3D sid) + if (master->streams[j].id =3D=3D sid) break; if (j < i) continue; @@ -1486,6 +1507,123 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_d= evice *smmu, u32 sid) =20 return sid < limit; } + +static int arm_smmu_insert_master(struct arm_smmu_device *smmu, + struct arm_smmu_master *master) +{ + int i; + int ret =3D 0; + struct arm_smmu_stream *new_stream, *cur_stream; + struct rb_node **new_node, *parent_node =3D NULL; + struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(master->dev); + bool *insert; + + master->streams =3D _xzalloc_array(sizeof(*master->streams), sizeof(void = *), + fwspec->num_ids); + if (!master->streams) + return -ENOMEM; + + insert =3D _xzalloc_array(sizeof(bool), sizeof(bool *), + fwspec->num_ids); + if (!insert) { + xfree(master->streams); + master->streams =3D NULL; + return -ENOMEM; + } + + master->num_streams =3D fwspec->num_ids; + + mutex_lock(&smmu->streams_mutex); + for (i =3D 0; i < fwspec->num_ids; i++) { + u32 sid =3D fwspec->ids[i]; + insert[i] =3D false; + + new_stream =3D &master->streams[i]; + new_stream->id =3D sid; + new_stream->master =3D master; + RB_CLEAR_NODE(&new_stream->node); + + /* + * Check the SIDs are in range of the SMMU and our stream table + */ + if (!arm_smmu_sid_in_range(smmu, sid)) { + ret =3D -ERANGE; + break; + } + + /* Ensure l2 strtab is initialised */ + if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { + ret =3D arm_smmu_init_l2_strtab(smmu, sid); + if (ret) + break; + } + + /* Insert into SID tree */ + insert[i] =3D true; + new_node =3D &(smmu->streams.rb_node); + while (*new_node) { + cur_stream =3D rb_entry(*new_node, struct arm_smmu_stream, + node); + parent_node =3D *new_node; + if (cur_stream->id > new_stream->id) { + new_node =3D &((*new_node)->rb_left); + } else if (cur_stream->id < new_stream->id) { + new_node =3D &((*new_node)->rb_right); + } else if (cur_stream->master =3D=3D master) { + /* Bridged PCI devices may end up with duplicated IDs */ + insert[i] =3D false; + break; + } + else { + dev_warn(master->dev, + "stream %u already in tree\n", + cur_stream->id); + ret =3D -EINVAL; + insert[i] =3D false; + break; + } + } + if (ret) + break; + + if(insert[i]) { + rb_link_node(&new_stream->node, parent_node, new_node); + rb_insert_color(&new_stream->node, &smmu->streams); + } + } + + if (ret) { + for (i--; i >=3D 0; i--) + if (insert[i]) + rb_erase(&master->streams[i].node, &smmu->streams); + xfree(master->streams); + master->streams =3D NULL; + } + mutex_unlock(&smmu->streams_mutex); + + xfree(insert); + + return ret; +} + +static void arm_smmu_remove_master(struct arm_smmu_master *master) +{ + int i; + struct arm_smmu_device *smmu =3D master->smmu; + struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(master->dev); + + if (!smmu || !master->streams) + return; + + mutex_lock(&smmu->streams_mutex); + for (i =3D 0; i < fwspec->num_ids; i++) + if(!RB_EMPTY_NODE(&master->streams[i].node)) + rb_erase(&master->streams[i].node, &smmu->streams); + mutex_unlock(&smmu->streams_mutex); + + xfree(master->streams); +} + /* Forward declaration */ static struct arm_smmu_device *arm_smmu_get_by_dev(const struct device *de= v); static int arm_smmu_assign_dev(struct domain *d, u8 devfn, struct device *= dev, @@ -1552,7 +1690,7 @@ static int arm_smmu_remove_device(uint8_t devfn, stru= ct device *dev) =20 static int arm_smmu_add_device(u8 devfn, struct device *dev) { - int i, ret; + int ret; struct arm_smmu_device *smmu; struct arm_smmu_master *master; struct iommu_fwspec *fwspec; @@ -1561,7 +1699,6 @@ static int arm_smmu_add_device(u8 devfn, struct devic= e *dev) if ( dev_is_pci(dev) ) { struct pci_dev *pdev =3D dev_to_pci(dev); - int ret; =09 /* Ignore calls for phantom functions */ if ( devfn !=3D pdev->devfn ) @@ -1589,26 +1726,11 @@ static int arm_smmu_add_device(u8 devfn, struct dev= ice *dev) =20 master->dev =3D dev; master->smmu =3D smmu; - master->sids =3D fwspec->ids; - master->num_sids =3D fwspec->num_ids; dev_iommu_priv_set(dev, master); =20 - /* Check the SIDs are in range of the SMMU and our stream table */ - for (i =3D 0; i < master->num_sids; i++) { - u32 sid =3D master->sids[i]; - - if (!arm_smmu_sid_in_range(smmu, sid)) { - ret =3D -ERANGE; - goto err_free_master; - } - - /* Ensure l2 strtab is initialised */ - if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { - ret =3D arm_smmu_init_l2_strtab(smmu, sid); - if (ret) - goto err_free_master; - } - } + ret =3D arm_smmu_insert_master(smmu, master); + if (ret) + goto err_free_master; =20 /* * Note that PASID must be enabled before, and disabled after ATS: @@ -1655,6 +1777,8 @@ static int arm_smmu_add_device(u8 devfn, struct devic= e *dev) return 0; =20 err_free_master: + arm_smmu_disable_pasid(master); + arm_smmu_remove_master(master); xfree(master); dev_iommu_priv_set(dev, NULL); return ret; @@ -1853,6 +1977,9 @@ static int __init arm_smmu_init_structures(struct arm= _smmu_device *smmu) { int ret; =20 + mutex_init(&smmu->streams_mutex); + smmu->streams =3D RB_ROOT; + ret =3D arm_smmu_init_queues(smmu); if (ret) return ret; diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug= h/arm/smmu-v3.h index ab07366294..ab1f29f6c7 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -639,6 +639,15 @@ struct arm_smmu_device { struct tasklet evtq_irq_tasklet; struct tasklet priq_irq_tasklet; struct tasklet combined_irq_tasklet; + + struct rb_root streams; + struct mutex streams_mutex; +}; + +struct arm_smmu_stream { + u32 id; + struct arm_smmu_master *master; + struct rb_node node; }; =20 /* SMMU private data for each master */ @@ -647,8 +656,8 @@ struct arm_smmu_master { struct device *dev; struct arm_smmu_domain *domain; struct list_head domain_head; - u32 *sids; - unsigned int num_sids; + struct arm_smmu_stream *streams; + unsigned int num_streams; bool ats_enabled; }; =20 --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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b=SEIuyTyXyXrT+/UxKvdnjI+EOWQfcThCO2ky/LAnX8YR9pbKoy3ZWRJnE/QiE+gkr1oiObEiQSCacFhRBx6Znp39WF9C4wx30eE/OtxgoIGZV31DYwBKHGMDDhgDQkGI/Dhu/DhSBTmRPmE84FfCB92+GfE1aAXOx7MWmdvjntLwt2fRri/KYYsW1Tux78vdbOwFr3JDslQJh3kqboprAx24/xkJFZn4FWp8KAbhWnNjEciyDkc0RMgImw7OBWxkK8ywApGyAY7ruM0dBGXey8COJTh6mYOycakYZ8Zy9g6qdRuek0cAirfwGpNsZiXZmJYja91GFgfG83ZYzvd2Qw== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Rahul Singh , Bertrand Marquis , Stefano Stabellini , Julien Grall , Michal Orzel , Volodymyr Babchuk , Milan Djokic Subject: [PATCH v5 02/22] xen/arm: smmuv3: Add support for stage-1 and nested stage translation Thread-Topic: [PATCH v5 02/22] xen/arm: smmuv3: Add support for stage-1 and nested stage translation Thread-Index: AQHda7j+0OKnWXqhjk2GUMK3mkLmTQ== Date: Tue, 3 Nov 2026 17:30:17 +0000 Message-ID: <8b40ccc2707fbf02f3d6b1ba48db19c7467af321.1793726692.git.milan_djokic@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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charset="utf-8" From: Rahul Singh Xen SMMUv3 driver only supports stage-2 translation. Add support for Stage-1 translation that is required to support nested stage translation. In true nested mode, both s1_cfg and s2_cfg will coexist. Let's remove the union. When nested stage translation is setup, both s1_cfg and s2_cfg are valid. We introduce a new smmu_domain abort field that will be set upon guest stage-1 configuration passing. If no guest stage-1 config has been attached, it is ignored when writing the STE. arm_smmu_write_strtab_ent() is modified to write both stage fields in the STE and deal with the abort field. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/drivers/passthrough/arm/smmu-v3.c | 98 +++++++++++++++++++++++---- xen/drivers/passthrough/arm/smmu-v3.h | 10 +++ 2 files changed, 96 insertions(+), 12 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index d49085b38f..ecfa7e4723 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -683,8 +683,10 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_= master *master, u32 sid, * 3. Update Config, sync */ u64 val =3D le64_to_cpu(dst[0]); - bool ste_live =3D false; + bool s1_live =3D false, s2_live =3D false, ste_live =3D false; + bool abort, translate =3D false; struct arm_smmu_device *smmu =3D NULL; + struct arm_smmu_s1_cfg *s1_cfg =3D NULL; struct arm_smmu_s2_cfg *s2_cfg =3D NULL; struct arm_smmu_domain *smmu_domain =3D NULL; struct arm_smmu_cmdq_ent prefetch_cmd =3D { @@ -699,30 +701,57 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, smmu =3D master->smmu; } =20 - if (smmu_domain) - s2_cfg =3D &smmu_domain->s2_cfg; + if (smmu_domain) { + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_S1: + s1_cfg =3D &smmu_domain->s1_cfg; + break; + case ARM_SMMU_DOMAIN_NESTED: + s1_cfg =3D &smmu_domain->s1_cfg; + fallthrough; + case ARM_SMMU_DOMAIN_S2: + s2_cfg =3D &smmu_domain->s2_cfg; + break; + default: + break; + } + translate =3D s1_cfg || s2_cfg; + } =20 if (val & STRTAB_STE_0_V) { switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { case STRTAB_STE_0_CFG_BYPASS: break; + case STRTAB_STE_0_CFG_S1_TRANS: + s1_live =3D true; + break; case STRTAB_STE_0_CFG_S2_TRANS: - ste_live =3D true; + s2_live =3D true; + break; + case STRTAB_STE_0_CFG_NESTED: + s1_live =3D true; + s2_live =3D true; break; case STRTAB_STE_0_CFG_ABORT: - BUG_ON(!disable_bypass); break; default: BUG(); /* STE corruption */ } } =20 + ste_live =3D s1_live || s2_live; + /* Nuke the existing STE_0 value, as we're going to rewrite it */ val =3D STRTAB_STE_0_V; =20 /* Bypass/fault */ - if (!smmu_domain || !(s2_cfg)) { - if (!smmu_domain && disable_bypass) + if (!smmu_domain) + abort =3D disable_bypass; + else + abort =3D smmu_domain->abort; + + if (abort || !translate) { + if (abort) val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -740,7 +769,32 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_= master *master, u32 sid, return; } =20 + if (ste_live) { + /* First invalidate the live STE */ + dst[0] =3D cpu_to_le64(STRTAB_STE_0_CFG_ABORT); + arm_smmu_sync_ste_for_sid(smmu, sid); + } + + if (s1_cfg) { + dst[1] =3D cpu_to_le64( + FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | + FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1)); + + if (smmu->features & ARM_SMMU_FEAT_STALLS && + !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) + dst[1] |=3D cpu_to_le64(STRTAB_STE_1_S1STALLD); + + val |=3D (s1_cfg->s1ctxptr & STRTAB_STE_0_S1CTXPTR_MASK) | + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | + FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | + FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); + } + if (s2_cfg) { + u64 vttbr =3D s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK; u64 strtab =3D FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | @@ -750,12 +804,19 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2R; =20 - BUG_ON(ste_live); + if (s2_live) { + u64 s2ttb =3D le64_to_cpu(dst[3]) & STRTAB_STE_3_S2TTB_MASK; + BUG_ON(s2ttb !=3D vttbr); + } + dst[2] =3D cpu_to_le64(strtab); =20 - dst[3] =3D cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); + dst[3] =3D cpu_to_le64(vttbr); =20 val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); + } else { + dst[2] =3D 0; + dst[3] =3D 0; } =20 if (master->ats_enabled) @@ -1254,8 +1315,18 @@ static int arm_smmu_domain_finalise(struct iommu_dom= ain *domain, { int ret; struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) { + smmu_domain->stage =3D ARM_SMMU_DOMAIN_ABORT; + return 0; + } =20 - /* Restrict the stage to what we can actually support */ + /* + * Default to stage-2 support and initialize it. Stage-1 will be + * initialized during guest config attachment, if nested or stage-1 + * mode is required + */ smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2; =20 ret =3D arm_smmu_domain_finalise_s2(smmu_domain, master); @@ -2454,11 +2525,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu= _device *smmu) break; } =20 + if (reg & IDR0_S1P) + smmu->features |=3D ARM_SMMU_FEAT_TRANS_S1; + if (reg & IDR0_S2P) smmu->features |=3D ARM_SMMU_FEAT_TRANS_S2; =20 - if (!(reg & IDR0_S2P)) { - dev_err(smmu->dev, "no stage-2 translation support!\n"); + if (!(reg & (IDR0_S1P | IDR0_S2P))) { + dev_err(smmu->dev, "no translation support!\n"); return -ENXIO; } =20 diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug= h/arm/smmu-v3.h index ab1f29f6c7..f302c69d02 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -197,6 +197,7 @@ #define STRTAB_STE_0_CFG_BYPASS 4 #define STRTAB_STE_0_CFG_S1_TRANS 5 #define STRTAB_STE_0_CFG_S2_TRANS 6 +#define STRTAB_STE_0_CFG_NESTED 7 =20 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) #define STRTAB_STE_0_S1FMT_LINEAR 0 @@ -391,6 +392,7 @@ enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S2, ARM_SMMU_DOMAIN_NESTED, ARM_SMMU_DOMAIN_BYPASS, + ARM_SMMU_DOMAIN_ABORT, }; =20 /* Xen specific code. */ @@ -549,6 +551,12 @@ struct arm_smmu_strtab_l1_desc { dma_addr_t l2ptr_dma; }; =20 +struct arm_smmu_s1_cfg { + u64 s1ctxptr; + u8 s1fmt; + u8 s1cdmax; +}; + struct arm_smmu_s2_cfg { u16 vmid; u64 vttbr; @@ -669,6 +677,8 @@ struct arm_smmu_domain { atomic_t nr_ats_masters; =20 enum arm_smmu_domain_stage stage; + bool abort; + struct arm_smmu_s1_cfg s1_cfg; struct arm_smmu_s2_cfg s2_cfg; =20 /* Xen domain associated with this SMMU domain */ --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=epam.com); 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b=Qh0A5nFVfJ7wBsvB70EhHp0v+7Qr70IO/eGxPbyQhd6ZluC3cwHKsmQ/VryUUYApxTJP4L5ccrSnLMdZ+a7JQfYXKAENxwZzd6g8/nVqmTVFEvs+JCZfz9kKNm+Qy8D8AENdoBJT03Uja81R4YfRG9z2dJjy5a+ykVQV7UsuBT4cyZTiP0YgoxngB8Pq3+itEiYC7nhllPCwGQ/oHl1f8O7RMUvg+NjYPy+bk8vkrgoAGJKOknnzZ4gMc8fd5kxkHbx6QJjgPnSmiqaTCNTDCLBT9Um4DXJRItlEeKGOpxIpxh/oCpLb6mlXd+mhLdT6HOYuaiIuvtz2ji7q1Keqqg== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Rahul Singh , Bertrand Marquis , Stefano Stabellini , Julien Grall , Michal Orzel , Volodymyr Babchuk , Milan Djokic Subject: [PATCH v5 03/22] xen/arm: smmuv3: Alloc io_domain for each device Thread-Topic: [PATCH v5 03/22] xen/arm: smmuv3: Alloc io_domain for each device Thread-Index: AQHda7j/29wcCkNzHUuJF/zFPrPhCQ== Date: Tue, 3 Nov 2026 17:30:19 +0000 Message-ID: <6340fb19c3067df38d9d5e82fe60ea8deba27700.1793726692.git.milan_djokic@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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charset="utf-8" From: Rahul Singh In current implementation io_domain is allocated once for each xen domain as Stage2 translation is common for all devices in same xen domain. Nested stage supports S1 and S2 configuration at the same time. Stage1 translation will be different for each device as linux kernel will allocate page-table for each device. Alloc io_domain for each device so that each device can have different Stage-1 and Stage-2 configuration structure. The stage-2 configuration is now shared between devices belonging to the same domain. Update io_domain initialization to create a new stage-2 configuration only if a VMID has not already been allocated for the target Xen domain. Similarly, update io_domain teardown to free the VMID only when no other devices are assigned to the target domain. Also optimize the IOTLB flush procedure to invalidate each VMID only once. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/drivers/passthrough/arm/smmu-v3.c | 102 ++++++++++++++++++++++++-- 1 file changed, 94 insertions(+), 8 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index ecfa7e4723..0b26bb27a2 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1229,14 +1229,49 @@ static void arm_smmu_bitmap_free(unsigned long *map= , int idx) clear_bit(idx, map); } =20 +static struct arm_smmu_domain *arm_smmu_get_domain_s2(struct domain *d, + struct arm_smmu_device *smmu) +{ + struct iommu_domain *io_domain; + struct arm_smmu_domain *smmu_domain; + struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; + + if (!smmu) + return NULL; + + /* + * Loop through the &xen_domain->contexts to locate a context + * assigned to this SMMU + */ + list_for_each_entry(io_domain, &xen_domain->contexts, list) { + smmu_domain =3D to_smmu_domain(io_domain); + if (smmu_domain->smmu =3D=3D smmu && + smmu_domain->s2_cfg.vmid !=3D INVALID_VMID) + return smmu_domain; + } + + return NULL; +} + static void arm_smmu_domain_free(struct iommu_domain *domain) { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; + struct arm_smmu_domain *existing; =20 - if (cfg->vmid) - arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid); + if (cfg->vmid) { + /* + * VMIDs are shared across contexts belonging to the same + * Xen domain and SMMU. The current domain has already been + * removed from the domain list, so this lookup only finds + * remaining users of the VMID. + */ + existing =3D arm_smmu_get_domain_s2(smmu_domain->d, smmu); + + if (!existing) + arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid); + } =20 xfree(smmu_domain); } @@ -1316,6 +1351,7 @@ static int arm_smmu_domain_finalise(struct iommu_doma= in *domain, int ret; struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct arm_smmu_domain *existing; =20 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) { smmu_domain->stage =3D ARM_SMMU_DOMAIN_ABORT; @@ -1329,6 +1365,26 @@ static int arm_smmu_domain_finalise(struct iommu_dom= ain *domain, */ smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2; =20 + /* + * Look for an already initialized stage-2 configuration for this + * Xen domain and SMMU. + */ + existing =3D arm_smmu_get_domain_s2(smmu_domain->d, smmu); + + if (existing) { + /* + * Reuse the stage-2 configuration. + */ + smmu_domain->s2_cfg.vmid =3D existing->s2_cfg.vmid; + smmu_domain->s2_cfg.vttbr =3D existing->s2_cfg.vttbr; + smmu_domain->s2_cfg.vtcr =3D existing->s2_cfg.vtcr; + return 0; + } + + /* + * If no existing stage-2 configuration for this + * (Xen domain, SMMU), create it + */ ret =3D arm_smmu_domain_finalise_s2(smmu_domain, master); if (ret < 0) return ret; @@ -2865,20 +2921,40 @@ static uint32_t __ro_after_init platform_features = =3D ARM_SMMU_FEAT_COHERENCY; static int __must_check arm_smmu_iotlb_flush_all(struct domain *d) { struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; - struct iommu_domain *io_domain; + struct iommu_domain *io_domain, *prev; =20 spin_lock(&xen_domain->lock); =20 list_for_each_entry(io_domain, &xen_domain->contexts, list) { + struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(io_domain); + /* * Only invalidate the context when SMMU is present. * This is because the context initialization is delayed * until a master has been added. */ - if (unlikely(!ACCESS_ONCE(to_smmu_domain(io_domain)->smmu))) + if (unlikely(!ACCESS_ONCE(smmu_domain->smmu))) continue; =20 - arm_smmu_tlb_inv_context(to_smmu_domain(io_domain)); + /* + * Skip contexts that share the same SMMU and VMID with an + * earlier context. + */ + list_for_each_entry(prev, &xen_domain->contexts, list) { + struct arm_smmu_domain *prev_domain =3D to_smmu_domain(prev); + + if (prev =3D=3D io_domain) + break; + + if (prev_domain->smmu =3D=3D smmu_domain->smmu && + prev_domain->s2_cfg.vmid =3D=3D smmu_domain->s2_cfg.vmid) + break; + } + + if (prev !=3D io_domain) + continue; + + arm_smmu_tlb_inv_context(smmu_domain); } =20 spin_unlock(&xen_domain->lock); @@ -2924,12 +3000,22 @@ static struct iommu_domain *arm_smmu_get_domain(str= uct domain *d, =20 /* * Loop through the &xen_domain->contexts to locate a context - * assigned to this SMMU + * assigned to this device */ list_for_each_entry(io_domain, &xen_domain->contexts, list) { + unsigned long flags; + const struct arm_smmu_master *master; + smmu_domain =3D to_smmu_domain(io_domain); - if (smmu_domain->smmu =3D=3D smmu) - return io_domain; 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charset="utf-8" From: Rahul Singh This patch adds basic framework for vIOMMU. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/arch/arm/dom0less-build.c | 5 ++ xen/arch/arm/domain.c | 31 +++++++++++- xen/arch/arm/domain_build.c | 2 + xen/arch/arm/include/asm/viommu.h | 70 ++++++++++++++++++++++++++++ xen/drivers/passthrough/Kconfig | 5 ++ xen/drivers/passthrough/arm/Makefile | 1 + xen/drivers/passthrough/arm/viommu.c | 49 +++++++++++++++++++ xen/include/public/arch-arm.h | 6 ++- 8 files changed, 167 insertions(+), 2 deletions(-) create mode 100644 xen/arch/arm/include/asm/viommu.h create mode 100644 xen/drivers/passthrough/arm/viommu.c diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 7bbb2eafb6..b55218d920 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include =20 @@ -370,6 +371,10 @@ int __init arch_parse_dom0less_node(struct dt_device_n= ode *node, uint32_t val; =20 d_cfg->arch.gic_version =3D gic_domctl_hw_version(); + /* Set detected vIOMMU domain type only if IOMMU is enabled for the do= main */ + d_cfg->arch.viommu_type =3D d_cfg->flags & XEN_DOMCTL_CDF_iommu ? + viommu_get_type() : + XEN_DOMCTL_CONFIG_VIOMMU_NONE; d_cfg->flags |=3D XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap; =20 if ( domu_dt_sci_parse(node, d_cfg) ) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 34b5a85f9f..950163a927 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -33,6 +33,7 @@ #include #include #include +#include #include =20 #include "vuart.h" @@ -659,6 +660,21 @@ int arch_sanitise_domain_config(const struct xen_domct= l_createdomain *config) return -EINVAL; } =20 + if ( !(config->flags & XEN_DOMCTL_CDF_iommu) && + config->arch.viommu_type !=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE ) + { + dprintk(XENLOG_INFO, + "vIOMMU requested while iommu not enabled for domain\n"); + return -EINVAL; + } + + if ( config->arch.viommu_type !=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE ) + { + dprintk(XENLOG_INFO, + "vIOMMU type requested not supported by the platform or Xe= n\n"); + return -EINVAL; + } + return sci_domain_sanitise_config(config); } =20 @@ -758,6 +774,9 @@ int arch_domain_create(struct domain *d, if ( (rc =3D sci_domain_init(d, config)) !=3D 0 ) goto fail; =20 + if ( (rc =3D domain_viommu_init(d, config->arch.viommu_type)) !=3D 0 ) + goto fail; + return 0; =20 fail: @@ -818,7 +837,8 @@ static void resume_ctx_reset(struct resume_info *ctx) void arch_domain_destroy(struct domain *d) { resume_ctx_reset(&d->arch.resume_ctx); - + if ( viommu_relinquish_resources(d) ) + printk(XENLOG_ERR "%pd: Domain vIOMMU teardown failed\n", d); tee_free_domain_ctx(d); /* IOMMU page table is shared with P2M, always call * iommu_domain_destroy() before p2m_final_teardown(). @@ -1054,6 +1074,7 @@ static int relinquish_memory(struct domain *d, struct= page_list_head *list) */ enum { PROG_pci =3D 1, + PROG_viommu, PROG_sci, PROG_tee, PROG_xen, @@ -1101,6 +1122,14 @@ int domain_relinquish_resources(struct domain *d) if ( ret ) return ret; #endif + /* + * PCI devices may rely on the vIOMMU, so its resources + * should be relinquished only after the PCI devices are released. + */ + PROGRESS(viommu): + ret =3D viommu_relinquish_resources(d); + if (ret ) + return ret; =20 PROGRESS(sci): ret =3D sci_relinquish_resources(d); diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 1ee1f1f6a7..f749f9ae10 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -37,6 +37,7 @@ #include #include #include +#include #include =20 #include @@ -1988,6 +1989,7 @@ void __init create_dom0(void) dom0_cfg.arch.nr_spis =3D vgic_def_nr_spis(); dom0_cfg.arch.tee_type =3D tee_get_type(); dom0_cfg.max_vcpus =3D dom0_max_vcpus(); + dom0_cfg.arch.viommu_type =3D viommu_get_type(); =20 if ( iommu_enabled ) dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu; diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/v= iommu.h new file mode 100644 index 0000000000..95f82d9cf5 --- /dev/null +++ b/xen/arch/arm/include/asm/viommu.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef __ARCH_ARM_VIOMMU_H__ +#define __ARCH_ARM_VIOMMU_H__ + +#include +#include +#include + +struct viommu_ops { + /* + * Called during domain construction if toolstack requests to enable + * vIOMMU support. + */ + int (*domain_init)(struct domain *d); + + /* + * Called during domain destruction to free resources used by vIOMMU. + */ + int (*relinquish_resources)(struct domain *d); +}; + +struct viommu_desc { + /* vIOMMU domains init/free operations described above. */ + const struct viommu_ops *ops; + + /* + * ID of vIOMMU. Corresponds to xen_arch_domainconfig.viommu_type. + * Should be one of XEN_DOMCTL_CONFIG_VIOMMU_xxx + */ + uint8_t viommu_type; +}; + +#ifdef CONFIG_ARM_VIRTUAL_IOMMU + +int domain_viommu_init(struct domain *d, uint8_t viommu_type); +int viommu_relinquish_resources(struct domain *d); +uint8_t viommu_get_type(void); + +#else + +static inline uint8_t viommu_get_type(void) +{ + return XEN_DOMCTL_CONFIG_VIOMMU_NONE; +} + +static inline int domain_viommu_init(struct domain *d, uint8_t viommu_type) +{ + if ( likely(viommu_type =3D=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE) ) + return 0; + + return -ENODEV; +} + +static inline int viommu_relinquish_resources(struct domain *d) +{ + return 0; +} + +#endif /* CONFIG_ARM_VIRTUAL_IOMMU */ + +#endif /* __ARCH_ARM_VIOMMU_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/drivers/passthrough/Kconfig b/xen/drivers/passthrough/Kcon= fig index b413c33a4c..a92cfbea98 100644 --- a/xen/drivers/passthrough/Kconfig +++ b/xen/drivers/passthrough/Kconfig @@ -35,6 +35,11 @@ config IPMMU_VMSA (H3 ES3.0, M3-W+, etc) or Gen4 SoCs which IPMMU hardware supports stage= 2 translation table format and is able to use CPU's P2M table as is. =20 +config ARM_VIRTUAL_IOMMU + bool "Virtual IOMMU Support (UNSUPPORTED)" if UNSUPPORTED + help + Support virtual IOMMU infrastructure to implement vIOMMU. + endif =20 config AMD_IOMMU diff --git a/xen/drivers/passthrough/arm/Makefile b/xen/drivers/passthrough= /arm/Makefile index c5fb3b58a5..c3783188e3 100644 --- a/xen/drivers/passthrough/arm/Makefile +++ b/xen/drivers/passthrough/arm/Makefile @@ -2,3 +2,4 @@ obj-y +=3D iommu.o iommu_helpers.o iommu_fwspec.o obj-$(CONFIG_ARM_SMMU) +=3D smmu.o obj-$(CONFIG_IPMMU_VMSA) +=3D ipmmu-vmsa.o obj-$(CONFIG_ARM_SMMU_V3) +=3D smmu-v3.o +obj-$(CONFIG_ARM_VIRTUAL_IOMMU) +=3D viommu.o diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough= /arm/viommu.c new file mode 100644 index 0000000000..0c0efd668e --- /dev/null +++ b/xen/drivers/passthrough/arm/viommu.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ + +#include +#include +#include + +#include + +/* Struct to hold the vIOMMU ops and vIOMMU type */ +static const struct viommu_desc __ro_after_init *cur_viommu; + +int domain_viommu_init(struct domain *d, uint8_t viommu_type) +{ + if ( viommu_type =3D=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE ) + return 0; + + if ( !cur_viommu ) + return -ENODEV; + + if ( cur_viommu->viommu_type !=3D viommu_type ) + return -EINVAL; + + return cur_viommu->ops->domain_init(d); +} + +int viommu_relinquish_resources(struct domain *d) +{ + if ( !cur_viommu ) + return 0; + + return cur_viommu->ops->relinquish_resources(d); +} + +uint8_t viommu_get_type(void) +{ + if ( !cur_viommu ) + return XEN_DOMCTL_CONFIG_VIOMMU_NONE; + + return cur_viommu->viommu_type; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 5d15f572c7..a7d456be08 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -334,6 +334,8 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); #define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA 1 #define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA 2 =20 +#define XEN_DOMCTL_CONFIG_VIOMMU_NONE 0 + struct xen_arch_domainconfig { /* IN */ uint8_t gic_version; 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charset="utf-8" Content-ID: <130415816C7C2947B186D047DFEDCB59@eurprd03.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB9587.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b0e6f773-653d-4210-3dbf-08df39d023d2 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Nov 2026 17:30:22.6833 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /N9FlM9nC2JDASeCorVh9tx5kgpfoVUqlFENOahNw1kMSZxdefOIWegZG+R3lOKPsGfzo4/GbvdIOK/tcCptWA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR03MB10511 X-purgate-ID: tlsNG-c1860d/1793727024-CC37587B-7BF5D478/0/0 X-purgate-type: clean X-purgate-size: 20466 X-ZohoMail-DKIM: pass (identity @epam.com) X-ZM-MESSAGEID: 1793727048971158500 From: Rahul Singh domain_viommu_init() will be called during domain creation and will add the dummy trap handler for virtual IOMMUs for guests. A host IOMMU list will be created when host IOMMU devices are probed and this list will be used to create the IOMMU device tree node for dom0. For dom0, 1-1 mapping will be established between vIOMMU in dom0 and=C2=A0physical IOMMU. For domUs, the 1-N mapping will be established between domU and physical IOMMUs. A new area has been reserved in the arm guest physical map at which the emulated vIOMMU node is created in the device tree. Also set the vIOMMU type to vSMMUv3 to enable vIOMMU framework to call vSMMUv3 domain creation/destroy functions. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/arch/arm/domain.c | 6 +- xen/arch/arm/include/asm/domain.h | 5 ++ xen/arch/arm/include/asm/viommu.h | 36 ++++++++ xen/drivers/passthrough/Kconfig | 8 ++ xen/drivers/passthrough/arm/Makefile | 1 + xen/drivers/passthrough/arm/smmu-v3.c | 7 ++ xen/drivers/passthrough/arm/viommu.c | 84 ++++++++++++++++- xen/drivers/passthrough/arm/vsmmu-v3.c | 119 +++++++++++++++++++++++++ xen/drivers/passthrough/arm/vsmmu-v3.h | 20 +++++ xen/include/public/arch-arm.h | 5 ++ 10 files changed, 289 insertions(+), 2 deletions(-) create mode 100644 xen/drivers/passthrough/arm/vsmmu-v3.c create mode 100644 xen/drivers/passthrough/arm/vsmmu-v3.h diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 950163a927..94dfd2f291 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -668,7 +668,8 @@ int arch_sanitise_domain_config(const struct xen_domctl= _createdomain *config) return -EINVAL; } =20 - if ( config->arch.viommu_type !=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE ) + if ( config->arch.viommu_type !=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE && + config->arch.viommu_type !=3D viommu_get_type() ) { dprintk(XENLOG_INFO, "vIOMMU type requested not supported by the platform or Xe= n\n"); @@ -724,6 +725,9 @@ int arch_domain_create(struct domain *d, =20 count +=3D domain_vpci_get_num_mmio_handlers(d); =20 + if ( config->arch.viommu_type !=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE ) + count +=3D domain_viommu_get_num_mmio_handlers(d); + if ( (rc =3D domain_io_init(d, count + MAX_IO_HANDLER)) !=3D 0 ) goto fail; =20 diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index c3d2c4981f..70af0bf8b7 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -102,6 +102,11 @@ struct arch_domain #ifdef CONFIG_MPU uint8_t v8r_el1_msa; #endif + +#ifdef CONFIG_ARM_VIRTUAL_IOMMU + struct list_head viommu_list; /* List of virtual IOMMUs */ +#endif + } __cacheline_aligned; =20 struct arch_vcpu diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/v= iommu.h index 95f82d9cf5..287595068b 100644 --- a/xen/arch/arm/include/asm/viommu.h +++ b/xen/arch/arm/include/asm/viommu.h @@ -3,9 +3,23 @@ #define __ARCH_ARM_VIOMMU_H__ =20 #include +#include #include #include =20 +/* data structure for each hardware IOMMU */ +struct host_iommu { + struct list_head entry; + /* IOMMU DT node used to establish virtual to physical IOMMU/SID mappi= ng */ + const struct dt_device_node *dt_node; + /* Used for dom0 vIOMMU instantiation (1-1 MMIO regions mappings) */ + paddr_t addr; + /* Used for dom0 vIOMMU instantiation (1-1 MMIO regions mappings) */ + paddr_t size; + /* Used for dom0 EVTQ and GERROR interrupts (1-1 IRQ mapping) */ + uint32_t irq; +}; + struct viommu_ops { /* * Called during domain construction if toolstack requests to enable @@ -32,9 +46,15 @@ struct viommu_desc { =20 #ifdef CONFIG_ARM_VIRTUAL_IOMMU =20 +extern struct list_head host_iommu_list; + int domain_viommu_init(struct domain *d, uint8_t viommu_type); int viommu_relinquish_resources(struct domain *d); uint8_t viommu_get_type(void); +void add_to_host_iommu_list(paddr_t addr, paddr_t size, + const struct dt_device_node *node); +void set_cur_viommu(const struct viommu_desc *desc); +unsigned int domain_viommu_get_num_mmio_handlers(struct domain *d); =20 #else =20 @@ -56,6 +76,22 @@ static inline int viommu_relinquish_resources(struct dom= ain *d) return 0; } =20 +static inline void __init add_to_host_iommu_list(paddr_t addr, paddr_t siz= e, + const struct dt_device_node *nod= e) +{ + return; +} + +static inline unsigned int domain_viommu_get_num_mmio_handlers(struct doma= in *d) +{ + return 0; +} + +static inline void __init set_cur_viommu(const struct viommu_desc *desc) +{ + return; +} + #endif /* CONFIG_ARM_VIRTUAL_IOMMU */ =20 #endif /* __ARCH_ARM_VIOMMU_H__ */ diff --git a/xen/drivers/passthrough/Kconfig b/xen/drivers/passthrough/Kcon= fig index a92cfbea98..40d072822f 100644 --- a/xen/drivers/passthrough/Kconfig +++ b/xen/drivers/passthrough/Kconfig @@ -40,6 +40,14 @@ config ARM_VIRTUAL_IOMMU help Support virtual IOMMU infrastructure to implement vIOMMU. =20 +config VIRTUAL_ARM_SMMU_V3 + bool "ARM Ltd. Virtual SMMUv3 Support (UNSUPPORTED)" + depends on ARM_SMMU_V3 && ARM_VIRTUAL_IOMMU + help + Support for implementations of the virtual ARM System MMU architecture + version 3. Virtual SMMUv3 is unsupported feature and should not be used + in production. + endif =20 config AMD_IOMMU diff --git a/xen/drivers/passthrough/arm/Makefile b/xen/drivers/passthrough= /arm/Makefile index c3783188e3..c8f0a5f802 100644 --- a/xen/drivers/passthrough/arm/Makefile +++ b/xen/drivers/passthrough/arm/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_ARM_SMMU) +=3D smmu.o obj-$(CONFIG_IPMMU_VMSA) +=3D ipmmu-vmsa.o obj-$(CONFIG_ARM_SMMU_V3) +=3D smmu-v3.o obj-$(CONFIG_ARM_VIRTUAL_IOMMU) +=3D viommu.o +obj-$(CONFIG_VIRTUAL_ARM_SMMU_V3) +=3D vsmmu-v3.o diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index 0b26bb27a2..b85ad730db 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -93,6 +93,7 @@ #include =20 #include "smmu-v3.h" +#include "vsmmu-v3.h" =20 #define ARM_SMMU_VTCR_SH_IS 3 #define ARM_SMMU_VTCR_RGN_WBWA 1 @@ -2887,6 +2888,9 @@ static int __init arm_smmu_device_probe(struct platfo= rm_device *pdev) list_add(&smmu->devices, &arm_smmu_devices); spin_unlock(&arm_smmu_devices_lock); =20 + /* Add to host IOMMU list to initialize vIOMMU for dom0 */ + add_to_host_iommu_list(ioaddr, iosize, dev_to_dt(pdev)); + return 0; =20 =20 @@ -3240,6 +3244,9 @@ static __init int arm_smmu_dt_init(struct dt_device_n= ode *dev, =20 platform_features &=3D smmu->features; =20 + /* Set vIOMMU type to SMMUv3 */ + vsmmuv3_set_type(); + return 0; } =20 diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough= /arm/viommu.c index 0c0efd668e..2b16f11017 100644 --- a/xen/drivers/passthrough/arm/viommu.c +++ b/xen/drivers/passthrough/arm/viommu.c @@ -2,12 +2,55 @@ =20 #include #include +#include #include +#include +#include =20 #include =20 +/* List of all host IOMMUs */ +LIST_HEAD(host_iommu_list); + /* Struct to hold the vIOMMU ops and vIOMMU type */ static const struct viommu_desc __ro_after_init *cur_viommu; +static bool host_iommu_list_incomplete; + +/* Common function for adding to host_iommu_list */ +void __init add_to_host_iommu_list(paddr_t addr, paddr_t size, + const struct dt_device_node *node) +{ + struct host_iommu *iommu_data; + int irq; + + iommu_data =3D xzalloc(struct host_iommu); + if ( !iommu_data ) + { + host_iommu_list_incomplete =3D true; + printk(XENLOG_WARNING + "vIOMMU: Cannot allocate memory for host IOMMU data\n"); + return; + } + + iommu_data->addr =3D addr; + iommu_data->size =3D size; + iommu_data->dt_node =3D node; + irq =3D platform_get_irq(node, 0); + if ( irq < 0 ) + { + host_iommu_list_incomplete =3D true; + printk(XENLOG_WARNING + "vIOMMU: disabling support because IOMMU @0x%"PRIx64 + " has no usable IRQ (%d)\n", addr, irq); + xfree(iommu_data); + return; + } + iommu_data->irq =3D irq; + + printk("vIOMMU: Found IOMMU @0x%"PRIx64"\n", addr); + + list_add_tail(&iommu_data->entry, &host_iommu_list); +} =20 int domain_viommu_init(struct domain *d, uint8_t viommu_type) { @@ -33,12 +76,51 @@ int viommu_relinquish_resources(struct domain *d) =20 uint8_t viommu_get_type(void) { - if ( !cur_viommu ) + if ( !cur_viommu || host_iommu_list_incomplete || + list_empty(&host_iommu_list) ) return XEN_DOMCTL_CONFIG_VIOMMU_NONE; =20 return cur_viommu->viommu_type; } =20 +void __init set_cur_viommu(const struct viommu_desc *desc) +{ + if ( cur_viommu && (cur_viommu !=3D desc) ) + { + printk("WARNING: Cannot set vIOMMU, already set to a different val= ue\n"); + return; + } + + cur_viommu =3D desc; +} + +unsigned int domain_viommu_get_num_mmio_handlers(struct domain *d) +{ + if ( domain_use_host_layout(d) ) + { + struct host_iommu *hw_iommu; + int count =3D 0; + + /* + * For hardware domain, vIOMMU per pIOMMU is exposed. Number of + * regions required for the configuration space is equal to number = of + * host IOMMUs. + */ + list_for_each_entry(hw_iommu, &host_iommu_list, entry) + { + count++; + } + + return count; + } + + /* + * For unpriviliged domains, single vIOMMU is exposed and requires one + * region to cover the configuration space. + */ + return 1; +} + /* * Local variables: * mode: C diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c new file mode 100644 index 0000000000..7540c6fc54 --- /dev/null +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ + +#include +#include +#include +#include +#include + +struct virt_smmu { + struct domain *d; + struct list_head viommu_list; +}; + +static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, + register_t r, void *priv) +{ + BUG_ON("unimplemented"); + return IO_HANDLED; +} + +static int vsmmuv3_mmio_read(struct vcpu *v, mmio_info_t *info, + register_t *r, void *priv) +{ + BUG_ON("unimplemented"); + return IO_HANDLED; +} + +static const struct mmio_handler_ops vsmmuv3_mmio_handler =3D { + .read =3D vsmmuv3_mmio_read, + .write =3D vsmmuv3_mmio_write, +}; + +static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t siz= e) +{ + struct virt_smmu *smmu; + + smmu =3D xzalloc(struct virt_smmu); + if ( !smmu ) + return -ENOMEM; + + smmu->d =3D d; + + register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu); + + /* Register the vIOMMU to be able to clean it up later. */ + list_add_tail(&smmu->viommu_list, &d->arch.viommu_list); + + return 0; +} + +static int domain_vsmmuv3_init(struct domain *d) +{ + int ret; + + INIT_LIST_HEAD(&d->arch.viommu_list); + + if ( domain_use_host_layout(d) ) + { + struct host_iommu *hw_iommu; + + list_for_each_entry(hw_iommu, &host_iommu_list, entry) + { + ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size); + if ( ret ) + return ret; + } + } + else + { + ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_S= IZE); + if ( ret ) + return ret; + } + + return 0; +} + +static int vsmmuv3_relinquish_resources(struct domain *d) +{ + struct virt_smmu *pos, *temp; + + /* Cope with uninitialized vIOMMU */ + if ( list_head_is_null(&d->arch.viommu_list) ) + return 0; + + list_for_each_entry_safe(pos, temp, &d->arch.viommu_list, viommu_list ) + { + list_del(&pos->viommu_list); + xfree(pos); + } + + return 0; +} + +static const struct viommu_ops vsmmuv3_ops =3D { + .domain_init =3D domain_vsmmuv3_init, + .relinquish_resources =3D vsmmuv3_relinquish_resources, +}; + +static const struct viommu_desc vsmmuv3_desc =3D { + .ops =3D &vsmmuv3_ops, + .viommu_type =3D XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3, +}; + +void __init vsmmuv3_set_type(void) +{ + const struct viommu_desc *desc =3D &vsmmuv3_desc; + + set_cur_viommu(desc); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.h b/xen/drivers/passthrou= gh/arm/vsmmu-v3.h new file mode 100644 index 0000000000..9f4c86abd5 --- /dev/null +++ b/xen/drivers/passthrough/arm/vsmmu-v3.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef __ARCH_ARM_VSMMU_V3_H__ +#define __ARCH_ARM_VSMMU_V3_H__ + +#include + +#ifdef CONFIG_VIRTUAL_ARM_SMMU_V3 + +void vsmmuv3_set_type(void); + +#else + +static inline void __init vsmmuv3_set_type(void) +{ + return; +} + +#endif /* CONFIG_VIRTUAL_ARM_SMMU_V3 */ + +#endif /* __ARCH_ARM_VSMMU_V3_H__ */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index a7d456be08..7c76f2afd4 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -335,6 +335,7 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); #define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA 2 =20 #define XEN_DOMCTL_CONFIG_VIOMMU_NONE 0 +#define XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3 1 =20 struct xen_arch_domainconfig { /* IN */ @@ -449,6 +450,10 @@ typedef uint64_t xen_callback_t; #define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127= */ #define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000) =20 +/* vsmmuv3 MMIO mappings */ +#define GUEST_VSMMUV3_BASE xen_mk_ullong(0x04040000) +#define GUEST_VSMMUV3_SIZE xen_mk_ullong(0x00020000) + /* * 256 MB is reserved for VPCI configuration space based on calculation * 256 buses x 32 devices x 8 functions x 4 KB =3D 256 MB --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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b=S9BnW7CEoxpxsQTdRicJBpWGmCshVNUx1G1s5/cpjGLV88FvvoMuRFj4uIWvJAJk4E+Qn4oA/IcMxcbkYvWDoDoq3tOT515jxQyepEnmMWBCUMEAt9JxwW+Eeo8bmMsiqvPVVF3XAPNSKSOExSGr7HCWIi0xRFMRMYAeSUCVGsS5yPnFeCr3Kv3Xjhv6NVNh4sU7K+X8fRa+r47E+ZBtA1nLEJnIbJEDACUxNG7pDHceZxVXABqNhh7u2XqYoEcaYUipgPxmQePg26sFMmlAaU7L7mG55YY4I7otjXycIB2ZmYY8rMgdvKsjpiaUMVMbDemrnnmQCHtrC2KBemfJ/A== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Rahul Singh , Anthony PERARD , Nick Rosbrook , George Dunlap , Juergen Gross , Milan Djokic Subject: [PATCH v5 06/22] tools: Add XEN_DOMCTL_CONFIG_VIOMMU_* and viommu config param Thread-Topic: [PATCH v5 06/22] tools: Add XEN_DOMCTL_CONFIG_VIOMMU_* and viommu config param Thread-Index: AQHda7kC/hJHclJuGkWXi0K+IS/7rA== Date: Tue, 3 Nov 2026 17:30:24 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="utf-8" From: Rahul Singh Add new viommu_type field and field values XEN_DOMCTL_CONFIG_VIOMMU_NONE XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3 in xen_arch_domainconfig to enable/disable vIOMMU support for domains. Also add viommu=3D"N" parameter to xl domain configuration to enable the vIOMMU for the domains. Currently, only the "smmuv3" type is supported for ARM. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic Acked-by: Nick Rosbrook --- docs/man/xl.cfg.5.pod.in | 22 ++++++++++++++++++++++ tools/golang/xenlight/helpers.gen.go | 2 ++ tools/golang/xenlight/types.gen.go | 7 +++++++ tools/include/libxl.h | 5 +++++ tools/libs/light/libxl_arm.c | 13 +++++++++++++ tools/libs/light/libxl_types.idl | 6 ++++++ tools/xl/xl_parse.c | 9 +++++++++ 7 files changed, 64 insertions(+) diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index b19c25c8d1..3920911033 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -3190,6 +3190,28 @@ option. =20 =3Dback =20 +=3Dover 4 + +=3Ditem B + +Enable an emulated IOMMU for the guest, allowing the guest to configure +IOMMU stage-1 translation for guest-assigned devices protected by the +IOMMU. + +To enable the emulated IOMMU, specify the following option in the VM +configuration file: + +viommu =3D "smmuv3" + +Currently, only the "smmuv3" type is supported on ARM. + +For this option to take effect, the passthrough option must also be +enabled. E.g. if passthrough is explicitly disabled, or implicitly when no +devices passed through to the guest while the vIOMMU is enabled, the +domain configuration is invalid and will be refused by Xen. + +=3Dback + =3Dhead3 x86 =20 =3Dover 4 diff --git a/tools/golang/xenlight/helpers.gen.go b/tools/golang/xenlight/h= elpers.gen.go index 6ab23a708f..254e040802 100644 --- a/tools/golang/xenlight/helpers.gen.go +++ b/tools/golang/xenlight/helpers.gen.go @@ -1273,6 +1273,7 @@ x.ArchArm.NrSpis =3D uint32(xc.arch_arm.nr_spis) if err :=3D x.ArchArm.ArmSci.fromC(&xc.arch_arm.arm_sci);err !=3D nil { return fmt.Errorf("converting field ArchArm.ArmSci: %v", err) } +x.ArchArm.ViommuType =3D ViommuType(xc.arch_arm.viommu_type) if err :=3D x.ArchX86.MsrRelaxed.fromC(&xc.arch_x86.msr_relaxed);err !=3D = nil { return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err) } @@ -1815,6 +1816,7 @@ xc.arch_arm.nr_spis =3D C.uint32_t(x.ArchArm.NrSpis) if err :=3D x.ArchArm.ArmSci.toC(&xc.arch_arm.arm_sci); err !=3D nil { return fmt.Errorf("converting field ArchArm.ArmSci: %v", err) } +xc.arch_arm.viommu_type =3D C.libxl_viommu_type(x.ArchArm.ViommuType) if err :=3D x.ArchX86.MsrRelaxed.toC(&xc.arch_x86.msr_relaxed); err !=3D n= il { return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err) } diff --git a/tools/golang/xenlight/types.gen.go b/tools/golang/xenlight/typ= es.gen.go index 39bf9962d1..112b2825da 100644 --- a/tools/golang/xenlight/types.gen.go +++ b/tools/golang/xenlight/types.gen.go @@ -531,6 +531,12 @@ type ArmSci struct { Type ArmSciType } =20 +type ViommuType int +const( +ViommuTypeNone ViommuType =3D 0 +ViommuTypeSmmuv3 ViommuType =3D 1 +) + type RdmReserve struct { Strategy RdmReserveStrategy Policy RdmReservePolicy @@ -620,6 +626,7 @@ Vuart VuartType SveVl SveType NrSpis uint32 ArmSci ArmSci +ViommuType ViommuType } ArchX86 struct { MsrRelaxed Defbool diff --git a/tools/include/libxl.h b/tools/include/libxl.h index d294fb36bd..4ffbaba179 100644 --- a/tools/include/libxl.h +++ b/tools/include/libxl.h @@ -326,6 +326,11 @@ */ #define LIBXL_HAVE_BUILDINFO_ARCH_ARM_SCI 1 =20 +/* + * libxl_domain_build_info has the arch_arm.viommu_type field. + */ +#define LIBXL_HAVE_BUILDINFO_ARCH_ARM_VIOMMU 1 + /* * LIBXL_HAVE_SOFT_RESET indicates that libxl supports performing * 'soft reset' for domains and there is 'soft_reset' shutdown reason diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c index 47b662ea5c..7f1adfd79b 100644 --- a/tools/libs/light/libxl_arm.c +++ b/tools/libs/light/libxl_arm.c @@ -244,6 +244,19 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, } LOG(DEBUG, " - SCI type=3D%u", config->arch.arm_sci_type); =20 + switch (d_config->b_info.arch_arm.viommu_type) { + case LIBXL_VIOMMU_TYPE_NONE: + config->arch.viommu_type =3D XEN_DOMCTL_CONFIG_VIOMMU_NONE; + break; + case LIBXL_VIOMMU_TYPE_SMMUV3: + config->arch.viommu_type =3D XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3; + break; + default: + LOG(ERROR, "Unknown vIOMMU type %d", + d_config->b_info.arch_arm.viommu_type); + return ERROR_FAIL; + } + return 0; } =20 diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_type= s.idl index ce697303b6..a585d24964 100644 --- a/tools/libs/light/libxl_types.idl +++ b/tools/libs/light/libxl_types.idl @@ -562,6 +562,11 @@ libxl_arm_sci =3D Struct("arm_sci", [ ("type", libxl_arm_sci_type), ]) =20 +libxl_viommu_type =3D Enumeration("viommu_type", [ + (0, "none"), + (1, "smmuv3") + ], init_val =3D "LIBXL_VIOMMU_TYPE_NONE") + libxl_rdm_reserve =3D Struct("rdm_reserve", [ ("strategy", libxl_rdm_reserve_strategy), ("policy", libxl_rdm_reserve_policy), @@ -746,6 +751,7 @@ libxl_domain_build_info =3D Struct("domain_build_info",[ ("sve_vl", libxl_sve_type), ("nr_spis", uint32, {'init_val': 'LIBXL_NR_= SPIS_DEFAULT'}), ("arm_sci", libxl_arm_sci), + ("viommu_type", libxl_viommu_type), ])), ("arch_x86", Struct(None, [("msr_relaxed", libxl_defbool), ])), diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c index 0ccece3e8a..4e5bc84ca3 100644 --- a/tools/xl/xl_parse.c +++ b/tools/xl/xl_parse.c @@ -3080,6 +3080,15 @@ skip_usbdev: } } =20 + if (!xlu_cfg_get_string (config, "viommu", &buf, 1)) { + e =3D libxl_viommu_type_from_string(buf, &b_info->arch_arm.viommu_= type); + if (e) { + fprintf(stderr, + "Unknown vIOMMU type \"%s\" specified\n", buf); + exit(-ERROR_FAIL); + } + } + parse_vkb_list(config, d_config); =20 d_config->virtios =3D NULL; --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=epam.com); dmarc=pass(p=quarantine dis=none) header.from=epam.com ARC-Seal: i=2; a=rsa-sha256; t=1793727054; cv=pass; d=zohomail.com; s=zohoarc; b=BLO+3HQGt6gQ5DUyaBv+pik/D7+uDR5qanjZwWFUZOQGOuyplLxTreHLrmLP6K4nCXZYcnFZOogY5eHIFAATt3LY+IVfeDxYa/H2ME1chbj54I0tF4S/ACNELP3itCHfvn42+6eCzDQjbnVV5/vUvDF0aNYp8cb9E3CGqs6x3hw= ARC-Message-Signature: i=2; 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charset="utf-8" Backport Linux commits 4bbd63eb685b and fd86b5944215, adapted to the Xen SMMUv3 implementation, applying errata workarounds to prevent nesting on MMU-600 and MMU-700 products. Detect IOMMU hardware features and store them in the IOMMU host list for each probed SMMUv3 device, allowing the emulated IOMMU to advertise features supported by the physical IOMMU. Linux commits: 4bbd63eb685b ("iommu/arm-smmu-v3: Work around MMU-600 erratum 1076982") fd86b5944215 ("iommu/arm-smmu-v3: Add explicit feature for nesting") Link: https://lore.kernel.org/all/08adbe3d01024d8382a478325f73b56851f76e49.= 1683731256.git.robin.murphy@arm.com/ Link: https://lore.kernel.org/all/136c3f4a3a84cc14a5a1978ace57dfd3ed67b688.= 1683731256.git.robin.murphy@arm.com/ Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 4b= bd63eb685b Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git fd= 86b5944215 Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/arch/arm/include/asm/viommu.h | 8 ++- xen/drivers/passthrough/arm/smmu-v3.c | 81 +++++++++++++++++++++++-- xen/drivers/passthrough/arm/smmu-v3.h | 32 ++++++++-- xen/drivers/passthrough/arm/viommu.c | 4 +- xen/drivers/passthrough/arm/vsmmu-v3.c | 83 ++++++++++++++++++++++++-- 5 files changed, 191 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/v= iommu.h index 287595068b..844cf34d56 100644 --- a/xen/arch/arm/include/asm/viommu.h +++ b/xen/arch/arm/include/asm/viommu.h @@ -12,6 +12,8 @@ struct host_iommu { struct list_head entry; /* IOMMU DT node used to establish virtual to physical IOMMU/SID mappi= ng */ const struct dt_device_node *dt_node; + /* Physical IOMMU device structure used to detect supported features */ + const void *iommu; /* Used for dom0 vIOMMU instantiation (1-1 MMIO regions mappings) */ paddr_t addr; /* Used for dom0 vIOMMU instantiation (1-1 MMIO regions mappings) */ @@ -52,7 +54,8 @@ int domain_viommu_init(struct domain *d, uint8_t viommu_t= ype); int viommu_relinquish_resources(struct domain *d); uint8_t viommu_get_type(void); void add_to_host_iommu_list(paddr_t addr, paddr_t size, - const struct dt_device_node *node); + const struct dt_device_node *node, + const void *iommu); void set_cur_viommu(const struct viommu_desc *desc); unsigned int domain_viommu_get_num_mmio_handlers(struct domain *d); =20 @@ -77,7 +80,8 @@ static inline int viommu_relinquish_resources(struct doma= in *d) } =20 static inline void __init add_to_host_iommu_list(paddr_t addr, paddr_t siz= e, - const struct dt_device_node *nod= e) + const struct dt_device_node *nod= e, + const void *iommu) { return; } diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index b85ad730db..d2dfb06cae 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -2509,6 +2509,37 @@ err_free_irqs: return ret; } =20 +static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu) +{ + u32 reg; + unsigned int implementer, productid, variant, revision; + + reg =3D readl_relaxed(smmu->base + ARM_SMMU_IIDR); + implementer =3D FIELD_GET(IIDR_IMPLEMENTER, reg); + productid =3D FIELD_GET(IIDR_PRODUCTID, reg); + variant =3D FIELD_GET(IIDR_VARIANT, reg); + revision =3D FIELD_GET(IIDR_REVISION, reg); + + switch (implementer) { + case IIDR_IMPLEMENTER_ARM: + switch (productid) { + case IIDR_PRODUCTID_ARM_MMU_600: + /* Arm erratum 1076982 */ + if (variant =3D=3D 0 && revision <=3D 2) + smmu->features &=3D ~ARM_SMMU_FEAT_SEV; + /* Arm erratum 1209401 */ + if (variant < 2) + smmu->features &=3D ~ARM_SMMU_FEAT_NESTING; + break; + case IIDR_PRODUCTID_ARM_MMU_700: + /* Arm errata 2268618, 2812531 */ + smmu->features &=3D ~ARM_SMMU_FEAT_NESTING; + break; + } + break; + } +} + static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) { u32 reg; @@ -2597,8 +2628,10 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_= device *smmu) switch (FIELD_GET(IDR0_TTF, reg)) { case IDR0_TTF_AARCH32_64: smmu->ias =3D 40; + smmu->features |=3D ARM_SMMU_FEAT_TTF_AARCH32_64; fallthrough; case IDR0_TTF_AARCH64: + smmu->features |=3D ARM_SMMU_FEAT_TTF_AARCH64; break; default: dev_err(smmu->dev, "AArch64 table format not supported!\n"); @@ -2607,6 +2640,8 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_d= evice *smmu) =20 /* ASID/VMID sizes */ smmu->vmid_bits =3D reg & IDR0_VMID16 ? 16 : 8; + if (reg & IDR0_ASID16) + smmu->features |=3D ARM_SMMU_FEAT_ASID_16; =20 /* IDR1 */ reg =3D readl_relaxed(smmu->base + ARM_SMMU_IDR1); @@ -2646,12 +2681,18 @@ static int arm_smmu_device_hw_probe(struct arm_smmu= _device *smmu) smmu->evtq.max_stalls =3D FIELD_GET(IDR5_STALL_MAX, reg); =20 /* Page sizes */ - if (reg & IDR5_GRAN64K) + if (reg & IDR5_GRAN64K) { smmu->pgsize_bitmap |=3D SZ_64K | SZ_512M; - if (reg & IDR5_GRAN16K) + smmu->features |=3D ARM_SMMU_FEAT_GRAN64K; + } + if (reg & IDR5_GRAN16K) { smmu->pgsize_bitmap |=3D SZ_16K | SZ_32M; - if (reg & IDR5_GRAN4K) + smmu->features |=3D ARM_SMMU_FEAT_GRAN16K; + } + if (reg & IDR5_GRAN4K) { smmu->pgsize_bitmap |=3D SZ_4K | SZ_2M | SZ_1G; + smmu->features |=3D ARM_SMMU_FEAT_GRAN4K; + } =20 /* Input address size */ if (FIELD_GET(IDR5_VAX, reg) =3D=3D IDR5_VAX_52_BIT) @@ -2684,15 +2725,46 @@ static int arm_smmu_device_hw_probe(struct arm_smmu= _device *smmu) fallthrough; case IDR5_OAS_48_BIT: smmu->oas =3D 48; + smmu->features |=3D ARM_SMMU_FEAT_OAS_48_BIT; break; } =20 smmu->oas =3D min_t(unsigned long, PADDR_BITS, smmu->oas); smmu->ias =3D max(smmu->ias, smmu->oas); =20 + switch (smmu->oas) { + case 32: + smmu->features |=3D ARM_SMMU_FEAT_OAS_32_BIT; + break; + case 36: + smmu->features |=3D ARM_SMMU_FEAT_OAS_36_BIT; + break; + case 40: + smmu->features |=3D ARM_SMMU_FEAT_OAS_40_BIT; + break; + case 42: + smmu->features |=3D ARM_SMMU_FEAT_OAS_42_BIT; + break; + case 44: + smmu->features |=3D ARM_SMMU_FEAT_OAS_44_BIT; + break; + case 48: + smmu->features |=3D ARM_SMMU_FEAT_OAS_48_BIT; + break; + case 52: + smmu->features |=3D ARM_SMMU_FEAT_OAS_52_BIT; + break; + } + /* Xen: Set maximum Stage-2 input size supported by the SMMU. */ p2m_restrict_ipa_bits(smmu->ias); =20 + if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) && + (smmu->features & ARM_SMMU_FEAT_TRANS_S2)) + smmu->features |=3D ARM_SMMU_FEAT_NESTING; + + arm_smmu_device_iidr_probe(smmu); + dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", smmu->ias, smmu->oas, smmu->features); return 0; @@ -2887,9 +2959,8 @@ static int __init arm_smmu_device_probe(struct platfo= rm_device *pdev) spin_lock(&arm_smmu_devices_lock); list_add(&smmu->devices, &arm_smmu_devices); spin_unlock(&arm_smmu_devices_lock); - /* Add to host IOMMU list to initialize vIOMMU for dom0 */ - add_to_host_iommu_list(ioaddr, iosize, dev_to_dt(pdev)); + add_to_host_iommu_list(ioaddr, iosize, dev_to_dt(pdev), (void *) smmu); =20 return 0; =20 diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug= h/arm/smmu-v3.h index f302c69d02..4a912be740 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -60,6 +60,16 @@ #define IDR5_VAX GENMASK(11, 10) #define IDR5_VAX_52_BIT 1 =20 +#define ARM_SMMU_IIDR 0x18 +#define IIDR_PRODUCTID GENMASK(31, 20) +#define IIDR_VARIANT GENMASK(19, 16) +#define IIDR_REVISION GENMASK(15, 12) +#define IIDR_IMPLEMENTER GENMASK(11, 0) + +#define IIDR_IMPLEMENTER_ARM 0x43b +#define IIDR_PRODUCTID_ARM_MMU_600 0x483 +#define IIDR_PRODUCTID_ARM_MMU_700 0x487 + #define ARM_SMMU_CR0 0x20 #define CR0_ATSCHK (1 << 4) #define CR0_CMDQEN (1 << 3) @@ -603,10 +613,24 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_COHERENCY (1 << 8) #define ARM_SMMU_FEAT_TRANS_S1 (1 << 9) #define ARM_SMMU_FEAT_TRANS_S2 (1 << 10) -#define ARM_SMMU_FEAT_STALLS (1 << 11) -#define ARM_SMMU_FEAT_HYP (1 << 12) -#define ARM_SMMU_FEAT_STALL_FORCE (1 << 13) -#define ARM_SMMU_FEAT_VAX (1 << 14) +#define ARM_SMMU_FEAT_NESTING (1 << 11) +#define ARM_SMMU_FEAT_STALLS (1 << 12) +#define ARM_SMMU_FEAT_HYP (1 << 13) +#define ARM_SMMU_FEAT_STALL_FORCE (1 << 14) +#define ARM_SMMU_FEAT_VAX (1 << 15) +#define ARM_SMMU_FEAT_ASID_16 (1 << 16) +#define ARM_SMMU_FEAT_TTF_AARCH64 (1 << 17) +#define ARM_SMMU_FEAT_TTF_AARCH32_64 (1 << 18) +#define ARM_SMMU_FEAT_GRAN64K (1 << 19) +#define ARM_SMMU_FEAT_GRAN16K (1 << 20) +#define ARM_SMMU_FEAT_GRAN4K (1 << 21) +#define ARM_SMMU_FEAT_OAS_32_BIT (1 << 22) +#define ARM_SMMU_FEAT_OAS_36_BIT (1 << 23) +#define ARM_SMMU_FEAT_OAS_40_BIT (1 << 24) +#define ARM_SMMU_FEAT_OAS_42_BIT (1 << 25) +#define ARM_SMMU_FEAT_OAS_44_BIT (1 << 26) +#define ARM_SMMU_FEAT_OAS_48_BIT (1 << 27) +#define ARM_SMMU_FEAT_OAS_52_BIT (1 << 28) u32 features; =20 #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough= /arm/viommu.c index 2b16f11017..b4b91ab1cb 100644 --- a/xen/drivers/passthrough/arm/viommu.c +++ b/xen/drivers/passthrough/arm/viommu.c @@ -18,7 +18,8 @@ static bool host_iommu_list_incomplete; =20 /* Common function for adding to host_iommu_list */ void __init add_to_host_iommu_list(paddr_t addr, paddr_t size, - const struct dt_device_node *node) + const struct dt_device_node *node, + const void *iommu) { struct host_iommu *iommu_data; int irq; @@ -46,6 +47,7 @@ void __init add_to_host_iommu_list(paddr_t addr, paddr_t = size, return; } iommu_data->irq =3D irq; + iommu_data->iommu =3D iommu; =20 printk("vIOMMU: Found IOMMU @0x%"PRIx64"\n", addr); =20 diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index 7540c6fc54..e3ef68d193 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -6,9 +6,13 @@ #include #include =20 +#include "smmu-v3.h" +#include "vsmmu-v3.h" + struct virt_smmu { struct domain *d; struct list_head viommu_list; + uint32_t features; }; =20 static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, @@ -30,7 +34,8 @@ static const struct mmio_handler_ops vsmmuv3_mmio_handler= =3D { .write =3D vsmmuv3_mmio_write, }; =20 -static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t siz= e) +static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t siz= e, + uint32_t features) { struct virt_smmu *smmu; =20 @@ -39,6 +44,7 @@ static int vsmmuv3_init_single(struct domain *d, paddr_t = addr, paddr_t size) return -ENOMEM; =20 smmu->d =3D d; + smmu->features =3D features; =20 register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu); =20 @@ -51,23 +57,90 @@ static int vsmmuv3_init_single(struct domain *d, paddr_= t addr, paddr_t size) static int domain_vsmmuv3_init(struct domain *d) { int ret; + struct host_iommu *hw_iommu; + const struct arm_smmu_device *smmu; + + if ( list_head_is_null(&host_iommu_list) ) + return -ENODEV; + + /* + * Check physical IOMMUs for Stage-1 and nesting support. + * vIOMMU exposure is rejected if Stage-1 is not supported or + * if both Stage-1 and Stage-2 are supported but nesting is + * disabled, e.g. due to hardware errata. + */ + list_for_each_entry(hw_iommu, &host_iommu_list, entry) + { + smmu =3D (const struct arm_smmu_device *)hw_iommu->iommu; + + if ( !(smmu->features & ARM_SMMU_FEAT_TRANS_S1) ) + { + printk(XENLOG_G_ERR + "vSMMUv3: Stage-1 translation not supported by HW IOMMU\n"= ); + return -EINVAL; + } + + if ( (smmu->features & ARM_SMMU_FEAT_TRANS_S2) && + !(smmu->features & ARM_SMMU_FEAT_NESTING) ) + { + printk(XENLOG_G_ERR + "vSMMUv3: Nesting not supported by HW IOMMU\n"); + return -EINVAL; + } + } =20 INIT_LIST_HEAD(&d->arch.viommu_list); =20 if ( domain_use_host_layout(d) ) { - struct host_iommu *hw_iommu; - list_for_each_entry(hw_iommu, &host_iommu_list, entry) { - ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size); + smmu =3D (const struct arm_smmu_device *) hw_iommu->iommu; + ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size, + smmu->features); if ( ret ) return ret; } } else { - ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_S= IZE); + /* + * Require: For non-hardware domains, features must be uniform acr= oss + * physical SMMUs to avoid advertising features that are unsupport= ed by + * certain units. + */ + uint32_t features; + hw_iommu =3D list_first_entry(&host_iommu_list, struct host_iommu,= entry); + smmu =3D (const struct arm_smmu_device *) hw_iommu->iommu; + features =3D smmu->features; + list_for_each_entry(hw_iommu, &host_iommu_list, entry) + { + smmu =3D (const struct arm_smmu_device *) hw_iommu->iommu; + + if ( smmu->features !=3D features ) + { + printk(XENLOG_G_ERR + "vSMMUv3: Unsupported HW layout: physical SMMUs mus= t " \ + "have a uniform set of features\n"); + return -EINVAL; + } + } + + /* + * Reject vIOMMU exposure to non-hardware + * domains if the physical SMMU does not support stage-2 + * (stage-1-only mode is supported for direct-mapped domains only) + */ + if ( !(features & ARM_SMMU_FEAT_TRANS_S2) ) + { + printk(XENLOG_G_ERR + "vSMMUv3: Physical SMMU must support stage-2 translatio= n " + "for non-hardware domains.\n"); + return -EINVAL; + } + + ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_S= IZE, + features); if ( ret ) return ret; } --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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b=RC1s0ZIvO1vSqrBROMjOnMvxTNB6pxRpAfWXRmJfObdmt7QYs6bYfvMDNjVp4lvUJiN3z+YY1RHmof0/Xj8Qqw43VWH9MVgExJ0qf2KSdfM4mItXWu7WkSzHUtMRO5+HAV+asG2hpU8LAHHNewRVdXFbp+yLoz3r986xpLTGKoA1YdQVa0WFAMbJyGj5IXPmigMcFi1k5c2iMe7vJPtpWlgUF1tHnR3aFk1yezk6zE/fTXOoFtM5flXZi0e0Yc0Ky3jp6HUB5SmfMUJLp8K/ku6VRMaE/5yBKRdx/g5Q0PXiJTrW/IWlRZ/IdrV/CM4HarADoBxy7QNUH0PynZFXHw== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Milan Djokic Subject: [PATCH v5 08/22] xen/arm: vsmmuv3: Add support for registers emulation Thread-Topic: [PATCH v5 08/22] xen/arm: vsmmuv3: Add support for registers emulation Thread-Index: AQHda7kEfjyU8g9/U0W6seOCh9dclQ== Date: Tue, 3 Nov 2026 17:30:27 +0000 Message-ID: <4f7bd0e5cbe5e46f3ba12a7276ca9a49635d6b95.1793726692.git.milan_djokic@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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charset="utf-8" From: Rahul Singh Add initial support for various emulated registers for virtual SMMUv3 for guests and also add support for virtual cmdq and eventq. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/drivers/passthrough/arm/vsmmu-v3.c | 573 ++++++++++++++++++++++++- 1 file changed, 571 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index e3ef68d193..070fe7af79 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -1,31 +1,589 @@ /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ =20 +/* + * IOMMU stage-1 emulation for ARM SMMUv3. + * + * TODO: Using ARM generic implementer/product/variant to avoid activating + * errata workarounds in the guest driver due to emulation layer. + * This needs to be fully handled in the future. + */ + #include #include #include #include +#include #include +#include =20 #include "smmu-v3.h" #include "vsmmu-v3.h" =20 +/* Register Definition */ +#define ARM_SMMU_IDR2 0x8 +#define ARM_SMMU_IDR3 0xc +#define ARM_SMMU_IDR4 0x10 +#define IDR0_TERM_MODEL (1 << 26) +#define IDR3_RIL (1 << 10) +/* Only CMDQ, EVENTQ and SMMUEN supported */ +#define CR0_RESERVED 0xFFFFFFF2U +/* TODO: Right now only 16-bit SID size is supported */ +#define SMMU_IDR1_SIDSIZE 16 +/* The CMDQ/EVTQ sizes are currently set to the architectural maximum. */ +#define SMMU_CMDQS 19 +#define SMMU_EVTQS 19 +#define DWORDS_BYTES 8 + +/* virtual smmu queue */ +struct arm_vsmmu_queue { + uint64_t q_base; /* base register */ + uint32_t prod; + uint32_t cons; + uint8_t ent_size; + uint8_t max_n_shift; +}; + struct virt_smmu { struct domain *d; struct list_head viommu_list; uint32_t features; + paddr_t addr; + uint32_t cr[3]; + uint32_t cr0ack; + uint32_t gerror; + uint32_t gerrorn; + uint32_t strtab_base_cfg; + uint64_t strtab_base; + uint32_t irq_ctrl; + uint64_t gerror_irq_cfg0; + uint64_t evtq_irq_cfg0; + struct arm_vsmmu_queue evtq, cmdq; + spinlock_t cmd_queue_lock; + spinlock_t evt_queue_lock; + spinlock_t gerror_lock; + spinlock_t cr0_lock; + spinlock_t cr1_lock; + spinlock_t cr2_lock; + spinlock_t strtab_cfg_lock; + spinlock_t irq_cfg_lock; }; =20 +/* Helper functions */ +static inline bool smmu_get_smmu_enabled(struct virt_smmu *smmu) +{ + bool enabled; + + spin_lock(&smmu->cr0_lock); + enabled =3D FIELD_GET(CR0_SMMUEN, smmu->cr[0]); + spin_unlock(&smmu->cr0_lock); + + return enabled; +} + +static inline bool smmu_get_cmdq_enabled(struct virt_smmu *smmu) +{ + bool enabled; + + spin_lock(&smmu->cr0_lock); + enabled =3D FIELD_GET(CR0_CMDQEN, smmu->cr[0]); + spin_unlock(&smmu->cr0_lock); + + return enabled; +} + +static inline bool smmu_get_evtq_enabled(struct virt_smmu *smmu) +{ + bool enabled; + + spin_lock(&smmu->cr0_lock); + enabled =3D FIELD_GET(CR0_EVTQEN, smmu->cr[0]); + spin_unlock(&smmu->cr0_lock); + + return enabled; +} + static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, register_t r, void *priv) { - BUG_ON("unimplemented"); + struct virt_smmu *smmu =3D priv; + uint64_t reg; + uint32_t reg32; + struct hsr_dabt dabt =3D info->dabt; + uint64_t offset =3D info->gpa - smmu->addr; + + if ( offset & 0x10000 ) + { + /* page 1 */ + switch ( info->gpa & 0xffff ) + { + case VREG32(ARM_SMMU_EVTQ_PROD): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + /* Write allowed only when SMMU_CR0.EVTQEN =3D=3D 0 */ + if ( smmu_get_evtq_enabled(smmu) ) + break; + spin_lock(&smmu->evt_queue_lock); + reg32 =3D smmu->evtq.prod; + vreg_reg32_update(®32, r, info); + smmu->evtq.prod =3D reg32; + spin_unlock(&smmu->evt_queue_lock); + break; + case VREG32(ARM_SMMU_EVTQ_CONS): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->evt_queue_lock); + reg32 =3D smmu->evtq.cons; + vreg_reg32_update(®32, r, info); + smmu->evtq.cons =3D reg32; + spin_unlock(&smmu->evt_queue_lock); + break; + default: + printk(XENLOG_G_ERR + "%pd: vSMMUv3: unhandled write r%d offset %"PRIpaddr"\n", + v->domain, info->dabt.reg, (unsigned long)info->gpa & 0xff= ff); + return IO_HANDLED; + } + } + else + { + /* page 0 */ + switch ( info->gpa & 0xffff ) + { + case VREG32(ARM_SMMU_CR0): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cr0_lock); + reg32 =3D smmu->cr[0]; + vreg_reg32_update(®32, r, info); + smmu->cr[0] =3D reg32; + smmu->cr0ack =3D reg32 & ~CR0_RESERVED; + spin_unlock(&smmu->cr0_lock); + break; + + case VREG32(ARM_SMMU_CR1): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cr1_lock); + reg32 =3D smmu->cr[1]; + vreg_reg32_update(®32, r, info); + smmu->cr[1] =3D reg32; + spin_unlock(&smmu->cr1_lock); + break; + + case VREG32(ARM_SMMU_CR2): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cr2_lock); + reg32 =3D smmu->cr[2]; + vreg_reg32_update(®32, r, info); + smmu->cr[2] =3D reg32; + spin_unlock(&smmu->cr2_lock); + break; + + case VREG64(ARM_SMMU_STRTAB_BASE): + /* Must only be written when SMMU_CR0.SMMUEN =3D=3D 0, otherw= ise ignore */ + if ( smmu_get_smmu_enabled(smmu) ) + break; + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->strtab_cfg_lock); + reg =3D smmu->strtab_base; + vreg_reg64_update(®, r, info); + smmu->strtab_base =3D reg; + spin_unlock(&smmu->strtab_cfg_lock); + break; + + case VREG32(ARM_SMMU_STRTAB_BASE_CFG): + /* Must only be written when SMMU_CR0.SMMUEN =3D=3D 0, otherw= ise ignore */ + if ( smmu_get_smmu_enabled(smmu) ) + break; + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->strtab_cfg_lock); + reg32 =3D smmu->strtab_base_cfg; + vreg_reg32_update(®32, r, info); + smmu->strtab_base_cfg =3D reg32; + spin_unlock(&smmu->strtab_cfg_lock); + break; + + case VREG64(ARM_SMMU_CMDQ_BASE): + /* Must only be written when SMMU_CR0.CMDQEN =3D=3D 0, otherw= ise ignore */ + if ( smmu_get_cmdq_enabled(smmu) ) + break; + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->cmd_queue_lock); + reg =3D smmu->cmdq.q_base; + vreg_reg64_update(®, r, info); + smmu->cmdq.q_base =3D reg; + smmu->cmdq.max_n_shift =3D FIELD_GET(Q_BASE_LOG2SIZE, smmu->cm= dq.q_base); + if ( smmu->cmdq.max_n_shift > SMMU_CMDQS ) + smmu->cmdq.max_n_shift =3D SMMU_CMDQS; + spin_unlock(&smmu->cmd_queue_lock); + break; + + case VREG32(ARM_SMMU_CMDQ_PROD): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cmd_queue_lock); + reg32 =3D smmu->cmdq.prod; + vreg_reg32_update(®32, r, info); + smmu->cmdq.prod =3D reg32; + spin_unlock(&smmu->cmd_queue_lock); + break; + + case VREG32(ARM_SMMU_CMDQ_CONS): + /* Must only be written when SMMU_CR0.CMDQEN =3D=3D 0, otherw= ise ignore */ + if ( smmu_get_cmdq_enabled(smmu) ) + break; + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cmd_queue_lock); + reg32 =3D smmu->cmdq.cons; + vreg_reg32_update(®32, r, info); + smmu->cmdq.cons =3D reg32; + spin_unlock(&smmu->cmd_queue_lock); + break; + + case VREG64(ARM_SMMU_EVTQ_BASE): + /* Must only be written when SMMU_CR0.EVTQEN =3D=3D 0, otherw= ise ignore */ + if ( smmu_get_evtq_enabled(smmu) ) + break; + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->evt_queue_lock); + reg =3D smmu->evtq.q_base; + vreg_reg64_update(®, r, info); + smmu->evtq.q_base =3D reg; + smmu->evtq.max_n_shift =3D FIELD_GET(Q_BASE_LOG2SIZE, smmu->ev= tq.q_base); + if ( smmu->evtq.max_n_shift > SMMU_EVTQS ) + smmu->evtq.max_n_shift =3D SMMU_EVTQS; + spin_unlock(&smmu->evt_queue_lock); + break; + + case VREG32(ARM_SMMU_IRQ_CTRL): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->irq_cfg_lock); + reg32 =3D smmu->irq_ctrl; + vreg_reg32_update(®32, r, info); + smmu->irq_ctrl =3D reg32; + spin_unlock(&smmu->irq_cfg_lock); + break; + + case VREG64(ARM_SMMU_GERROR_IRQ_CFG0): + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->irq_cfg_lock); + reg =3D smmu->gerror_irq_cfg0; + vreg_reg64_update(®, r, info); + smmu->gerror_irq_cfg0 =3D reg; + spin_unlock(&smmu->irq_cfg_lock); + break; + + case VREG64(ARM_SMMU_EVTQ_IRQ_CFG0): + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->irq_cfg_lock); + reg =3D smmu->evtq_irq_cfg0; + vreg_reg64_update(®, r, info); + smmu->evtq_irq_cfg0 =3D reg; + spin_unlock(&smmu->irq_cfg_lock); + break; + + case VREG32(ARM_SMMU_GERRORN): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->gerror_lock); + reg32 =3D smmu->gerrorn; + vreg_reg32_update(®32, r, info); + smmu->gerrorn =3D reg32; + spin_unlock(&smmu->gerror_lock); + break; + + default: + printk(XENLOG_G_ERR + "%pd: vSMMUv3: unhandled write r%d offset %"PRIpaddr"\n", + v->domain, info->dabt.reg, (unsigned long)info->gpa & 0xff= ff); + return IO_HANDLED; + } + } + + return IO_HANDLED; + + bad_width: + gprintk(XENLOG_G_ERR, + "%pd: vSMMUv3: bad write width %d r%d offset %"PRIpaddr"\n", + v->domain, dabt.size, dabt.reg, info->gpa & 0xffff); return IO_HANDLED; } =20 static int vsmmuv3_mmio_read(struct vcpu *v, mmio_info_t *info, register_t *r, void *priv) { - BUG_ON("unimplemented"); + struct virt_smmu *smmu =3D priv; + uint64_t reg; + struct hsr_dabt dabt =3D info->dabt; + uint64_t offset =3D info->gpa - smmu->addr; + + if ( offset & 0x10000 ) + { + /* page 1 */ + switch ( info->gpa & 0xffff ) + { + case VREG32(ARM_SMMU_EVTQ_PROD): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->evt_queue_lock); + *r =3D vreg_reg32_extract(smmu->evtq.prod, info); + spin_unlock(&smmu->evt_queue_lock); + break; + + case VREG32(ARM_SMMU_EVTQ_CONS): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->evt_queue_lock); + *r =3D vreg_reg32_extract(smmu->evtq.cons, info); + spin_unlock(&smmu->evt_queue_lock); + break; + + default: + printk(XENLOG_G_ERR + "%pd: vSMMUv3: unhandled read r%d offset %"PRIpaddr"\n= ", + v->domain, info->dabt.reg, (unsigned long)info->gpa & = 0xffff); + return IO_HANDLED; + } + } + else + { + /* page 0 */ + switch ( info->gpa & 0xffff ) + { + case VREG32(ARM_SMMU_IDR0): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + /* + * Emulated SMMU capabilities. + * + * Some architectural capabilities are currently not implement= ed + * by the stage-1 emulation layer or underlying Xen SMMU suppo= rt, + * therefore they are not advertised atm even if supported by = the HW + */ + reg =3D FIELD_PREP(IDR0_S1P, 1) | + /* + * TODO: Coherent access not supported by the emulation at= m. + * Guest must perform explicit cache clean + */ + FIELD_PREP(IDR0_COHACC, 0) | + /* Transaction stall on fault not implemented */ + FIELD_PREP(IDR0_STALL_MODEL, 1) | + /* Terminating a transaction with RAZ/WI behavior not impl= emented */ + FIELD_PREP(IDR0_TERM_MODEL, 1); + + /* HW reflected capabilities */ + reg |=3D FIELD_PREP(IDR0_ST_LVL, + smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? + 1 : 0); + reg |=3D FIELD_PREP(IDR0_TTF, + smmu->features & ARM_SMMU_FEAT_TTF_AARCH32_64 ? + IDR0_TTF_AARCH32_64 : IDR0_TTF_AARCH64); + + reg |=3D FIELD_PREP(IDR0_ASID16, + smmu->features & ARM_SMMU_FEAT_ASID_16 ? 1 : 0= ); + if ( (smmu->features & ARM_SMMU_FEAT_TT_LE) && + (smmu->features & ARM_SMMU_FEAT_TT_BE) ) + reg |=3D FIELD_PREP(IDR0_TTENDIAN, IDR0_TTENDIAN_MIXED); + else if ( smmu->features & ARM_SMMU_FEAT_TT_LE ) + reg |=3D FIELD_PREP(IDR0_TTENDIAN, IDR0_TTENDIAN_LE); + #ifdef __BIG_ENDIAN + else if ( smmu->features & ARM_SMMU_FEAT_TT_BE ) + reg |=3D FIELD_PREP(IDR0_TTENDIAN, IDR0_TTENDIAN_BE); + #endif + *r =3D vreg_reg32_extract(reg, info); + break; + + case VREG32(ARM_SMMU_IDR1): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + reg =3D FIELD_PREP(IDR1_SIDSIZE, SMMU_IDR1_SIDSIZE) | + FIELD_PREP(IDR1_CMDQS, SMMU_CMDQS) | + FIELD_PREP(IDR1_EVTQS, SMMU_EVTQS); + *r =3D vreg_reg32_extract(reg, info); + break; + + case VREG32(ARM_SMMU_IDR2): + goto read_reserved; + + case VREG32(ARM_SMMU_IDR3): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + reg =3D 0; + *r =3D vreg_reg32_extract(reg, info); + break; + + case VREG32(ARM_SMMU_IDR4): + goto read_impl_defined; + + case VREG32(ARM_SMMU_IDR5): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + reg =3D 0; + if (smmu->features & ARM_SMMU_FEAT_GRAN64K) + reg |=3D IDR5_GRAN64K; + if (smmu->features & ARM_SMMU_FEAT_GRAN16K) + reg |=3D IDR5_GRAN16K; + if (smmu->features & ARM_SMMU_FEAT_GRAN4K) + reg |=3D IDR5_GRAN4K; + + if (smmu->features & ARM_SMMU_FEAT_OAS_32_BIT) + reg |=3D IDR5_OAS_32_BIT; + if (smmu->features & ARM_SMMU_FEAT_OAS_36_BIT) + reg |=3D IDR5_OAS_36_BIT; + if (smmu->features & ARM_SMMU_FEAT_OAS_40_BIT) + reg |=3D IDR5_OAS_40_BIT; + if (smmu->features & ARM_SMMU_FEAT_OAS_42_BIT) + reg |=3D IDR5_OAS_42_BIT; + if (smmu->features & ARM_SMMU_FEAT_OAS_44_BIT) + reg |=3D IDR5_OAS_44_BIT; + if (smmu->features & ARM_SMMU_FEAT_OAS_48_BIT) + reg |=3D IDR5_OAS_48_BIT; + if (smmu->features & ARM_SMMU_FEAT_OAS_52_BIT) + reg |=3D IDR5_OAS_52_BIT; + + *r =3D vreg_reg32_extract(reg, info); + break; + + case VREG32(ARM_SMMU_IIDR): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + /* Use generic ARM IIDR value to avoid activating errata worka= rounds */ + reg =3D FIELD_PREP(IIDR_IMPLEMENTER, IIDR_IMPLEMENTER_ARM) | + FIELD_PREP(IIDR_REVISION, 0) | + FIELD_PREP(IIDR_VARIANT, 0) | + FIELD_PREP(IIDR_PRODUCTID, 0); + *r =3D vreg_reg32_extract(reg, info); + break; + + case VREG32(ARM_SMMU_CR0): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cr0_lock); + *r =3D vreg_reg32_extract(smmu->cr[0], info); + spin_unlock(&smmu->cr0_lock); + break; + + case VREG32(ARM_SMMU_CR0ACK): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cr0_lock); + *r =3D vreg_reg32_extract(smmu->cr0ack, info); + spin_unlock(&smmu->cr0_lock); + break; + + case VREG32(ARM_SMMU_CR1): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cr1_lock); + *r =3D vreg_reg32_extract(smmu->cr[1], info); + spin_unlock(&smmu->cr1_lock); + break; + + case VREG32(ARM_SMMU_CR2): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cr2_lock); + *r =3D vreg_reg32_extract(smmu->cr[2], info); + spin_unlock(&smmu->cr2_lock); + break; + + case VREG64(ARM_SMMU_STRTAB_BASE): + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->strtab_cfg_lock); + *r =3D vreg_reg64_extract(smmu->strtab_base, info); + spin_unlock(&smmu->strtab_cfg_lock); + break; + + case VREG32(ARM_SMMU_STRTAB_BASE_CFG): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->strtab_cfg_lock); + *r =3D vreg_reg32_extract(smmu->strtab_base_cfg, info); + spin_unlock(&smmu->strtab_cfg_lock); + break; + + case VREG64(ARM_SMMU_CMDQ_BASE): + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->cmd_queue_lock); + *r =3D vreg_reg64_extract(smmu->cmdq.q_base, info); + spin_unlock(&smmu->cmd_queue_lock); + break; + + case VREG32(ARM_SMMU_CMDQ_PROD): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cmd_queue_lock); + *r =3D vreg_reg32_extract(smmu->cmdq.prod, info); + spin_unlock(&smmu->cmd_queue_lock); + break; + + case VREG32(ARM_SMMU_CMDQ_CONS): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->cmd_queue_lock); + *r =3D vreg_reg32_extract(smmu->cmdq.cons, info); + spin_unlock(&smmu->cmd_queue_lock); + break; + + case VREG64(ARM_SMMU_EVTQ_BASE): + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->evt_queue_lock); + *r =3D vreg_reg64_extract(smmu->evtq.q_base, info); + spin_unlock(&smmu->evt_queue_lock); + break; + + case VREG32(ARM_SMMU_IRQ_CTRL): + case VREG32(ARM_SMMU_IRQ_CTRLACK): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->irq_cfg_lock); + *r =3D vreg_reg32_extract(smmu->irq_ctrl, info); + spin_unlock(&smmu->irq_cfg_lock); + break; + + case VREG64(ARM_SMMU_GERROR_IRQ_CFG0): + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->irq_cfg_lock); + *r =3D vreg_reg64_extract(smmu->gerror_irq_cfg0, info); + spin_unlock(&smmu->irq_cfg_lock); + break; + + case VREG64(ARM_SMMU_EVTQ_IRQ_CFG0): + if ( dabt.size !=3D DABT_DOUBLE_WORD && dabt.size !=3D DABT_WO= RD ) + goto bad_width; + spin_lock(&smmu->irq_cfg_lock); + *r =3D vreg_reg64_extract(smmu->evtq_irq_cfg0, info); + spin_unlock(&smmu->irq_cfg_lock); + break; + + case VREG32(ARM_SMMU_GERROR): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->gerror_lock); + *r =3D vreg_reg32_extract(smmu->gerror, info); + spin_unlock(&smmu->gerror_lock); + break; + + case VREG32(ARM_SMMU_GERRORN): + if ( dabt.size !=3D DABT_WORD ) goto bad_width; + spin_lock(&smmu->gerror_lock); + *r =3D vreg_reg32_extract(smmu->gerrorn, info); + spin_unlock(&smmu->gerror_lock); + break; + + default: + printk(XENLOG_G_ERR + "%pd: vSMMUv3: unhandled read r%d offset %"PRIpaddr"\n", + v->domain, info->dabt.reg, (unsigned long)info->gpa & 0xff= ff); + return IO_HANDLED; + } + } + return IO_HANDLED; + + read_impl_defined: + printk(XENLOG_G_DEBUG + "%pd: vSMMUv3: RAZ on implementation defined register offset %"= PRIpaddr"\n", + v->domain, info->gpa & 0xffff); + *r =3D 0; + return IO_HANDLED; + + read_reserved: + printk(XENLOG_G_DEBUG + "%pd: vSMMUv3: RAZ on reserved register offset %"PRIpaddr"\n", + v->domain, info->gpa & 0xffff); + *r =3D 0; + return IO_HANDLED; + bad_width: + gprintk(XENLOG_G_ERR, + "%pd: vSMMUv3: bad read width %d r%d offset %"PRIpaddr"\n", + v->domain, dabt.size, dabt.reg, info->gpa & 0xffff); return IO_HANDLED; } =20 @@ -45,6 +603,17 @@ static int vsmmuv3_init_single(struct domain *d, paddr_= t addr, paddr_t size, =20 smmu->d =3D d; smmu->features =3D features; + smmu->cmdq.ent_size =3D CMDQ_ENT_DWORDS * DWORDS_BYTES; + smmu->evtq.ent_size =3D EVTQ_ENT_DWORDS * DWORDS_BYTES; + + spin_lock_init(&smmu->cmd_queue_lock); + spin_lock_init(&smmu->evt_queue_lock); + spin_lock_init(&smmu->gerror_lock); + spin_lock_init(&smmu->cr0_lock); + spin_lock_init(&smmu->cr1_lock); + spin_lock_init(&smmu->cr2_lock); + spin_lock_init(&smmu->strtab_cfg_lock); + spin_lock_init(&smmu->irq_cfg_lock); =20 register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu); =20 --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=epam.com); dmarc=pass(p=quarantine dis=none) header.from=epam.com ARC-Seal: i=2; a=rsa-sha256; t=1793727060; cv=pass; d=zohomail.com; s=zohoarc; b=TDldmsSGV/FFwyVa5MqEgTk2FyqXQI9j/IedyjNBoxfARFh6oOsvl7DHTo9yyPjEmH5cQdUuGaDEbAcVwXj57yW6cbHOjdbXsFUd8FQjw+SzNFbB8GKuWMyvtGzCXXUAD88HbyPXiH2v4j/sOHcj8h6OBly8ntqFTUro0xvbOqI= ARC-Message-Signature: i=2; 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charset="utf-8" From: Rahul Singh Add support for virtual cmdqueue handling for guests Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/drivers/passthrough/arm/vsmmu-v3.c | 133 +++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index 070fe7af79..780f36bf2a 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -8,6 +8,7 @@ * This needs to be fully handled in the future. */ =20 +#include #include #include #include @@ -34,6 +35,51 @@ #define SMMU_EVTQS 19 #define DWORDS_BYTES 8 =20 +/*=20 + * SMMUv3 command definitions + * Some commands are fully handled by the emulation layer, while others are + * currently treated as architectural no-ops because the required behavior + * is either implicitly guaranteed by Xen or not yet modeled explicitly. + * + * Emulation handled commands: + * + * - CMD_CFGI_STE + * - CMD_TLBI_NH_ASID + * - CMD_TLBI_NSNH_ALL + * - CMD_TLBI_NH_VA + * + * No-op/Implicitly handled commands: + * + * - CMD_SYNC + * - CMD_PREFETCH_CFG + * - CMD_CFGI_CD + * - CMD_CFGI_CD_ALL + * - CMD_CFGI_ALL + * + * TODO: Remaining architecture-defined commands are not supported (error + * produced), due to lack of support in SMMUv3 driver / emulation layer + * TODO: Range / per-device invalidation not supported atm + * TODO: Long-running command queue handling is not implemented (command + * consumption should be budgeted with asynchronous resumption). + */ +#define CMDQ_OP_PREFETCH_CFG 0x1 +#define CMDQ_OP_CFGI_STE 0x3 +#define CMDQ_OP_CFGI_ALL 0x4 +#define CMDQ_OP_CFGI_CD 0x5 +#define CMDQ_OP_CFGI_CD_ALL 0x6 +#define CMDQ_OP_TLBI_NH_ASID 0x11 +#define CMDQ_OP_TLBI_NH_VA 0x12 +#define CMDQ_OP_TLBI_NSNH_ALL 0x30 +#define CMDQ_OP_CMD_SYNC 0x46 + +/* Queue Handling */ +#define Q_BASE(q) ((q)->q_base & Q_BASE_ADDR_MASK) +#define Q_CONS_ENT(q) (Q_BASE(q) + Q_IDX(q, (q)->cons) * (q)->ent_size) +#define Q_PROD_ENT(q) (Q_BASE(q) + Q_IDX(q, (q)->prod) * (q)->ent_size) + +/* Helper Macros */ +#define smmu_cmd_get_command(x) FIELD_GET(CMDQ_0_OP, x) + /* virtual smmu queue */ struct arm_vsmmu_queue { uint64_t q_base; /* base register */ @@ -100,6 +146,89 @@ static inline bool smmu_get_evtq_enabled(struct virt_s= mmu *smmu) spin_unlock(&smmu->cr0_lock); =20 return enabled; +}; + +/* Queue manipulation functions */ +static bool queue_empty(struct arm_vsmmu_queue *q) +{ + return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) && + Q_WRP(q, q->prod) =3D=3D Q_WRP(q, q->cons); +} + +static void queue_inc_cons(struct arm_vsmmu_queue *q) +{ + uint32_t cons =3D (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; + q->cons =3D Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); +} + +static void dump_smmu_command(uint64_t *command) +{ + gprintk(XENLOG_ERR, "cmd 0x%02llx: %016"PRIx64" %016"PRIx64"\n", + smmu_cmd_get_command(command[0]), command[0], command[1]); +} +static int arm_vsmmu_handle_cmds(struct virt_smmu *smmu) +{ + struct arm_vsmmu_queue *q =3D &smmu->cmdq; + struct domain *d =3D smmu->d; + uint64_t command[CMDQ_ENT_DWORDS]; + paddr_t addr; + int ret =3D 0; + + if ( !smmu_get_cmdq_enabled(smmu) ) + return 0; + + /* + * TODO: A large number of commands could cause this loop to run for + * an extended period while holding the command queue lock, potentially + * monopolizing CPU time. Implement commands rescheduling and asynchro= nous + * execution as outlined in the design. + */ + while ( !queue_empty(q) ) + { + int ret; + + addr =3D Q_CONS_ENT(q); + ret =3D access_guest_memory_by_gpa(d, addr, command, + sizeof(command), false); + if ( ret ) { + queue_inc_cons(q); + return ret; + } + + switch ( smmu_cmd_get_command(command[0]) ) + { + case CMDQ_OP_CFGI_STE: + break; + case CMDQ_OP_PREFETCH_CFG: + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + case CMDQ_OP_CFGI_ALL: + case CMDQ_OP_CMD_SYNC: + break; + case CMDQ_OP_TLBI_NH_ASID: + case CMDQ_OP_TLBI_NSNH_ALL: + case CMDQ_OP_TLBI_NH_VA: + ret =3D iommu_iotlb_flush_all(smmu->d, 1); + if ( !ret ) + break; + fallthrough; + default: + gdprintk(XENLOG_ERR, "vSMMUv3: unhandled command\n"); + dump_smmu_command(command); + break; + } + + if ( ret ) + { + gdprintk(XENLOG_ERR, + "vSMMUv3: command error %d while handling command\n", + ret); + dump_smmu_command(command); + } + queue_inc_cons(q); + } + + return ret; } =20 static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, @@ -222,6 +351,10 @@ static int vsmmuv3_mmio_write(struct vcpu *v, mmio_inf= o_t *info, reg32 =3D smmu->cmdq.prod; vreg_reg32_update(®32, r, info); smmu->cmdq.prod =3D reg32; + + if ( arm_vsmmu_handle_cmds(smmu) ) + gdprintk(XENLOG_ERR, "error handling vSMMUv3 commands\n"); + spin_unlock(&smmu->cmd_queue_lock); break; =20 --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=epam.com); dmarc=pass(p=quarantine dis=none) header.from=epam.com ARC-Seal: i=2; a=rsa-sha256; t=1793727049; cv=pass; d=zohomail.com; s=zohoarc; b=my139YZBQlrKmGj6fdWQinNg1GJjfVvXY6epzSDi2Ip5qBxR+ZZB2GzVKNOSKkfMNRqtJjYuRPzLznz4AtueZH5SnUb0t+S8u8pmUK1WEDh2YD1RTJvyXc4JbF1NG/rgJSdf+/7G+NoPk4ppi2F4BbqQY04DDDLO1yCF/MvKzvc= ARC-Message-Signature: i=2; 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charset="utf-8" From: Rahul Singh CMD_CFGI_STE is used to invalidate/validate the STE. Emulated vSMMUv3 driver in XEN will read the STE from the guest memory space and capture the Stage-1 configuration required to support nested translation. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/drivers/passthrough/arm/vsmmu-v3.c | 173 +++++++++++++++++++++++++ 1 file changed, 173 insertions(+) diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index 780f36bf2a..5e12d5c587 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -79,6 +79,21 @@ =20 /* Helper Macros */ #define smmu_cmd_get_command(x) FIELD_GET(CMDQ_0_OP, x) +#define smmu_cmd_get_sid(x) FIELD_GET(CMDQ_CFGI_0_SID, x) +#define smmu_get_ste_s1cdmax(x) FIELD_GET(STRTAB_STE_0_S1CDMAX, x) +#define smmu_get_ste_s1fmt(x) FIELD_GET(STRTAB_STE_0_S1FMT, x) +#define smmu_get_ste_s1stalld(x) FIELD_GET(STRTAB_STE_1_S1STALLD, x) +#define smmu_get_ste_s1ctxptr(x) FIELD_PREP(STRTAB_STE_0_S1CTXPTR_MASK,= \ + FIELD_GET(STRTAB_STE_0_S1CTXPTR_MASK, = x)) + +/* stage-1 translation configuration */ +struct arm_vsmmu_s1_trans_cfg { + paddr_t s1ctxptr; + uint8_t s1fmt; + uint8_t s1cdmax; + bool bypassed; /* translation is bypassed */ + bool aborted; /* translation is aborted */ +}; =20 /* virtual smmu queue */ struct arm_vsmmu_queue { @@ -166,6 +181,163 @@ static void dump_smmu_command(uint64_t *command) gprintk(XENLOG_ERR, "cmd 0x%02llx: %016"PRIx64" %016"PRIx64"\n", smmu_cmd_get_command(command[0]), command[0], command[1]); } + +static int arm_vsmmu_find_ste(struct virt_smmu *smmu, uint32_t sid, + uint64_t *ste) +{ + paddr_t addr, strtab_base; + struct domain *d =3D smmu->d; + uint32_t log2size; + int strtab_size_shift; + int ret; + + spin_lock(&smmu->strtab_cfg_lock); + log2size =3D MIN(FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, smmu->strtab_base= _cfg), + SMMU_IDR1_SIDSIZE); + spin_unlock(&smmu->strtab_cfg_lock); + + if ( sid >=3D (1U << log2size) ) + return -EINVAL; + + spin_lock(&smmu->strtab_cfg_lock); + if ( FIELD_GET(STRTAB_BASE_CFG_FMT, smmu->strtab_base_cfg) =3D=3D + STRTAB_BASE_CFG_FMT_2LVL ) + { + int idx, max_l2_ste, span; + paddr_t l1ptr, l2ptr; + uint64_t l1std; + uint8_t sid_split =3D FIELD_GET(STRTAB_BASE_CFG_SPLIT, + smmu->strtab_base_cfg); + + /* + * Reserved SPLIT values behave as 6 according to the architecture. + */ + if ( sid_split !=3D 0x6 && sid_split !=3D 0x8 && sid_split !=3D 0x= A ) + { + sid_split =3D 0x6; + } + + strtab_size_shift =3D MAX(5, (int)log2size - sid_split - 1 + 3); + strtab_base =3D smmu->strtab_base & STRTAB_BASE_ADDR_MASK & + ~GENMASK_ULL(strtab_size_shift, 0); + spin_unlock(&smmu->strtab_cfg_lock); + idx =3D (sid >> sid_split) * STRTAB_L1_DESC_DWORDS; + l1ptr =3D (paddr_t)(strtab_base + idx * sizeof(l1std)); + + ret =3D access_guest_memory_by_gpa(d, l1ptr, &l1std, + sizeof(l1std), false); + if ( ret ) + { + gdprintk(XENLOG_ERR, + "Could not read L1PTR at 0X%"PRIx64"\n", l1ptr); + return ret; + } + + span =3D FIELD_GET(STRTAB_L1_DESC_SPAN, l1std); + + /* Validate SPAN against the architecturally defined range and SPL= IT. */ + if ( !span || span > 0xB || span > sid_split + 1 ) + { + /* L2Ptr is invalid; this descriptor matches no valid STEs. */ + return -EINVAL; + } + + max_l2_ste =3D (1U << (span - 1)) - 1; + l2ptr =3D FIELD_PREP(STRTAB_L1_DESC_L2PTR_MASK, + FIELD_GET(STRTAB_L1_DESC_L2PTR_MASK, l1std)); + idx =3D sid & ((1 << sid_split) - 1); + if ( idx > max_l2_ste ) + { + gdprintk(XENLOG_ERR, "idx=3D%d > max_l2_ste=3D%d\n", + idx, max_l2_ste); + return -EINVAL; + } + addr =3D l2ptr + idx * sizeof(*ste) * STRTAB_STE_DWORDS; + } + else + { + strtab_size_shift =3D log2size + 5; + strtab_base =3D smmu->strtab_base & STRTAB_BASE_ADDR_MASK & + ~GENMASK_ULL(strtab_size_shift, 0); + spin_unlock(&smmu->strtab_cfg_lock); + addr =3D strtab_base + sid * sizeof(*ste) * STRTAB_STE_DWORDS; + } + ret =3D access_guest_memory_by_gpa(d, addr, ste, sizeof(*ste), false); + if ( ret ) + { + gdprintk(XENLOG_ERR, + "Cannot fetch pte at address=3D0x%"PRIx64"\n", addr); + return -EINVAL; + } + + return 0; +} + +static int arm_vsmmu_decode_ste(struct virt_smmu *smmu, uint32_t sid, + struct arm_vsmmu_s1_trans_cfg *cfg, + uint64_t *ste) +{ + uint64_t val =3D ste[0]; + + if ( !(val & STRTAB_STE_0_V) ) + { + cfg->aborted =3D true; + return 0; + } + + switch ( FIELD_GET(STRTAB_STE_0_CFG, val) ) + { + case STRTAB_STE_0_CFG_BYPASS: + cfg->bypassed =3D true; + return 0; + case STRTAB_STE_0_CFG_ABORT: + cfg->aborted =3D true; + return 0; + case STRTAB_STE_0_CFG_S1_TRANS: + break; + case STRTAB_STE_0_CFG_S2_TRANS: + gdprintk(XENLOG_ERR, "vSMMUv3 does not support stage 2 yet\n"); + goto bad_ste; + default: + gdprintk(XENLOG_ERR, "Invalid STE config type\n"); + goto bad_ste; + } + + cfg->s1ctxptr =3D smmu_get_ste_s1ctxptr(val); + cfg->s1fmt =3D smmu_get_ste_s1fmt(val); + cfg->s1cdmax =3D smmu_get_ste_s1cdmax(val); + if ( cfg->s1cdmax !=3D 0 ) + { + gdprintk(XENLOG_ERR, + "vSMMUv3 does not support multiple context descriptors\n"= ); + goto bad_ste; + } + + return 0; + + bad_ste: + return -EINVAL; +} + +static int arm_vsmmu_handle_cfgi_ste(struct virt_smmu *smmu, uint64_t *cmd= ptr) +{ + int ret; + /* Only the first 8 bytes of the STE are currently used. */ + uint64_t ste[1]; + struct arm_vsmmu_s1_trans_cfg s1_cfg =3D {0}; + uint32_t sid =3D smmu_cmd_get_sid(cmdptr[0]); + + ret =3D arm_vsmmu_find_ste(smmu, sid, ste); + if ( ret ) + return ret; + + ret =3D arm_vsmmu_decode_ste(smmu, sid, &s1_cfg, ste); + if ( ret ) + return (ret =3D=3D -EAGAIN ) ? 0 : ret; + + return 0; +} + static int arm_vsmmu_handle_cmds(struct virt_smmu *smmu) { struct arm_vsmmu_queue *q =3D &smmu->cmdq; @@ -198,6 +370,7 @@ static int arm_vsmmu_handle_cmds(struct virt_smmu *smmu) switch ( smmu_cmd_get_command(command[0]) ) { case CMDQ_OP_CFGI_STE: + ret =3D arm_vsmmu_handle_cfgi_ste(smmu, command); break; case CMDQ_OP_PREFETCH_CFG: case CMDQ_OP_CFGI_CD: --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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b=VPU53uhS7MnfgbMVVveBR6SAn1cfEPf+Z8VGVaDriIqHy4EIh8hxBzFNCOjwi9WnDZqx5S64BE9ZaGN6H9uLk5KRD+ieJ6HmPkhmgLsjp5vfjbNt2ScDxs99qKWSepUJxR159mJg31WxHwrb2t9/yV9sfvuIBv+eYZE4a/sk3oi2Pi7AODkSREpm/WYAegnbLdemLhnjloWrV5ApqF8yqUT5E986tOvt2tSNklfQQrfS9kebjTR9XaON7LIeKzyXDqxGUyPB/J9KcrfRXcSJtAQ5GhP5oiOtHzIeLPivJcJf3hhwRF/irshYrY63ZqS8Nxt6vcZ1CwhPInhDvY14TQ== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Jan Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Milan Djokic Subject: [PATCH v5 11/22] xen/arm: vsmmuv3: Attach Stage-1 configuration to SMMUv3 hardware Thread-Topic: [PATCH v5 11/22] xen/arm: vsmmuv3: Attach Stage-1 configuration to SMMUv3 hardware Thread-Index: AQHda7kGEs1jLaaktkeEsaJubIp4rQ== Date: Tue, 3 Nov 2026 17:30:31 +0000 Message-ID: <60014e87e1c8e125e59a87bd89ce4ce87d4a590f.1793726692.git.milan_djokic@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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charset="utf-8" From: Rahul Singh Attach the Stage-1 configuration to device STE to support nested translation for the guests. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/arch/arm/include/asm/iommu.h | 7 ++ xen/drivers/passthrough/arm/smmu-v3.c | 114 +++++++++++++++++++++++++ xen/drivers/passthrough/arm/vsmmu-v3.c | 18 ++++ xen/include/xen/iommu.h | 6 ++ 4 files changed, 145 insertions(+) diff --git a/xen/arch/arm/include/asm/iommu.h b/xen/arch/arm/include/asm/io= mmu.h index ad15477e24..56bc9314a7 100644 --- a/xen/arch/arm/include/asm/iommu.h +++ b/xen/arch/arm/include/asm/iommu.h @@ -20,6 +20,13 @@ struct arch_iommu void *priv; }; =20 +struct iommu_guest_config { + paddr_t s1ctxptr; + uint8_t config; + uint8_t s1fmt; + uint8_t s1cdmax; +}; + const struct iommu_ops *iommu_get_ops(void); void iommu_set_ops(const struct iommu_ops *ops); =20 diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index d2dfb06cae..4f95b5206e 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -3061,6 +3061,37 @@ static struct arm_smmu_device *arm_smmu_get_by_dev(c= onst struct device *dev) return NULL; } =20 +static struct iommu_domain *arm_smmu_get_domain_by_sid(struct domain *d, + u32 sid) +{ + int i; + unsigned long flags; + struct iommu_domain *io_domain; + struct arm_smmu_domain *smmu_domain; + struct arm_smmu_master *master; + struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; + + /* + * Loop through the &xen_domain->contexts to locate a context + * associated with the target SMMU and device SID + */ + list_for_each_entry(io_domain, &xen_domain->contexts, list) { + smmu_domain =3D to_smmu_domain(io_domain); + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + for (i =3D 0; i < master->num_streams; i++) { + if (sid !=3D master->streams[i].id) + continue; + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + return io_domain; + } + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + } + return NULL; +} + static struct iommu_domain *arm_smmu_get_domain(struct domain *d, struct device *dev) { @@ -3274,6 +3305,88 @@ static void arm_smmu_iommu_xen_domain_teardown(struc= t domain *d) xfree(xen_domain); } =20 +static int arm_smmu_attach_guest_config(struct domain *d, uint32_t sid, + const struct iommu_guest_config *cfg) +{ + int ret =3D -EINVAL; + unsigned long flags; + struct arm_smmu_master *master; + struct arm_smmu_domain *smmu_domain; + struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; + struct iommu_domain *io_domain; + + spin_lock(&xen_domain->lock); + io_domain =3D arm_smmu_get_domain_by_sid(d, sid); + if (!io_domain) { + ret =3D -ENODEV; + goto out; + } + + smmu_domain =3D to_smmu_domain(io_domain); + + switch (cfg->config) { + case ARM_SMMU_DOMAIN_ABORT: + smmu_domain->abort =3D true; + smmu_domain->stage =3D cfg->config; + break; + case ARM_SMMU_DOMAIN_BYPASS: + smmu_domain->abort =3D false; + /* Install stage-2-only config */ + smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2; + break; + case ARM_SMMU_DOMAIN_S1: + /* Check stage-1 support */ + if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_S1)) { + dev_info(smmu_domain->smmu->dev, + "stage-1 not implemented\n"); + goto out; + } + + /* If stage-2 is not supported, configure stage-1 only */ + if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_S2)) { + dev_warn(smmu_domain->smmu->dev, + "SMMU does not implement stage-2 translation support. " + "Fallback to stage-1-only translation configuration\n"); + /* Enable Stage-1 translation. */ + smmu_domain->stage =3D ARM_SMMU_DOMAIN_S1; + } + else { + /* Check nested support */ + if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_NESTING)) { + dev_info(smmu_domain->smmu->dev, + "Nested translation not supported\n"); + goto out; + } + smmu_domain->stage =3D ARM_SMMU_DOMAIN_NESTED; + } + + /* Enable Stage-1 translation. */ + smmu_domain->s1_cfg.s1ctxptr =3D cfg->s1ctxptr; + smmu_domain->s1_cfg.s1fmt =3D cfg->s1fmt; + smmu_domain->s1_cfg.s1cdmax =3D cfg->s1cdmax; + smmu_domain->abort =3D false; + break; + default: + goto out; + } + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + /* + * TODO: The same Stage-1 configuration is applied to all SIDs + * belonging to this SMMU domain. PCI devices may require different + * Stage-1 configurations for different SIDs, which is not supported + * by the current implementation. + */ + list_for_each_entry(master, &smmu_domain->devices, domain_head) + arm_smmu_install_ste_for_dev(master); + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + ret =3D 0; +out: + spin_unlock(&xen_domain->lock); + return ret; +} + static const struct iommu_ops arm_smmu_iommu_ops =3D { .page_sizes =3D PAGE_SIZE_4K, .init =3D arm_smmu_iommu_xen_domain_init, @@ -3287,6 +3400,7 @@ static const struct iommu_ops arm_smmu_iommu_ops =3D { .dt_xlate =3D arm_smmu_dt_xlate, .add_device =3D arm_smmu_add_device, .remove_device =3D arm_smmu_remove_device, + .attach_guest_config =3D arm_smmu_attach_guest_config, }; =20 static __init int arm_smmu_dt_init(struct dt_device_node *dev, diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index 5e12d5c587..72f8075e0a 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -324,8 +324,11 @@ static int arm_vsmmu_handle_cfgi_ste(struct virt_smmu = *smmu, uint64_t *cmdptr) int ret; /* Only the first 8 bytes of the STE are currently used. */ uint64_t ste[1]; + struct domain *d =3D smmu->d; + struct domain_iommu *hd =3D dom_iommu(d); struct arm_vsmmu_s1_trans_cfg s1_cfg =3D {0}; uint32_t sid =3D smmu_cmd_get_sid(cmdptr[0]); + struct iommu_guest_config guest_cfg =3D {0}; =20 ret =3D arm_vsmmu_find_ste(smmu, sid, ste); if ( ret ) @@ -335,6 +338,21 @@ static int arm_vsmmu_handle_cfgi_ste(struct virt_smmu = *smmu, uint64_t *cmdptr) if ( ret ) return (ret =3D=3D -EAGAIN ) ? 0 : ret; =20 + guest_cfg.s1ctxptr =3D s1_cfg.s1ctxptr; + guest_cfg.s1fmt =3D s1_cfg.s1fmt; + guest_cfg.s1cdmax =3D s1_cfg.s1cdmax; + + if ( s1_cfg.bypassed ) + guest_cfg.config =3D ARM_SMMU_DOMAIN_BYPASS; + else if ( s1_cfg.aborted ) + guest_cfg.config =3D ARM_SMMU_DOMAIN_ABORT; + else + guest_cfg.config =3D ARM_SMMU_DOMAIN_S1; + + ret =3D hd->platform_ops->attach_guest_config(d, sid, &guest_cfg); + if ( ret ) + return ret; + return 0; } =20 diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index 37c4a1dc82..253f8bb6cb 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -312,6 +312,7 @@ static inline int iommu_add_dt_pci_sideband_ids(struct = pci_dev *pdev) #endif /* HAS_DEVICE_TREE_DISCOVERY */ =20 struct page_info; +struct iommu_guest_config; =20 /* * Any non-zero value returned from callbacks of this type will cause the @@ -387,6 +388,11 @@ struct iommu_ops { #endif /* Inhibit all interrupt generation, to be used at shutdown. */ void (*quiesce)(void); + +#ifdef CONFIG_ARM + int (*attach_guest_config)(struct domain *d, uint32_t sid, + const struct iommu_guest_config *cfg); +#endif }; =20 /* --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=epam.com); dmarc=pass(p=quarantine dis=none) header.from=epam.com ARC-Seal: i=2; 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charset="utf-8" From: Rahul Singh Event queue is used to send the events to guest when there is an events/ faults. Add support for event queue to send events to guest. Global error in SMMUv3 hw will be updated in smmu_gerror and smmu_gerrorn register. Add support for global error registers to send global error to guest. Add architectural error handling to the emulated command queue, updating the global error register and stopping command consumption on error. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/arch/arm/dom0less-build.c | 50 +++-- xen/drivers/passthrough/arm/smmu-v3.h | 20 ++ xen/drivers/passthrough/arm/vsmmu-v3.c | 246 +++++++++++++++++++++++-- xen/include/public/arch-arm.h | 2 + 4 files changed, 295 insertions(+), 23 deletions(-) diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index b55218d920..6ad2a1b745 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -386,34 +386,60 @@ int __init arch_parse_dom0less_node(struct dt_device_= node *node, if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) ) { int vpl011_virq =3D GUEST_VPL011_SPI; + int vsmmu_virq =3D GUEST_VSMMU_SPI; =20 d_cfg->arch.nr_spis =3D vgic_def_nr_spis(); =20 /* - * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is - * set, in which case it'll match the hardware. - * - * Since the domain is not yet created, we can't use - * d->arch.vpl011.irq. So the logic to find the vIRQ has to - * be hardcoded. - * The logic here shall be consistent with the one in - * domain_vpl011_init(). + * The VPL011 and VSMMU interrupts use predefined virtual SPIs, + * unless direct-map is set, in which case they match the + * corresponding hardware interrupts. */ if ( flags & CDF_directmap ) { +#ifdef CONFIG_ARM_VIRTUAL_IOMMU + struct host_iommu *hw_iommu; +#endif + /* + * Since the domain is not yet created, we can't use + * d->arch.vpl011.irq. So the logic to find the vIRQ has to + * be hardcoded. + * The logic here shall be consistent with the one in + * domain_vpl011_init(). + */ vpl011_virq =3D serial_irq(SERHND_DTUART); if ( vpl011_virq < 0 ) panic("Error getting IRQ number for this serial port %d\n", SERHND_DTUART); - } =20 +#ifdef CONFIG_ARM_VIRTUAL_IOMMU + /* + * The host SMMU list is already populated during SMMUv3 driver + * probe, so we can determine the highest SMMU interrupt ID + * from this list. + */ + vsmmu_virq =3D 0; + list_for_each_entry(hw_iommu, &host_iommu_list, entry) + { + vsmmu_virq =3D MAX(vsmmu_virq, hw_iommu->irq); + } +#endif + } /* - * vpl011 uses one emulated SPI. If vpl011 is requested, make - * sure that we allocate enough SPIs for it. - */ + * vpl011 uses one emulated SPI. If vpl011 is requested, make + * sure that we allocate enough SPIs for it. + */ if ( dt_property_read_bool(node, "vpl011") ) d_cfg->arch.nr_spis =3D MAX(d_cfg->arch.nr_spis, vpl011_virq - 32 + 1); + + /* + * vsmmu uses one emulated SPI. If vsmmu is enabled, make + * sure that we allocate enough SPIs for it. + */ + if ( d_cfg->arch.viommu_type =3D=3D XEN_DOMCTL_CONFIG_VIOMMU_SMMUV= 3 ) + d_cfg->arch.nr_spis =3D MAX(d_cfg->arch.nr_spis, + vsmmu_virq - 32 + 1); } else if ( flags & CDF_hardware ) panic("nr_spis cannot be specified for hardware domain\n"); diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug= h/arm/smmu-v3.h index 4a912be740..44ecb5d89c 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -358,6 +358,26 @@ =20 #define EVTQ_0_ID GENMASK_ULL(7, 0) =20 +#define EVT_ID_BAD_STREAMID 0x02 +#define EVT_ID_BAD_STE 0x04 +#define EVT_ID_TRANSLATION_FAULT 0x10 +#define EVT_ID_ADDR_SIZE_FAULT 0x11 +#define EVT_ID_ACCESS_FAULT 0x12 +#define EVT_ID_PERMISSION_FAULT 0x13 + +#define EVTQ_0_SSV (1UL << 11) +#define EVTQ_0_SSID GENMASK_ULL(31, 12) +#define EVTQ_0_SID GENMASK_ULL(63, 32) +#define EVTQ_1_STAG GENMASK_ULL(15, 0) +#define EVTQ_1_STALL (1UL << 31) +#define EVTQ_1_PnU (1UL << 33) +#define EVTQ_1_InD (1UL << 34) +#define EVTQ_1_RnW (1UL << 35) +#define EVTQ_1_S2 (1UL << 39) +#define EVTQ_1_CLASS GENMASK_ULL(41, 40) +#define EVTQ_1_TT_READ (1UL << 44) +#define EVTQ_2_ADDR GENMASK_ULL(63, 0) +#define EVTQ_3_IPA GENMASK_ULL(51, 12) /* PRI queue */ #define PRIQ_ENT_SZ_SHIFT 4 #define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3) diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index 72f8075e0a..17e83dcb1a 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -86,6 +86,35 @@ #define smmu_get_ste_s1ctxptr(x) FIELD_PREP(STRTAB_STE_0_S1CTXPTR_MASK,= \ FIELD_GET(STRTAB_STE_0_S1CTXPTR_MASK, = x)) =20 +/* event queue entry */ +struct arm_smmu_evtq_ent { + /* Common fields */ + uint8_t opcode; + uint32_t sid; + + /* Event-specific fields */ + union { + struct { + uint32_t ssid; + bool ssv; + } c_bad_ste_streamid; + + struct { + bool stall; + uint16_t stag; + uint32_t ssid; + bool ssv; + bool s2; + uint64_t addr; + bool rnw; + bool pnu; + bool ind; + uint8_t class; + uint64_t addr2; + } f_translation; + }; +}; + /* stage-1 translation configuration */ struct arm_vsmmu_s1_trans_cfg { paddr_t s1ctxptr; @@ -116,6 +145,7 @@ struct virt_smmu { uint32_t strtab_base_cfg; uint64_t strtab_base; uint32_t irq_ctrl; + uint32_t virq; uint64_t gerror_irq_cfg0; uint64_t evtq_irq_cfg0; struct arm_vsmmu_queue evtq, cmdq; @@ -161,9 +191,15 @@ static inline bool smmu_get_evtq_enabled(struct virt_s= mmu *smmu) spin_unlock(&smmu->cr0_lock); =20 return enabled; -}; +} =20 /* Queue manipulation functions */ +static bool queue_full(struct arm_vsmmu_queue *q) +{ + return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) && + Q_WRP(q, q->prod) !=3D Q_WRP(q, q->cons); +} + static bool queue_empty(struct arm_vsmmu_queue *q) { return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) && @@ -176,12 +212,141 @@ static void queue_inc_cons(struct arm_vsmmu_queue *q) q->cons =3D Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); } =20 +static void queue_inc_prod(struct arm_vsmmu_queue *q) +{ + u32 prod =3D (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + 1; + q->prod =3D Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); +} + static void dump_smmu_command(uint64_t *command) { gprintk(XENLOG_ERR, "cmd 0x%02llx: %016"PRIx64" %016"PRIx64"\n", smmu_cmd_get_command(command[0]), command[0], command[1]); } =20 +static void arm_vsmmu_update_irq(struct virt_smmu *smmu) +{ + bool evt_pending =3D false; + bool gerr_pending =3D false; + uint32_t irq_ctrl; + + spin_lock(&smmu->irq_cfg_lock); + irq_ctrl =3D smmu->irq_ctrl; + spin_unlock(&smmu->irq_cfg_lock); + + spin_lock(&smmu->evt_queue_lock); + evt_pending =3D !queue_empty(&smmu->evtq); + spin_unlock(&smmu->evt_queue_lock); + + spin_lock(&smmu->gerror_lock); + gerr_pending =3D (smmu->gerror ^ smmu->gerrorn) !=3D 0; + spin_unlock(&smmu->gerror_lock); + + vgic_inject_irq(smmu->d, NULL, smmu->virq, + ((irq_ctrl & IRQ_CTRL_EVTQ_IRQEN) && evt_pending) || + ((irq_ctrl & IRQ_CTRL_GERROR_IRQEN) && gerr_pending)); +} + +static void arm_vsmmu_set_gerror(struct virt_smmu *smmu, uint32_t gerror_e= rr) +{ + uint32_t pending, new_gerrors; + + spin_lock(&smmu->gerror_lock); + + pending =3D smmu->gerror ^ smmu->gerrorn; + new_gerrors =3D ~pending & gerror_err; + + if ( new_gerrors ) + smmu->gerror ^=3D new_gerrors; + + spin_unlock(&smmu->gerror_lock); + + arm_vsmmu_update_irq(smmu); +} + +static int arm_vsmmu_write_evtq(struct virt_smmu *smmu, uint64_t *evt) +{ + struct arm_vsmmu_queue *q =3D &smmu->evtq; + struct domain *d =3D smmu->d; + paddr_t addr; + int ret; + + if ( !smmu_get_evtq_enabled(smmu) ) + return 0; + + spin_lock(&smmu->evt_queue_lock); + + if ( queue_full(q) ) + { + /* + * Toggle OVFLG only if the previous overflow + * has already been acknowledged. + */ + if ( Q_OVF(smmu->evtq.prod) =3D=3D + Q_OVF(smmu->evtq.cons) ) + smmu->evtq.prod ^=3D Q_OVERFLOW_FLAG; + + spin_unlock(&smmu->evt_queue_lock); + return 0; + } + + addr =3D Q_PROD_ENT(q); + + ret =3D access_guest_memory_by_gpa(d, addr, evt, + sizeof(*evt) * EVTQ_ENT_DWORDS, true); + if ( ret ) + { + spin_unlock(&smmu->evt_queue_lock); + return ret; + } + + queue_inc_prod(q); + + spin_unlock(&smmu->evt_queue_lock); + + arm_vsmmu_update_irq(smmu); + + return 0; +} + +static void arm_vsmmu_send_event(struct virt_smmu *smmu, + struct arm_smmu_evtq_ent *ent) +{ + uint64_t evt[EVTQ_ENT_DWORDS]; + int ret; + + memset(evt, 0, 1 << EVTQ_ENT_SZ_SHIFT); + + if ( !smmu_get_evtq_enabled(smmu) ) + return; + + evt[0] |=3D FIELD_PREP(EVTQ_0_ID, ent->opcode); + evt[0] |=3D FIELD_PREP(EVTQ_0_SID, ent->sid); + + switch ( ent->opcode ) + { + case EVT_ID_BAD_STREAMID: + case EVT_ID_BAD_STE: + evt[0] |=3D FIELD_PREP(EVTQ_0_SSID, ent->c_bad_ste_streamid.ssid); + evt[0] |=3D FIELD_PREP(EVTQ_0_SSV, ent->c_bad_ste_streamid.ssv); + break; + case EVT_ID_TRANSLATION_FAULT: + case EVT_ID_ADDR_SIZE_FAULT: + case EVT_ID_ACCESS_FAULT: + case EVT_ID_PERMISSION_FAULT: + break; + default: + gdprintk(XENLOG_WARNING, "vSMMUv3: event opcode is bad\n"); + break; + } + + ret =3D arm_vsmmu_write_evtq(smmu, evt); + if ( ret ) + arm_vsmmu_set_gerror(smmu, GERROR_EVTQ_ABT_ERR); + + return; +} + static int arm_vsmmu_find_ste(struct virt_smmu *smmu, uint32_t sid, uint64_t *ste) { @@ -190,6 +355,14 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu, = uint32_t sid, uint32_t log2size; int strtab_size_shift; int ret; + struct arm_smmu_evtq_ent ent =3D { + .opcode =3D EVT_ID_BAD_STREAMID, + .sid =3D sid, + .c_bad_ste_streamid =3D { + .ssid =3D 0, + .ssv =3D false, + }, + }; =20 spin_lock(&smmu->strtab_cfg_lock); log2size =3D MIN(FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, smmu->strtab_base= _cfg), @@ -197,7 +370,10 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu, = uint32_t sid, spin_unlock(&smmu->strtab_cfg_lock); =20 if ( sid >=3D (1U << log2size) ) + { + arm_vsmmu_send_event(smmu, &ent); return -EINVAL; + } =20 spin_lock(&smmu->strtab_cfg_lock); if ( FIELD_GET(STRTAB_BASE_CFG_FMT, smmu->strtab_base_cfg) =3D=3D @@ -250,6 +426,7 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu, u= int32_t sid, { gdprintk(XENLOG_ERR, "idx=3D%d > max_l2_ste=3D%d\n", idx, max_l2_ste); + arm_vsmmu_send_event(smmu, &ent); return -EINVAL; } addr =3D l2ptr + idx * sizeof(*ste) * STRTAB_STE_DWORDS; @@ -278,6 +455,14 @@ static int arm_vsmmu_decode_ste(struct virt_smmu *smmu= , uint32_t sid, uint64_t *ste) { uint64_t val =3D ste[0]; + struct arm_smmu_evtq_ent ent =3D { + .opcode =3D EVT_ID_BAD_STE, + .sid =3D sid, + .c_bad_ste_streamid =3D { + .ssid =3D 0, + .ssv =3D false, + }, + }; =20 if ( !(val & STRTAB_STE_0_V) ) { @@ -316,6 +501,7 @@ static int arm_vsmmu_decode_ste(struct virt_smmu *smmu,= uint32_t sid, return 0; =20 bad_ste: + arm_vsmmu_send_event(smmu, &ent); return -EINVAL; } =20 @@ -373,16 +559,19 @@ static int arm_vsmmu_handle_cmds(struct virt_smmu *sm= mu) * monopolizing CPU time. Implement commands rescheduling and asynchro= nous * execution as outlined in the design. */ - while ( !queue_empty(q) ) + while ( !queue_empty(q) && + ((smmu->gerror ^ smmu->gerrorn) & (GERROR_CMDQ_ERR)) =3D=3D 0 ) { - int ret; - addr =3D Q_CONS_ENT(q); ret =3D access_guest_memory_by_gpa(d, addr, command, sizeof(command), false); - if ( ret ) { - queue_inc_cons(q); - return ret; + if ( ret ) + { + smmu->cmdq.cons &=3D ~CMDQ_CONS_ERR; + smmu->cmdq.cons |=3D FIELD_PREP(CMDQ_CONS_ERR, + CMDQ_ERR_CERROR_ABT_IDX); + arm_vsmmu_set_gerror(smmu, GERROR_CMDQ_ERR); + break; } =20 switch ( smmu_cmd_get_command(command[0]) ) @@ -406,6 +595,10 @@ static int arm_vsmmu_handle_cmds(struct virt_smmu *smm= u) default: gdprintk(XENLOG_ERR, "vSMMUv3: unhandled command\n"); dump_smmu_command(command); + smmu->cmdq.cons &=3D ~CMDQ_CONS_ERR; + smmu->cmdq.cons |=3D FIELD_PREP(CMDQ_CONS_ERR, + CMDQ_ERR_CERROR_ILL_IDX); + arm_vsmmu_set_gerror(smmu, GERROR_CMDQ_ERR); break; } =20 @@ -416,6 +609,15 @@ static int arm_vsmmu_handle_cmds(struct virt_smmu *smm= u) ret); dump_smmu_command(command); } + + /* + * Stop consuming the command queue if a command error occurred. + * CMDQ_CONS continues to point at the offending command until the + * error is acknowledged. + */ + if ( (smmu->gerror ^ smmu->gerrorn) & GERROR_CMDQ_ERR ) + break; + queue_inc_cons(q); } =20 @@ -454,6 +656,7 @@ static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info= _t *info, vreg_reg32_update(®32, r, info); smmu->evtq.cons =3D reg32; spin_unlock(&smmu->evt_queue_lock); + arm_vsmmu_update_irq(smmu); break; default: printk(XENLOG_G_ERR @@ -584,6 +787,7 @@ static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info= _t *info, vreg_reg32_update(®32, r, info); smmu->irq_ctrl =3D reg32; spin_unlock(&smmu->irq_cfg_lock); + arm_vsmmu_update_irq(smmu); break; =20 case VREG64(ARM_SMMU_GERROR_IRQ_CFG0): @@ -608,11 +812,20 @@ static int vsmmuv3_mmio_write(struct vcpu *v, mmio_in= fo_t *info, =20 case VREG32(ARM_SMMU_GERRORN): if ( dabt.size !=3D DABT_WORD ) goto bad_width; + /* + * Acquire cmd_queue_lock before updating GERRORN to serialize= error + * acknowledgement with command processing and ensure that rep= aired + * commands are not skipped. + */ + spin_lock(&smmu->cmd_queue_lock); spin_lock(&smmu->gerror_lock); reg32 =3D smmu->gerrorn; vreg_reg32_update(®32, r, info); smmu->gerrorn =3D reg32; spin_unlock(&smmu->gerror_lock); + arm_vsmmu_update_irq(smmu); + arm_vsmmu_handle_cmds(smmu); + spin_unlock(&smmu->cmd_queue_lock); break; =20 default: @@ -916,9 +1129,10 @@ static const struct mmio_handler_ops vsmmuv3_mmio_han= dler =3D { .write =3D vsmmuv3_mmio_write, }; =20 -static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t siz= e, - uint32_t features) +static int vsmmuv3_init_single(struct domain *d, paddr_t addr, + paddr_t size, uint32_t virq, uint32_t featu= res) { + int ret; struct virt_smmu *smmu; =20 smmu =3D xzalloc(struct virt_smmu); @@ -927,6 +1141,7 @@ static int vsmmuv3_init_single(struct domain *d, paddr= _t addr, paddr_t size, =20 smmu->d =3D d; smmu->features =3D features; + smmu->virq =3D virq; smmu->cmdq.ent_size =3D CMDQ_ENT_DWORDS * DWORDS_BYTES; smmu->evtq.ent_size =3D EVTQ_ENT_DWORDS * DWORDS_BYTES; =20 @@ -939,6 +1154,15 @@ static int vsmmuv3_init_single(struct domain *d, padd= r_t addr, paddr_t size, spin_lock_init(&smmu->strtab_cfg_lock); spin_lock_init(&smmu->irq_cfg_lock); =20 + ret =3D vgic_reserve_virq(d, virq); + if ( !ret ) + { + printk(XENLOG_G_ERR + "vSMMUv3: Failed to reserve domain vIRQ %u\n", virq); + xfree(smmu); + return -EINVAL; + } + register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu); =20 /* Register the vIOMMU to be able to clean it up later. */ @@ -990,7 +1214,7 @@ static int domain_vsmmuv3_init(struct domain *d) { smmu =3D (const struct arm_smmu_device *) hw_iommu->iommu; ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size, - smmu->features); + hw_iommu->irq, smmu->features); if ( ret ) return ret; } @@ -1033,7 +1257,7 @@ static int domain_vsmmuv3_init(struct domain *d) } =20 ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_S= IZE, - features); + GUEST_VSMMU_SPI, features); if ( ret ) return ret; } diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 7c76f2afd4..35cdbbb867 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -524,6 +524,8 @@ typedef uint64_t xen_callback_t; #define GUEST_VIRTIO_MMIO_SPI_FIRST 33 #define GUEST_VIRTIO_MMIO_SPI_LAST 43 =20 +#define GUEST_VSMMU_SPI 44 + /* * SGI is the preferred delivery mechanism of FF-A pending notifications or * schedule recveive interrupt. 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charset="utf-8" From: Rahul Singh XEN will create an IOMMU device tree node in the device tree to enable the dom0 to discover the virtual SMMUv3 during dom0 boot. IOMMU device tree node will only be created when viommu is enabled via Kconfig build options. "iommus" property will be added for dom0 devices to virtual IOMMU node to enable the dom0 linux kernel to configure the IOMMU. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/arch/arm/domain_build.c | 104 +++++++++++++++++++++++++++++- xen/arch/arm/include/asm/viommu.h | 1 + 2 files changed, 103 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index f749f9ae10..79727ce206 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -558,9 +558,12 @@ static int __init write_properties(struct domain *d, s= truct kernel_info *kinfo, continue; } =20 - if ( iommu_node ) + /* + * Expose IOMMU specific properties to hwdom when vIOMMU is + * enabled. + */ + if ( iommu_node && viommu_get_type() =3D=3D XEN_DOMCTL_CONFIG_VIOM= MU_NONE ) { - /* Don't expose IOMMU specific properties to hwdom */ if ( dt_property_name_is_equal(prop, "iommus") ) continue; =20 @@ -1468,6 +1471,97 @@ int __init make_timer_node(const struct kernel_info = *kinfo) return res; } =20 +#ifdef CONFIG_ARM_VIRTUAL_IOMMU +static int __init make_hwdom_viommu_node(const struct kernel_info *kinfo, + struct dt_device_node *node) +{ + uint32_t len; + int res; + char buf[24]; + void *fdt =3D kinfo->fdt; + const void *prop =3D NULL; + const struct dt_device_node *iommu =3D NULL; + struct host_iommu *iommu_data; + gic_interrupt_t intr; + + if ( list_empty(&host_iommu_list) ) + return 0; + + list_for_each_entry( iommu_data, &host_iommu_list, entry ) + { + if ( iommu_data->hwdom_node_created || + iommu_data->dt_node->parent !=3D node->parent ) + continue; + + iommu =3D iommu_data->dt_node; + + snprintf(buf, sizeof(buf), "iommu@%"PRIx64, iommu_data->addr); + + res =3D fdt_begin_node(fdt, buf); + if ( res ) + return res; + + prop =3D dt_get_property(iommu, "compatible", &len); + if ( !prop ) + { + res =3D -FDT_ERR_XEN(ENOENT); + return res; + } + + res =3D fdt_property(fdt, "compatible", prop, len); + if ( res ) + return res; + + if ( iommu->phandle ) + { + res =3D fdt_property_cell(fdt, "phandle", iommu->phandle); + if ( res ) + return res; + } + + /* Use the same reg regions as the IOMMU node in host DTB. */ + prop =3D dt_get_property(iommu, "reg", &len); + if ( !prop ) + { + printk(XENLOG_ERR "vIOMMU: Can't find IOMMU reg property.\n"); + res =3D -FDT_ERR_XEN(ENOENT); + return res; + } + + res =3D fdt_property(fdt, "reg", prop, len); + if ( res ) + return res; + + prop =3D dt_get_property(iommu, "#iommu-cells", &len); + if ( !prop ) + { + res =3D -FDT_ERR_XEN(ENOENT); + return res; + } + + res =3D fdt_property(fdt, "#iommu-cells", prop, len); + if ( res ) + return res; + + res =3D fdt_property_string(fdt, "interrupt-names", "combined"); + if ( res ) + return res; + + set_interrupt(intr, iommu_data->irq, 0xf, DT_IRQ_TYPE_LEVEL_HIGH); + + res =3D fdt_property_interrupts(kinfo, &intr, 1); + if ( res ) + return res; + + iommu_data->hwdom_node_created =3D true; + + fdt_end_node(fdt); + } + + return res; +} +#endif + static int __init handle_node(struct domain *d, struct kernel_info *kinfo, struct dt_device_node *node, p2m_type_t p2mt) @@ -1536,6 +1630,12 @@ static int __init handle_node(struct domain *d, stru= ct kernel_info *kinfo, if ( dt_match_node(timer_matches, node) ) return make_timer_node(kinfo); =20 +#ifdef CONFIG_ARM_VIRTUAL_IOMMU + if ( device_get_class(node) =3D=3D DEVICE_IOMMU && + viommu_get_type() !=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE ) + return make_hwdom_viommu_node(kinfo, node); +#endif + /* Skip nodes used by Xen */ if ( dt_device_used_by(node) =3D=3D DOMID_XEN ) { diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/v= iommu.h index 844cf34d56..5ae21042f0 100644 --- a/xen/arch/arm/include/asm/viommu.h +++ b/xen/arch/arm/include/asm/viommu.h @@ -20,6 +20,7 @@ struct host_iommu { paddr_t size; /* Used for dom0 EVTQ and GERROR interrupts (1-1 IRQ mapping) */ uint32_t irq; + bool hwdom_node_created; }; =20 struct viommu_ops { --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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b=aYojk+1DgmeO0jn/9JeAoASPDeLUDBLUa3QjE8athQ5pOZ5RTAUTaNAuHTGHVsi+geoYAgphyFBPBjoNqYCseTqASR927TYLq7J2X6tOHZQYNNTG0b5rCLqoVBgG0H3xvObdN0UjgBMcgtBMkixY0DrKOt53SNTsyv4UxQzjcmrwtB8dWwNgz5dZsJqUUjnJd0K7IjNdx+ilREEubO9qC/Kq5cMq4Pm+IHfV+DS80/G1dP0/wgkA4qA1l1Lkq+yKg6AzHXJHinDdW3vHYj8bo2Pj7/ROXdDN/DlxRXFOZNJCQTmOt6uL7btPxC3WHDvIzipgHAIBCfYsc449LvA0MQ== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Milan Djokic , Luca Fancellu Subject: [PATCH v5 14/22] xen/arm: vsmmuv3: Emulated SMMUv3 device tree node for dom0less Thread-Topic: [PATCH v5 14/22] xen/arm: vsmmuv3: Emulated SMMUv3 device tree node for dom0less Thread-Index: AQHda7kNdMT5x1BE9UuSem23a2jAMA== Date: Tue, 3 Nov 2026 17:30:43 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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charset="utf-8" From: Rahul Singh XEN will create an Emulated SMMUv3 device tree node in the device tree to enable the dom0less domains to discover the virtual SMMUv3 during boot. Emulated SMMUv3 device tree node will only be created when cmdline option vsmmuv3 is enabled. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic Reviewed-by: Luca Fancellu --- xen/arch/arm/dom0less-build.c | 53 +++++++++++++++++++++++++++ xen/include/public/device_tree_defs.h | 1 + 2 files changed, 54 insertions(+) diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 6ad2a1b745..6bd705102f 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -219,10 +219,63 @@ static int __init make_vpl011_uart_node(struct kernel= _info *kinfo) } #endif =20 +#ifdef CONFIG_VIRTUAL_ARM_SMMU_V3 +static int __init make_vsmmuv3_node(const struct kernel_info *kinfo) +{ + int res; + char buf[24]; + __be32 reg[GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS]; + __be32 *cells; + void *fdt =3D kinfo->fdt; + + snprintf(buf, sizeof(buf), "iommu@%llx", GUEST_VSMMUV3_BASE); + + res =3D fdt_begin_node(fdt, buf); + if ( res ) + return res; + + res =3D fdt_property_string(fdt, "compatible", "arm,smmu-v3"); + if ( res ) + return res; + + /* Create reg property */ + cells =3D ®[0]; + dt_child_set_range(&cells, GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_C= ELLS, + GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_SIZE); + res =3D fdt_property(fdt, "reg", reg, + (GUEST_ROOT_ADDRESS_CELLS + + GUEST_ROOT_SIZE_CELLS) * sizeof(*reg)); + if ( res ) + return res; + + res =3D fdt_property_cell(fdt, "phandle", GUEST_PHANDLE_VSMMUV3); + if ( res ) + return res; + + res =3D fdt_property_cell(fdt, "#iommu-cells", 1); + if ( res ) + return res; + + res =3D fdt_end_node(fdt); + + return res; +} +#endif + int __init make_arch_nodes(struct kernel_info *kinfo) { int ret; =20 + +#ifdef CONFIG_VIRTUAL_ARM_SMMU_V3 + if ( viommu_get_type() =3D=3D XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3 ) + { + ret =3D make_vsmmuv3_node(kinfo); + if ( ret ) + return -EINVAL; + } +#endif + ret =3D make_psci_node(kinfo->fdt); if ( ret ) return -EINVAL; diff --git a/xen/include/public/device_tree_defs.h b/xen/include/public/dev= ice_tree_defs.h index 9e80d0499d..7846a0425c 100644 --- a/xen/include/public/device_tree_defs.h +++ b/xen/include/public/device_tree_defs.h @@ -14,6 +14,7 @@ */ #define GUEST_PHANDLE_GIC (65000) #define GUEST_PHANDLE_IOMMU (GUEST_PHANDLE_GIC + 1) +#define GUEST_PHANDLE_VSMMUV3 (GUEST_PHANDLE_IOMMU + 1) =20 #define GUEST_ROOT_ADDRESS_CELLS 2 #define GUEST_ROOT_SIZE_CELLS 2 --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" From: Rahul Singh libxl will create an Emulated SMMUv3 device tree node in the device tree to enable the guest OS to discover the virtual SMMUv3 during guest boot. Emulated SMMUv3 device tree node will only be created when "viommu=3Dsmmuv3" is set in xl domain configuration. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- tools/libs/light/libxl_arm.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c index 7f1adfd79b..bbcc989284 100644 --- a/tools/libs/light/libxl_arm.c +++ b/tools/libs/light/libxl_arm.c @@ -921,6 +921,36 @@ static int make_vpl011_uart_node(libxl__gc *gc, void *= fdt, return 0; } =20 +static int make_vsmmuv3_node(libxl__gc *gc, void *fdt, + const struct arch_info *ainfo, + struct xc_dom_image *dom) +{ + int res; + const char *name =3D GCSPRINTF("iommu@%llx", GUEST_VSMMUV3_BASE); + + res =3D fdt_begin_node(fdt, name); + if (res) return res; + + res =3D fdt_property_compat(gc, fdt, 1, "arm,smmu-v3"); + if (res) return res; + + res =3D fdt_property_regs(gc, fdt, GUEST_ROOT_ADDRESS_CELLS, + GUEST_ROOT_SIZE_CELLS, 1, GUEST_VSMMUV3_BASE, + GUEST_VSMMUV3_SIZE); + if (res) return res; + + res =3D fdt_property_cell(fdt, "phandle", GUEST_PHANDLE_VSMMUV3); + if (res) return res; + + res =3D fdt_property_cell(fdt, "#iommu-cells", 1); + if (res) return res; + + res =3D fdt_end_node(fdt); + if (res) return res; + + return 0; +} + static int make_vpci_node(libxl__gc *gc, void *fdt, const struct arch_info *ainfo, struct xc_dom_image *dom) @@ -1428,6 +1458,9 @@ next_resize: if (d_config->num_pcidevs) FDT( make_vpci_node(gc, fdt, ainfo, dom) ); =20 + if (info->arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMMUV3) + FDT( make_vsmmuv3_node(gc, fdt, ainfo, dom) ); + for (i =3D 0; i < d_config->num_disks; i++) { libxl_device_disk *disk =3D &d_config->disks[i]; =20 --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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b=BE/V+1Xcr+OOevg4yThCCbENNvxGqnBpF+MVmR0oyZBmXqV9xyBg5ZDwvuwhCrxDjpnBW2TGJ4X0a6fX9l9jK0UZftrZ/C1vCqPZirv+pCmOmHijH+AST0ApKkQOYxUaTY0hiZpX2R8ROFfhgeyK5BkHDEiUmuybIDEsPdw8eH+askJu/sPbU5aOFDp6lxt+fg0IrDzPF2boEGywTrb/2yztoO8ZerHSPsCEeJ59FTv3EvtmTiOig3iJU7YEDtqY8SNmoLOs2dd0OrAQMqy53xGOfXytS54RgTiCb9c+Z98pXwFGLo1FsX9lYyDdT7kJktV/nUrp/MtQILJvHfm81A== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Rahul Singh , Anthony PERARD , Juergen Gross , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Milan Djokic Subject: [PATCH v5 16/22] xen/arm: vsmmuv3: Insert vIRQ properties into vIOMMU device tree node Thread-Topic: [PATCH v5 16/22] xen/arm: vsmmuv3: Insert vIRQ properties into vIOMMU device tree node Thread-Index: AQHda7kQMHPRCWWvpUGDZFNoCpKf4w== Date: Tue, 3 Nov 2026 17:30:47 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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charset="utf-8" From: Rahul Singh Insert vIRQ properties for event queue and GERROR handling into the emulated IOMMU device tree node for dom0less and libxl guests. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- tools/libs/light/libxl_arm.c | 30 +++++++++++++++++++++++++++--- xen/arch/arm/dom0less-build.c | 17 +++++++++++++++++ 2 files changed, 44 insertions(+), 3 deletions(-) diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c index bbcc989284..72b19d68af 100644 --- a/tools/libs/light/libxl_arm.c +++ b/tools/libs/light/libxl_arm.c @@ -86,8 +86,8 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, { uint32_t nr_spis =3D 0, cfg_nr_spis =3D d_config->b_info.arch_arm.nr_s= pis; unsigned int i; - uint32_t vuart_irq, virtio_irq =3D 0; - bool vuart_enabled =3D false, virtio_enabled =3D false; + uint32_t vuart_irq, virtio_irq =3D 0, vsmmu_irq =3D 0; + bool vuart_enabled =3D false, virtio_enabled =3D false, vsmmu_enabled = =3D false; uint64_t virtio_mmio_base =3D GUEST_VIRTIO_MMIO_BASE; uint32_t virtio_mmio_irq =3D GUEST_VIRTIO_MMIO_SPI_FIRST; int rc; @@ -97,11 +97,21 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, * of SPI VIRQ for pl011. */ if (d_config->b_info.arch_arm.vuart =3D=3D LIBXL_VUART_TYPE_SBSA_UART)= { - nr_spis +=3D (GUEST_VPL011_SPI - 32) + 1; vuart_irq =3D GUEST_VPL011_SPI; + nr_spis =3D max(nr_spis, vuart_irq - 32 + 1); vuart_enabled =3D true; } =20 + /* + * If smmuv3 viommu is enabled then increment the nr_spis to allow + * allocation of SPI VIRQ for VSMMU. + */ + if (d_config->b_info.arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMM= UV3) { + vsmmu_irq =3D GUEST_VSMMU_SPI; + nr_spis =3D max(nr_spis, vsmmu_irq - 32 + 1); + vsmmu_enabled =3D true; + } + for (i =3D 0; i < d_config->num_disks; i++) { libxl_device_disk *disk =3D &d_config->disks[i]; =20 @@ -170,6 +180,11 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, return ERROR_FAIL; } =20 + if (vsmmu_enabled && irq =3D=3D vsmmu_irq) { + LOG(ERROR, "Physical IRQ %u conflicting with vSMMUv3 SPI\n", i= rq); + return ERROR_FAIL; + } + if (irq < 32) continue; =20 @@ -927,6 +942,7 @@ static int make_vsmmuv3_node(libxl__gc *gc, void *fdt, { int res; const char *name =3D GCSPRINTF("iommu@%llx", GUEST_VSMMUV3_BASE); + gic_interrupt intr; =20 res =3D fdt_begin_node(fdt, name); if (res) return res; @@ -945,6 +961,14 @@ static int make_vsmmuv3_node(libxl__gc *gc, void *fdt, res =3D fdt_property_cell(fdt, "#iommu-cells", 1); if (res) return res; =20 + res =3D fdt_property_string(fdt, "interrupt-names", "combined"); + if (res) return res; + + set_interrupt(intr, GUEST_VSMMU_SPI, 0xf, DT_IRQ_TYPE_LEVEL_HIGH); + + res =3D fdt_property_interrupts(gc, fdt, &intr, 1); + if (res) return res; + res =3D fdt_end_node(fdt); if (res) return res; =20 diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 6bd705102f..9e519ff3da 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -226,6 +226,7 @@ static int __init make_vsmmuv3_node(const struct kernel= _info *kinfo) char buf[24]; __be32 reg[GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS]; __be32 *cells; + gic_interrupt_t intr; void *fdt =3D kinfo->fdt; =20 snprintf(buf, sizeof(buf), "iommu@%llx", GUEST_VSMMUV3_BASE); @@ -256,6 +257,22 @@ static int __init make_vsmmuv3_node(const struct kerne= l_info *kinfo) if ( res ) return res; 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charset="utf-8" From: Rahul Singh Stage-1 translation is handled by guest, therefore stage-1 fault has to be forwarded to guest. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/drivers/passthrough/arm/smmu-v3.c | 45 ++++++++++++++++++++++++-- xen/drivers/passthrough/arm/vsmmu-v3.c | 44 +++++++++++++++++++++++++ xen/drivers/passthrough/arm/vsmmu-v3.h | 8 +++++ 3 files changed, 95 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index 4f95b5206e..f213b3de12 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -871,7 +871,6 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_devi= ce *smmu, u32 sid) return 0; } =20 -__maybe_unused static struct arm_smmu_master * arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid) { @@ -892,10 +891,48 @@ arm_smmu_find_master(struct arm_smmu_device *smmu, u3= 2 sid) return NULL; } =20 +static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64 *evt) +{ + int ret =3D 0; + struct arm_smmu_master *master; + u32 sid =3D FIELD_GET(EVTQ_0_SID, evt[0]); + + switch (FIELD_GET(EVTQ_0_ID, evt[0])) { + case EVT_ID_TRANSLATION_FAULT: + break; + case EVT_ID_ADDR_SIZE_FAULT: + break; + case EVT_ID_ACCESS_FAULT: + break; + case EVT_ID_PERMISSION_FAULT: + break; + default: + return -EOPNOTSUPP; + } + + /* Stage-2 event */ + if (evt[1] & EVTQ_1_S2) + return -EFAULT; + + mutex_lock(&smmu->streams_mutex); + master =3D arm_smmu_find_master(smmu, sid); + if (!master) { + ret =3D -EINVAL; + goto out_unlock; + } + + if (master->domain) + ret =3D arm_vsmmu_handle_evt(master->domain->d, smmu->dev, evt); + +out_unlock: + mutex_unlock(&smmu->streams_mutex); + return ret; +} + /* IRQ and event handlers */ static void arm_smmu_evtq_tasklet(void *dev) { - int i; + int i, ret; struct arm_smmu_device *smmu =3D dev; struct arm_smmu_queue *q =3D &smmu->evtq.q; struct arm_smmu_ll_queue *llq =3D &q->llq; @@ -905,6 +942,10 @@ static void arm_smmu_evtq_tasklet(void *dev) while (!queue_remove_raw(q, evt)) { u8 id =3D FIELD_GET(EVTQ_0_ID, evt[0]); =20 + ret =3D arm_smmu_handle_evt(smmu, evt); + if (!ret) + continue; + dev_info(smmu->dev, "event 0x%02x received:\n", id); for (i =3D 0; i < ARRAY_SIZE(evt); ++i) dev_info(smmu->dev, "\t0x%016llx\n", diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index 17e83dcb1a..24588affe9 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -347,6 +347,49 @@ static void arm_vsmmu_send_event(struct virt_smmu *smm= u, return; } =20 +static struct virt_smmu *vsmmuv3_find_by_addr(struct domain *d, paddr_t pa= ddr) +{ + struct virt_smmu *smmu; + + list_for_each_entry( smmu, &d->arch.viommu_list, viommu_list ) + { + if ( smmu->addr =3D=3D paddr ) + return smmu; + } + + return NULL; +} + +int arm_vsmmu_handle_evt(struct domain *d, struct device *dev, uint64_t *e= vt) +{ + int ret; + struct virt_smmu *smmu; + + if ( domain_use_host_layout(d) ) + { + paddr_t paddr; + /* Base address */ + ret =3D dt_device_get_address(dev_to_dt(dev), 0, &paddr, NULL); + if ( ret ) + return -EINVAL; + + smmu =3D vsmmuv3_find_by_addr(d, paddr); + if ( !smmu ) + return -ENODEV; + } + else + { + smmu =3D list_entry(d->arch.viommu_list.next, + struct virt_smmu, viommu_list); + } + + ret =3D arm_vsmmu_write_evtq(smmu, evt); + if ( ret ) + arm_vsmmu_set_gerror(smmu, GERROR_EVTQ_ABT_ERR); + + return 0; +} + static int arm_vsmmu_find_ste(struct virt_smmu *smmu, uint32_t sid, uint64_t *ste) { @@ -1142,6 +1185,7 @@ static int vsmmuv3_init_single(struct domain *d, padd= r_t addr, smmu->d =3D d; smmu->features =3D features; smmu->virq =3D virq; + smmu->addr =3D addr; smmu->cmdq.ent_size =3D CMDQ_ENT_DWORDS * DWORDS_BYTES; smmu->evtq.ent_size =3D EVTQ_ENT_DWORDS * DWORDS_BYTES; =20 diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.h b/xen/drivers/passthrou= gh/arm/vsmmu-v3.h index 9f4c86abd5..d4b7cf805f 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.h +++ b/xen/drivers/passthrough/arm/vsmmu-v3.h @@ -8,6 +8,8 @@ =20 void vsmmuv3_set_type(void); =20 +int arm_vsmmu_handle_evt(struct domain *d, struct device *dev, uint64_t *e= vt); + #else =20 static inline void __init vsmmuv3_set_type(void) @@ -15,6 +17,12 @@ static inline void __init vsmmuv3_set_type(void) return; } =20 +static inline int arm_vsmmu_handle_evt(struct domain *d, + struct device *dev, uint64_t *evt) +{ + return -EINVAL; +} + #endif /* CONFIG_VIRTUAL_ARM_SMMU_V3 */ =20 #endif /* __ARCH_ARM_VSMMU_V3_H__ */ --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=epam.com); dmarc=pass(p=quarantine dis=none) header.from=epam.com ARC-Seal: i=2; a=rsa-sha256; t=1793727083; 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charset="utf-8" From: Rahul Singh To configure IOMMU in guest for passthrough devices, user will need to copy the unmodified "iommus" property from host device tree to partial device tree. To enable the dom0 linux kernel to configure the IOMMU correctly replace the phandle in partial device tree with virtual IOMMU phandle when "iommus" property is set. Signed-off-by: Rahul Singh Singed-off-by: Milan Djokic Reviewed-by: Luca Fancellu --- tools/libs/light/libxl_arm.c | 47 +++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c index 72b19d68af..0dc3789d08 100644 --- a/tools/libs/light/libxl_arm.c +++ b/tools/libs/light/libxl_arm.c @@ -1342,6 +1342,41 @@ static int copy_partial_fdt(libxl__gc *gc, void *fdt= , void *pfdt) return 0; } =20 +static int modify_partial_fdt(libxl__gc *gc, void *pfdt) +{ + int nodeoff, proplen, i, r; + const fdt32_t *prop; + fdt32_t *prop_c; + + nodeoff =3D fdt_path_offset(pfdt, "/passthrough"); + if (nodeoff < 0) + return nodeoff; + + for (nodeoff =3D fdt_first_subnode(pfdt, nodeoff); + nodeoff >=3D 0; + nodeoff =3D fdt_next_subnode(pfdt, nodeoff)) { + + prop =3D fdt_getprop(pfdt, nodeoff, "iommus", &proplen); + if (!prop) + continue; + + prop_c =3D libxl__zalloc(gc, proplen); + + for (i =3D 0; i < proplen / 8; ++i) { + prop_c[i * 2] =3D cpu_to_fdt32(GUEST_PHANDLE_VSMMUV3); + prop_c[i * 2 + 1] =3D prop[i * 2 + 1]; + } + + r =3D fdt_setprop(pfdt, nodeoff, "iommus", prop_c, proplen); + if (r) { + LOG(ERROR, "Can't set the iommus property in partial FDT"); + return r; + } + } + + return 0; +} + #else =20 static int check_partial_fdt(libxl__gc *gc, void *fdt, size_t size) @@ -1360,6 +1395,13 @@ static int copy_partial_fdt(libxl__gc *gc, void *fdt= , void *pfdt) return -FDT_ERR_INTERNAL; } =20 +static int modify_partial_fdt(libxl__gc *gc, void *pfdt) +{ + LOG(ERROR, "partial device tree not supported"); + + return ERROR_FAIL; +} + #endif /* ENABLE_PARTIAL_DEVICE_TREE */ =20 #define FDT_MAX_SIZE (1<<20) @@ -1482,8 +1524,11 @@ next_resize: if (d_config->num_pcidevs) FDT( make_vpci_node(gc, fdt, ainfo, dom) ); =20 - if (info->arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMMUV3) + if (info->arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMMUV3) { FDT( make_vsmmuv3_node(gc, fdt, ainfo, dom) ); + if (pfdt) + FDT( modify_partial_fdt(gc, pfdt) ); + } =20 for (i =3D 0; i < d_config->num_disks; i++) { libxl_device_disk *disk =3D &d_config->disks[i]; --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=epam.com); dmarc=pass(p=quarantine dis=none) header.from=epam.com ARC-Seal: i=2; a=rsa-sha256; t=1793727071; cv=pass; d=zohomail.com; s=zohoarc; b=atz/SPFnXxln/MD+Je3iblVVriSxfcfGl4rmzeyPSCwA89YnO4InMSwXuAf2fp4i/PuMA2ZniV11Spn1QxVqAst16cIHdk/p/78b9V5HDHAO6QRz1lq8NpRI+Y6HyDu2rKKtvUpK5e4nHs5LnA+w0NwJcCJHNg13LHLVPxXBrnM= ARC-Message-Signature: i=2; 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charset="utf-8" From: Rahul Singh To configure IOMMU in guest for passthrough devices, user will need to copy the unmodified "iommus" property from host device tree to partial device tree. To enable the dom0 linux kernel to configure the IOMMU correctly replace the phandle in partial device tree with virtual IOMMU phandle when "iommus" property is set. Signed-off-by: Rahul Singh Signed-off-by: Milan Djokic --- xen/common/device-tree/dom0less-build.c | 45 ++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tr= ee/dom0less-build.c index a877e695ad..970f89ef68 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -332,7 +332,46 @@ static int __init handle_prop_pfdt(struct kernel_info = *kinfo, return ( propoff !=3D -FDT_ERR_NOTFOUND ) ? propoff : 0; } =20 -static int __init scan_pfdt_node(struct kernel_info *kinfo, const void *pf= dt, +#ifdef CONFIG_ARM_VIRTUAL_IOMMU +static int __init modify_pfdt_node(void *pfdt, int nodeoff) +{ + int proplen, i, rc; + const fdt32_t *prop; + fdt32_t *prop_c; + + prop =3D fdt_getprop(pfdt, nodeoff, "iommus", &proplen); + if ( !prop ) + return -EINVAL; + + prop_c =3D xzalloc_bytes(proplen); + if ( !prop_c ) + return -ENOMEM; + + for ( i =3D 0; i < proplen / 8; ++i ) + { + prop_c[i * 2] =3D cpu_to_fdt32(GUEST_PHANDLE_VSMMUV3); + prop_c[i * 2 + 1] =3D prop[i * 2 + 1]; + } + + rc =3D fdt_setprop(pfdt, nodeoff, "iommus", prop_c, proplen); + if ( rc ) + { + dprintk(XENLOG_ERR, "Can't set the iommus property in partial FDT"= ); + goto out; + } + + out: + xfree(prop_c); + return rc; +} +#else +static inline int __init modify_pfdt_node(void *pfdt, int nodeoff) +{ + return -EOPNOTSUPP; +} +#endif + +static int __init scan_pfdt_node(struct kernel_info *kinfo, void *pfdt, int nodeoff, uint32_t address_cells, uint32_t size_cel= ls, bool scan_passthrough_prop) @@ -358,6 +397,10 @@ static int __init scan_pfdt_node(struct kernel_info *k= info, const void *pfdt, node_next =3D fdt_first_subnode(pfdt, nodeoff); while ( node_next > 0 ) { + rc =3D modify_pfdt_node(pfdt, node_next); + if ( rc ) + return rc; + rc =3D scan_pfdt_node(kinfo, pfdt, node_next, address_cells, size_= cells, scan_passthrough_prop); if ( rc ) --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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b=GYVxu0waZRyznJ+TpOCD7oUcJPnMIAauOi2p4/VfnVG7bfhFCS3UJRfjvWpyqnTYYKN2DWy2375WY9ooMMC4/yHI4rEk75YZNqC66wFWV6qAGxqXmSpVZnqflVUp1681tFgGnpNM4fqrxsws7s513/G9pVy2isirSQKzdJ8uljmBtw58JbCUJSbzqcX4aBNoctJY0erFyCIwzFMeml86zPttQ/DASR8jmYzXdtWx905KeAslNMGU3qchgHsape9sGjcsKHqNHApc20MKUhvQA3b8JU0fpnk5A8tGLxSeG8UKsH7GGThxLVY14zgIy6jFUeaUxvoBb+o7scVPvxdx9A== From: Milan Djokic To: "xen-devel@lists.xenproject.org" CC: Milan Djokic , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Rahul Singh , Jan Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= Subject: [PATCH v5 20/22] xen/arm: vIOMMU vSID->pSID mapping layer Thread-Topic: [PATCH v5 20/22] xen/arm: vIOMMU vSID->pSID mapping layer Thread-Index: AQHda7kULYxXGnfVkUmCgWLI1RRaWg== Date: Tue, 3 Nov 2026 17:30:54 +0000 Message-ID: <112c09580e509dd89db411fd61e556d8637582d4.1793726692.git.milan_djokic@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: mx.microsoft.com 1; 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charset="utf-8" Introduce a vIOMMU mapping layer to support passthrough of IOMMU devices attached to different physical IOMMUs, including devices with the same Stream ID. Add a new generic vIOMMU API, viommu_allocate_vsid(), which allocates a guest vSID and maps it to the input pSID and the backing physical SMMU. Once the mapping is established, the guest uses the vSID for stage-1 commands, and Xen translates the vSID to the corresponding pSID before processing the command on the physical SMMU. Implement usage of the new API for dom0less guests. Allocate vSIDs when creating the guest device tree and replace the original pSIDs with vSIDs that are subsequently used by the guest driver. Signed-off-by: Milan Djokic --- xen/arch/arm/include/asm/viommu.h | 12 ++ xen/common/device-tree/dom0less-build.c | 35 +++-- xen/drivers/passthrough/arm/smmu-v3.c | 10 +- xen/drivers/passthrough/arm/viommu.c | 9 ++ xen/drivers/passthrough/arm/vsmmu-v3.c | 184 +++++++++++++++++++++++- xen/include/xen/iommu.h | 6 +- 6 files changed, 242 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/v= iommu.h index 5ae21042f0..3d0eb92655 100644 --- a/xen/arch/arm/include/asm/viommu.h +++ b/xen/arch/arm/include/asm/viommu.h @@ -34,6 +34,16 @@ struct viommu_ops { * Called during domain destruction to free resources used by vIOMMU. */ int (*relinquish_resources)(struct domain *d); + + /* + * Allocate free vSID/vRID for the guest device and establish vID->pID= mapping + * Called during domain device assignment. + * Returns 0 on success and sets vsid argument to newly allocated vSID= /vRID + * mapped to physical ID (id argument). + * Negative error code returned if allocation fails. + */ + int (*allocate_vsid)(struct domain *d, uint32_t id, uint32_t phandle, + uint32_t *vsid); }; =20 struct viommu_desc { @@ -54,6 +64,8 @@ extern struct list_head host_iommu_list; int domain_viommu_init(struct domain *d, uint8_t viommu_type); int viommu_relinquish_resources(struct domain *d); uint8_t viommu_get_type(void); +int viommu_allocate_vsid(struct domain *d, uint32_t id, uint32_t phandle, + uint32_t *vsid); void add_to_host_iommu_list(paddr_t addr, paddr_t size, const struct dt_device_node *node, const void *iommu); diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tr= ee/dom0less-build.c index 970f89ef68..3b2a888698 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -32,6 +32,10 @@ #include #include =20 +#ifdef CONFIG_ARM_VIRTUAL_IOMMU +#include +#endif + #define XENSTORE_PFN_LATE_ALLOC UINT64_MAX =20 static domid_t __initdata xs_domid =3D DOMID_INVALID; @@ -333,11 +337,12 @@ static int __init handle_prop_pfdt(struct kernel_info= *kinfo, } =20 #ifdef CONFIG_ARM_VIRTUAL_IOMMU -static int __init modify_pfdt_node(void *pfdt, int nodeoff) +static int __init modify_pfdt_node(void *pfdt, int nodeoff, struct domain = *d) { int proplen, i, rc; const fdt32_t *prop; fdt32_t *prop_c; + uint32_t psid, phandle, vsid; =20 prop =3D fdt_getprop(pfdt, nodeoff, "iommus", &proplen); if ( !prop ) @@ -347,10 +352,23 @@ static int __init modify_pfdt_node(void *pfdt, int no= deoff) if ( !prop_c ) return -ENOMEM; =20 + /*=20 + * Assign pairs to iommus property and establish + * vSID->pSID mappings + */ for ( i =3D 0; i < proplen / 8; ++i ) { + phandle =3D fdt32_to_cpu(prop[i * 2]); + psid =3D fdt32_to_cpu(prop[i * 2 + 1]); + rc =3D viommu_allocate_vsid(d, psid, phandle, &vsid); + if ( rc ) + { + dprintk(XENLOG_ERR, "(DOMID=3D%u) Failed to allocate vSID for " + "pSID: %u, pIOMMU: %u", d->domain_id, psid, phandle); + goto out; + } prop_c[i * 2] =3D cpu_to_fdt32(GUEST_PHANDLE_VSMMUV3); - prop_c[i * 2 + 1] =3D prop[i * 2 + 1]; + prop_c[i * 2 + 1] =3D cpu_to_fdt32(vsid); } =20 rc =3D fdt_setprop(pfdt, nodeoff, "iommus", prop_c, proplen); @@ -365,7 +383,8 @@ static int __init modify_pfdt_node(void *pfdt, int node= off) return rc; } #else -static inline int __init modify_pfdt_node(void *pfdt, int nodeoff) +static inline int __init modify_pfdt_node(void *pfdt, int nodeoff, + struct domain *d) { return -EOPNOTSUPP; } @@ -374,7 +393,7 @@ static inline int __init modify_pfdt_node(void *pfdt, i= nt nodeoff) static int __init scan_pfdt_node(struct kernel_info *kinfo, void *pfdt, int nodeoff, uint32_t address_cells, uint32_t size_cel= ls, - bool scan_passthrough_prop) + bool scan_passthrough_prop, struct domain= *d) { int rc =3D 0; void *fdt =3D kinfo->fdt; @@ -397,12 +416,12 @@ static int __init scan_pfdt_node(struct kernel_info *= kinfo, void *pfdt, node_next =3D fdt_first_subnode(pfdt, nodeoff); while ( node_next > 0 ) { - rc =3D modify_pfdt_node(pfdt, node_next); + rc =3D modify_pfdt_node(pfdt, node_next, d); if ( rc ) return rc; =20 rc =3D scan_pfdt_node(kinfo, pfdt, node_next, address_cells, size_= cells, - scan_passthrough_prop); + scan_passthrough_prop, d); if ( rc ) return rc; =20 @@ -489,7 +508,7 @@ static int __init domain_handle_dtb_boot_module(struct = domain *d, res =3D scan_pfdt_node(kinfo, pfdt, node_next, DT_ROOT_NODE_ADDR_CELLS_DEFAULT, DT_ROOT_NODE_SIZE_CELLS_DEFAULT, - false); + false, d); if ( res ) goto out; continue; @@ -499,7 +518,7 @@ static int __init domain_handle_dtb_boot_module(struct = domain *d, res =3D scan_pfdt_node(kinfo, pfdt, node_next, DT_ROOT_NODE_ADDR_CELLS_DEFAULT, DT_ROOT_NODE_SIZE_CELLS_DEFAULT, - true); + true, d); if ( res ) goto out; continue; diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index f213b3de12..b0ec004960 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -3103,7 +3103,7 @@ static struct arm_smmu_device *arm_smmu_get_by_dev(co= nst struct device *dev) } =20 static struct iommu_domain *arm_smmu_get_domain_by_sid(struct domain *d, - u32 sid) + u32 sid, const struct arm_smmu_device *smmu) { int i; unsigned long flags; @@ -3119,6 +3119,9 @@ static struct iommu_domain *arm_smmu_get_domain_by_si= d(struct domain *d, list_for_each_entry(io_domain, &xen_domain->contexts, list) { smmu_domain =3D to_smmu_domain(io_domain); =20 + if (smmu_domain->smmu !=3D smmu) + continue; + spin_lock_irqsave(&smmu_domain->devices_lock, flags); list_for_each_entry(master, &smmu_domain->devices, domain_head) { for (i =3D 0; i < master->num_streams; i++) { @@ -3347,7 +3350,8 @@ static void arm_smmu_iommu_xen_domain_teardown(struct= domain *d) } =20 static int arm_smmu_attach_guest_config(struct domain *d, uint32_t sid, - const struct iommu_guest_config *cfg) + const struct iommu_guest_config *cfg, + const struct arm_smmu_device *smmu) { int ret =3D -EINVAL; unsigned long flags; @@ -3357,7 +3361,7 @@ static int arm_smmu_attach_guest_config(struct domain= *d, uint32_t sid, struct iommu_domain *io_domain; =20 spin_lock(&xen_domain->lock); - io_domain =3D arm_smmu_get_domain_by_sid(d, sid); + io_domain =3D arm_smmu_get_domain_by_sid(d, sid, smmu); if (!io_domain) { ret =3D -ENODEV; goto out; diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough= /arm/viommu.c index b4b91ab1cb..e476567b49 100644 --- a/xen/drivers/passthrough/arm/viommu.c +++ b/xen/drivers/passthrough/arm/viommu.c @@ -76,6 +76,15 @@ int viommu_relinquish_resources(struct domain *d) return cur_viommu->ops->relinquish_resources(d); } =20 +int viommu_allocate_vsid(struct domain *d, uint32_t id, uint32_t phandle, + uint32_t *vsid) +{ + if ( !cur_viommu ) + return -ENODEV; + + return cur_viommu->ops->allocate_vsid(d, id, phandle, vsid); +} + uint8_t viommu_get_type(void) { if ( !cur_viommu || host_iommu_list_incomplete || diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou= gh/arm/vsmmu-v3.c index 24588affe9..5d225ccc08 100644 --- a/xen/drivers/passthrough/arm/vsmmu-v3.c +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c @@ -86,6 +86,8 @@ #define smmu_get_ste_s1ctxptr(x) FIELD_PREP(STRTAB_STE_0_S1CTXPTR_MASK,= \ FIELD_GET(STRTAB_STE_0_S1CTXPTR_MASK, = x)) =20 +#define MAX_VSID (1 << SMMU_IDR1_SIDSIZE) + /* event queue entry */ struct arm_smmu_evtq_ent { /* Common fields */ @@ -133,6 +135,14 @@ struct arm_vsmmu_queue { uint8_t max_n_shift; }; =20 +/* vSID->pSID mapping entry */ +struct vsid_entry { + struct list_head entry; + uint32_t vsid; + uint32_t psid; + struct arm_smmu_device *smmu; +}; + struct virt_smmu { struct domain *d; struct list_head viommu_list; @@ -157,6 +167,8 @@ struct virt_smmu { spinlock_t cr2_lock; spinlock_t strtab_cfg_lock; spinlock_t irq_cfg_lock; + spinlock_t vsids_lock; + struct list_head vsids; }; =20 /* Helper functions */ @@ -379,8 +391,31 @@ int arm_vsmmu_handle_evt(struct domain *d, struct devi= ce *dev, uint64_t *evt) } else { + uint32_t sid =3D FIELD_GET(EVTQ_0_SID, evt[0]); + struct vsid_entry *vsid; + bool found =3D false; + smmu =3D list_entry(d->arch.viommu_list.next, struct virt_smmu, viommu_list); + + spin_lock(&smmu->vsids_lock); + + /* Translate pSID->vSID */ + list_for_each_entry(vsid, &smmu->vsids, entry) + { + if ( vsid->psid =3D=3D sid && vsid->smmu->dev =3D=3D dev ) + { + evt[0] &=3D ~EVTQ_0_SID; + evt[0] |=3D FIELD_PREP(EVTQ_0_SID, vsid->vsid); + found =3D true; + break; + } + } + + spin_unlock(&smmu->vsids_lock); + + if ( !found ) + return -ENOENT; } =20 ret =3D arm_vsmmu_write_evtq(smmu, evt); @@ -558,6 +593,71 @@ static int arm_vsmmu_handle_cfgi_ste(struct virt_smmu = *smmu, uint64_t *cmdptr) struct arm_vsmmu_s1_trans_cfg s1_cfg =3D {0}; uint32_t sid =3D smmu_cmd_get_sid(cmdptr[0]); struct iommu_guest_config guest_cfg =3D {0}; + struct arm_smmu_device *phys_smmu =3D NULL; + struct host_iommu *host_iommu; + uint32_t psid; + struct arm_smmu_evtq_ent ent =3D { + .opcode =3D EVT_ID_BAD_STREAMID, + .sid =3D sid, + .c_bad_ste_streamid =3D { + .ssid =3D 0, + .ssv =3D false, + }, + }; + + /* vIOMMU->pIOMMU identity mapped for HW domain */ + if ( domain_use_host_layout(d) ) + { + psid =3D sid; + list_for_each_entry(host_iommu, &host_iommu_list, entry) + { + if ( host_iommu->addr =3D=3D smmu->addr ) + { + phys_smmu =3D (struct arm_smmu_device *) host_iommu->iommu; + break; + } + } + } + else { + struct vsid_entry *vsid_entry; + bool entry_found =3D false; + + spin_lock(&smmu->vsids_lock); + /* vSID out of range or no vSIDs allocated */ + if ( sid >=3D MAX_VSID || list_empty(&smmu->vsids) ) + { + spin_unlock(&smmu->vsids_lock); + arm_vsmmu_send_event(smmu, &ent); + return -EINVAL; + } + + /* get vSID entry corresponding to passed vSID */ + list_for_each_entry(vsid_entry, &smmu->vsids, entry) + if ( vsid_entry->vsid =3D=3D sid ) + { + entry_found =3D true; + break; + } + + /* vSID not mapped */ + if ( !entry_found ) + { + spin_unlock(&smmu->vsids_lock); + arm_vsmmu_send_event(smmu, &ent); + return -EINVAL; + } + + psid =3D vsid_entry->psid; + phys_smmu =3D vsid_entry->smmu; + spin_unlock(&smmu->vsids_lock); + } + + /* vSID mapped to invalid physical SMMU */ + if (!phys_smmu) + { + arm_vsmmu_send_event(smmu, &ent); + return -EINVAL; + } =20 ret =3D arm_vsmmu_find_ste(smmu, sid, ste); if ( ret ) @@ -578,7 +678,7 @@ static int arm_vsmmu_handle_cfgi_ste(struct virt_smmu *= smmu, uint64_t *cmdptr) else guest_cfg.config =3D ARM_SMMU_DOMAIN_S1; =20 - ret =3D hd->platform_ops->attach_guest_config(d, sid, &guest_cfg); + ret =3D hd->platform_ops->attach_guest_config(d, psid, &guest_cfg, phy= s_smmu); if ( ret ) return ret; =20 @@ -1189,6 +1289,13 @@ static int vsmmuv3_init_single(struct domain *d, pad= dr_t addr, smmu->cmdq.ent_size =3D CMDQ_ENT_DWORDS * DWORDS_BYTES; smmu->evtq.ent_size =3D EVTQ_ENT_DWORDS * DWORDS_BYTES; =20 + /* + * vSID->pSID mapping layer is only used in the context of domains that + * are not direct-mapped + */ + if ( !domain_use_host_layout(d) ) + INIT_LIST_HEAD(&smmu->vsids); + spin_lock_init(&smmu->cmd_queue_lock); spin_lock_init(&smmu->evt_queue_lock); spin_lock_init(&smmu->gerror_lock); @@ -1197,6 +1304,7 @@ static int vsmmuv3_init_single(struct domain *d, padd= r_t addr, spin_lock_init(&smmu->cr2_lock); spin_lock_init(&smmu->strtab_cfg_lock); spin_lock_init(&smmu->irq_cfg_lock); + spin_lock_init(&smmu->vsids_lock); =20 ret =3D vgic_reserve_virq(d, virq); if ( !ret ) @@ -1317,8 +1425,16 @@ static int vsmmuv3_relinquish_resources(struct domai= n *d) if ( list_head_is_null(&d->arch.viommu_list) ) return 0; =20 - list_for_each_entry_safe(pos, temp, &d->arch.viommu_list, viommu_list ) + list_for_each_entry_safe(pos, temp, &d->arch.viommu_list, viommu_list) { + struct vsid_entry *vsid, *vsid_temp; + + list_for_each_entry_safe(vsid, vsid_temp, &pos->vsids, entry) + { + list_del(&vsid->entry); + xfree(vsid); + } + =20 list_del(&pos->viommu_list); xfree(pos); } @@ -1326,8 +1442,72 @@ static int vsmmuv3_relinquish_resources(struct domai= n *d) return 0; } =20 +static int vsmmuv3_allocate_vsid(struct domain *d, uint32_t id, + uint32_t phandle, uint32_t *vsid) +{ + uint32_t i =3D 0; + struct virt_smmu *smmu; + struct host_iommu *host_iommu; + struct arm_smmu_device *phys_smmu =3D NULL; + struct vsid_entry *entry; + struct list_head *vsid_head; + + /* vSID->pSID mapping layer not used for direct-mapped domains */ + if ( domain_use_host_layout(d) ) + return -EOPNOTSUPP; + + if ( list_head_is_null(&d->arch.viommu_list) ) + return -ENODEV; + + smmu =3D list_first_entry(&d->arch.viommu_list, struct virt_smmu, viom= mu_list); + + /* + * Find the physical SMMU corresponding to the device-tree phandle. + */ + list_for_each_entry(host_iommu, &host_iommu_list, entry) + { + if ( host_iommu->dt_node->phandle =3D=3D phandle ) + { + phys_smmu =3D (struct arm_smmu_device *) host_iommu->iommu; + break; + } + } + + if ( !phys_smmu ) + return -ENODEV; + + spin_lock(&smmu->vsids_lock); + /* Get first free vSID index */ + list_for_each(vsid_head, &smmu->vsids) + i++; + + /* Max number of vSIDs already allocated? */ + if ( i =3D=3D MAX_VSID ) + { + spin_unlock(&smmu->vsids_lock); + return -ENOMEM; + } + + entry =3D xzalloc(struct vsid_entry); + if ( !entry ) + { + spin_unlock(&smmu->vsids_lock); + return -ENOMEM; + } + + /* Establish vSID->pSID mapping */ + entry->vsid =3D i; + entry->psid =3D id; + entry->smmu =3D phys_smmu; + *vsid =3D entry->vsid; + list_add_tail(&entry->entry, &smmu->vsids); + spin_unlock(&smmu->vsids_lock); + return 0; +} + static const struct viommu_ops vsmmuv3_ops =3D { .domain_init =3D domain_vsmmuv3_init, + .allocate_vsid =3D vsmmuv3_allocate_vsid, .relinquish_resources =3D vsmmuv3_relinquish_resources, }; =20 diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index 253f8bb6cb..c94ee4f08e 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -312,7 +312,10 @@ static inline int iommu_add_dt_pci_sideband_ids(struct= pci_dev *pdev) #endif /* HAS_DEVICE_TREE_DISCOVERY */ =20 struct page_info; +#ifdef CONFIG_ARM struct iommu_guest_config; +struct arm_smmu_device; +#endif =20 /* * Any non-zero value returned from callbacks of this type will cause the @@ -391,7 +394,8 @@ struct iommu_ops { =20 #ifdef CONFIG_ARM int (*attach_guest_config)(struct domain *d, uint32_t sid, - const struct iommu_guest_config *cfg); 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charset="utf-8" For guests created via the control domain (xl, Zephyr xenlib), a partial device tree is parsed and loaded on the control domain side. SIDs in the guest device tree have to be replaced with virtual SIDs that are mapped to the corresponding physical SIDs. To do this, the control domain requests Xen to allocate a new vSID and map it to the original pSID for each IOMMU stream ID associated with a guest device. Introduce a new domctl command (XEN_DOMCTL_viommu_allocate_vid) that allows the control domain to request a new vSID mapping and replace the original pSID with the allocated vSID in the guest device tree. Implement vSID allocation in libxl using this interface for devices configured behind an IOMMU. Signed-off-by: Milan Djokic --- tools/include/xenctrl.h | 13 ++++ tools/libs/ctrl/xc_domain.c | 25 +++++++ tools/libs/light/libxl_arm.c | 112 +++++++++++++++++++++++++--- xen/arch/arm/domctl.c | 38 ++++++++++ xen/include/public/domctl.h | 22 ++++++ xen/xsm/flask/hooks.c | 4 + xen/xsm/flask/policy/access_vectors | 2 + 7 files changed, 207 insertions(+), 9 deletions(-) diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h index 6f4ea7ca62..7075e54a27 100644 --- a/tools/include/xenctrl.h +++ b/tools/include/xenctrl.h @@ -2670,6 +2670,19 @@ int xc_domain_set_llc_colors(xc_interface *xch, uint= 32_t domid, const uint32_t *llc_colors, uint32_t num_llc_colors); =20 +/* + * Allocate guest IOMMU vSID and establish its mapping to pSID. + * It can only be used on domain DT creation. + * Currently used for ARM only, possibly for RISC-V in the + * future. Function has no effect for x86. + */ +int xc_domain_viommu_allocate_vsid_range(xc_interface *xch, + uint32_t domid, + uint16_t nr_sids, + uint32_t first_psid, + uint32_t phandle, + uint32_t *first_vsid); + #if defined(__arm__) || defined(__aarch64__) int xc_dt_overlay(xc_interface *xch, void *overlay_fdt, uint32_t overlay_fdt_size, uint8_t overlay_op); diff --git a/tools/libs/ctrl/xc_domain.c b/tools/libs/ctrl/xc_domain.c index 94cfab0fa1..0bd3e45fbd 100644 --- a/tools/libs/ctrl/xc_domain.c +++ b/tools/libs/ctrl/xc_domain.c @@ -2222,6 +2222,31 @@ out: =20 return ret; } + +int xc_domain_viommu_allocate_vsid_range(xc_interface *xch, + uint32_t domid, + uint16_t nr_sids, + uint32_t first_psid, + uint32_t phandle, + uint32_t *first_vsid) +{ + int err; + struct xen_domctl domctl =3D {}; + + domctl.cmd =3D XEN_DOMCTL_viommu_alloc_vsid_range; + domctl.domain =3D domid; + domctl.u.viommu_alloc_vsid_range.first_psid =3D first_psid; + domctl.u.viommu_alloc_vsid_range.phandle =3D phandle; + domctl.u.viommu_alloc_vsid_range.nr_sids =3D nr_sids; + + if ( (err =3D do_domctl(xch, &domctl)) !=3D 0 ) + return err; + + *first_vsid =3D domctl.u.viommu_alloc_vsid_range.first_vsid; + + return 0; +} + /* * Local variables: * mode: C diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c index 0dc3789d08..c1e41ed7fe 100644 --- a/tools/libs/light/libxl_arm.c +++ b/tools/libs/light/libxl_arm.c @@ -1342,11 +1342,101 @@ static int copy_partial_fdt(libxl__gc *gc, void *f= dt, void *pfdt) return 0; } =20 -static int modify_partial_fdt(libxl__gc *gc, void *pfdt) +/* + * Store virtualized 'iommus' properties for every node attached to IOMMU + * and passthroughed to guest. + * Used as a lookup table for mapping -> + */ +struct viommu_stream { + XEN_LIST_ENTRY(struct viommu_stream) entry; + char path[128]; /* DT path, stable across resizes */ + uint32_t domid; + fdt32_t *iommus; /* fully virtualized iommus property */ +}; + +static XEN_LIST_HEAD(, struct viommu_stream) viommu_stream_list; + +/* + * Helper function which creates mapping of dt node to + * to virtualized 'iommus' property + * Mappings stored in a global 'viommu_stream_list' to + * make it reusable for every fdt resize + */ +static int viommu_get_stream(libxl__gc *gc, + uint32_t domid, + const fdt32_t *prop, + int proplen, + const char* path, fdt32_t **iommus) { - int nodeoff, proplen, i, r; + int i, r; + uint32_t vsid, psid, phandle; + struct viommu_stream *viommu_stream; + + /* Lookup if stream for target device is already allocated */ + XEN_LIST_FOREACH(viommu_stream, &viommu_stream_list, entry) + { + if (!strcmp(viommu_stream->path, path) && + viommu_stream->domid =3D=3D domid) { + *iommus =3D viommu_stream->iommus; + return 0; + } + } + + /* Allocate new viommu stream */ + viommu_stream =3D malloc(sizeof(struct viommu_stream)); + if (!viommu_stream) + return ERROR_NOMEM; + memset(viommu_stream, 0, sizeof(struct viommu_stream)); + viommu_stream->iommus =3D malloc(proplen); + if (!viommu_stream->iommus) { + free(viommu_stream); + return ERROR_NOMEM; + } + memset(viommu_stream->iommus, 0, proplen); + + LOG(DEBUG, "Creating vIOMMU stream for device %s", + path); + + /* + * Virtualize device "iommus" property + * (replace pIOMMU with vIOMMU phandle and pSIDs with mapped vSIDs) + */ + for (i =3D 0; i < proplen / 8; ++i) { + /* Allocate new vSID mapped to pSID and physical IOMMU */ + phandle =3D fdt32_to_cpu(prop[i * 2]); + psid =3D fdt32_to_cpu(prop[i * 2 + 1]); + r =3D xc_domain_viommu_allocate_vsid_range(CTX->xch, domid, 1, psi= d, + phandle, &vsid); + if (r) { + LOG(ERROR, "Can't allocate new vSID/vRID for guest IOMMU devic= e"); + free(viommu_stream->iommus); + free(viommu_stream); + return r; + } + viommu_stream->iommus[i * 2] =3D cpu_to_fdt32(GUEST_PHANDLE_VSMMUV= 3); + viommu_stream->iommus[i * 2 + 1] =3D cpu_to_fdt32(vsid); + LOG(DEBUG, "Mapped vSID: %u to pSID: %u", vsid, psid); + } + + strcpy(viommu_stream->path, path); + viommu_stream->domid =3D domid; + *iommus =3D viommu_stream->iommus; + + XEN_LIST_INSERT_HEAD(&viommu_stream_list, viommu_stream, entry); + + return 0; +} + +/* + * Used to update partial fdt when vIOMMU is enabled + * Maps dt properties of IOMMU devices to virtual IOMMU + */ +static int viommu_modify_partial_fdt(libxl__gc *gc, void *pfdt, uint32_t d= omid) +{ + int nodeoff, proplen, r; const fdt32_t *prop; fdt32_t *prop_c; + char path[128]; =20 nodeoff =3D fdt_path_offset(pfdt, "/passthrough"); if (nodeoff < 0) @@ -1360,11 +1450,16 @@ static int modify_partial_fdt(libxl__gc *gc, void *= pfdt) if (!prop) continue; =20 - prop_c =3D libxl__zalloc(gc, proplen); + r =3D fdt_get_path(pfdt, nodeoff, path, sizeof(path)); + if ( r < 0 ) { + LOG(ERROR, "Can't get passthrough node path"); + return r; + } =20 - for (i =3D 0; i < proplen / 8; ++i) { - prop_c[i * 2] =3D cpu_to_fdt32(GUEST_PHANDLE_VSMMUV3); - prop_c[i * 2 + 1] =3D prop[i * 2 + 1]; + r =3D viommu_get_stream(gc, domid, prop, proplen, path, &prop_c); + if (r) { + LOG(ERROR, "Can't get viommu stream"); + return r; } =20 r =3D fdt_setprop(pfdt, nodeoff, "iommus", prop_c, proplen); @@ -1376,7 +1471,6 @@ static int modify_partial_fdt(libxl__gc *gc, void *pf= dt) =20 return 0; } - #else =20 static int check_partial_fdt(libxl__gc *gc, void *fdt, size_t size) @@ -1395,7 +1489,7 @@ static int copy_partial_fdt(libxl__gc *gc, void *fdt,= void *pfdt) return -FDT_ERR_INTERNAL; } =20 -static int modify_partial_fdt(libxl__gc *gc, void *pfdt) +static int viommu_modify_partial_fdt(libxl__gc *gc, void *pfdt, uint32_t d= omid) { LOG(ERROR, "partial device tree not supported"); =20 @@ -1527,7 +1621,7 @@ next_resize: if (info->arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMMUV3) { FDT( make_vsmmuv3_node(gc, fdt, ainfo, dom) ); if (pfdt) - FDT( modify_partial_fdt(gc, pfdt) ); + FDT( viommu_modify_partial_fdt(gc, pfdt, dom->guest_domid)= ); } =20 for (i =3D 0; i < d_config->num_disks; i++) { diff --git a/xen/arch/arm/domctl.c b/xen/arch/arm/domctl.c index b76af56fad..40f1582891 100644 --- a/xen/arch/arm/domctl.c +++ b/xen/arch/arm/domctl.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 void arch_get_domain_info(const struct domain *d, struct xen_domctl_getdomaininfo *info) @@ -186,6 +187,43 @@ long arch_do_domctl(struct xen_domctl *domctl, struct = domain *d, } case XEN_DOMCTL_dt_overlay: return dt_overlay_domctl(d, &domctl->u.dt_overlay); + +#ifdef CONFIG_ARM_VIRTUAL_IOMMU + case XEN_DOMCTL_viommu_alloc_vsid_range: + { + int rc =3D 0; + uint16_t i; + uint32_t vsid; + struct xen_domctl_viommu_alloc_vsid_range *vsid_range =3D + &domctl->u.viommu_alloc_vsid_range; + + if ( vsid_range->pad || vsid_range->nr_sids =3D=3D 0 ) + return -EINVAL; + + for ( i =3D 0; i < vsid_range->nr_sids; i++ ) + { + rc =3D viommu_allocate_vsid(d, vsid_range->first_psid + + i, + vsid_range->phandle, + &vsid); + if( rc ) + return rc; + } + + if ( !rc ) + { + /* Calculate first vSID from allocated range */ + vsid_range->first_vsid =3D vsid - + vsid_range->nr_sids + 1; + rc =3D copy_to_guest(u_domctl, domctl, 1); + if ( rc ) + rc =3D -EFAULT; + } + + return rc; + } +#endif + default: return subarch_do_domctl(domctl, d, u_domctl); } diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 4ca8a2d7ca..739a0cd68a 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -1279,6 +1279,26 @@ struct xen_domctl_get_domain_state { uint64_t unique_id; /* Unique domain identifier. */ }; =20 +/* + * XEN_DOMCTL_viommu_alloc_vsid_range + * + * Allocate guest vSID range and + * establish pSID->vSID mapping for target range and physical IOMMU (phand= le). + * Allocated range is continous + */ +struct xen_domctl_viommu_alloc_vsid_range { + /* IN: Range first pSID */ + uint32_t first_psid; + /* IN: Physical IOMMU phandle behind which the target device streams a= re configured */ + uint32_t phandle; + /* IN: Number of vSIDs to allocate */ + uint16_t nr_sids; + /* padding, must be 0 */ + uint16_t pad; + /* OUT: Mapped range first vSID */ + uint32_t first_vsid; +}; + struct xen_domctl { /* Stable domctl ops: interface_version is required to be 0. */ uint32_t cmd; @@ -1371,6 +1391,7 @@ struct xen_domctl { #define XEN_DOMCTL_gsi_permission 88 #define XEN_DOMCTL_set_llc_colors 89 #define XEN_DOMCTL_get_domain_state 90 /* stable interface */ +#define XEN_DOMCTL_viommu_alloc_vsid_range 91 #define XEN_DOMCTL_gdbsx_guestmemio 1000 #define XEN_DOMCTL_gdbsx_pausevcpu 1001 #define XEN_DOMCTL_gdbsx_unpausevcpu 1002 @@ -1439,6 +1460,7 @@ struct xen_domctl { #endif struct xen_domctl_set_llc_colors set_llc_colors; struct xen_domctl_get_domain_state get_domain_state; + struct xen_domctl_viommu_alloc_vsid_range viommu_alloc_vsid_range; uint8_t pad[128]; } u; }; diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index d65ba0aeae..6321b4308b 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -881,6 +881,10 @@ static int cf_check flask_domctl(struct domain *d, str= uct xen_domctl *op) case XEN_DOMCTL_set_llc_colors: return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SET_LLC_COLO= RS); =20 + case XEN_DOMCTL_viommu_alloc_vsid_range: + return current_has_perm(d, SECCLASS_DOMAIN2, + DOMAIN2__VIOMMU_ALLOC_VSID_RANGE); + default: return avc_unknown_permission("domctl", op->cmd); } diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/acc= ess_vectors index bbb9c117ec..35acbefab2 100644 --- a/xen/xsm/flask/policy/access_vectors +++ b/xen/xsm/flask/policy/access_vectors @@ -253,6 +253,8 @@ class domain2 set_llc_colors # XEN_DOMCTL_get_domain_state get_domain_state +# XEN_DOMCTL_viommu_alloc_vsid_range + viommu_alloc_vsid_range } =20 # Similar to class domain, but primarily contains domctls related to HVM d= omains --=20 2.43.0 From nobody Thu Nov 5 07:29:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; 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charset="utf-8" This document outlines the design of the emulated IOMMU, including supported features, security considerations and future improvements. Signed-off-by: Milan Djokic --- docs/designs/arm-viommu.rst | 530 ++++++++++++++++++++++++++++++++++++ 1 file changed, 530 insertions(+) create mode 100644 docs/designs/arm-viommu.rst diff --git a/docs/designs/arm-viommu.rst b/docs/designs/arm-viommu.rst new file mode 100644 index 0000000000..de7bbf6998 --- /dev/null +++ b/docs/designs/arm-viommu.rst @@ -0,0 +1,530 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D +Design Proposal: Add SMMUv3 Stage-1 Support for XEN Guests +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D + +:Author: Milan Djokic +:Date: 2026-02-13 +:Status: Draft + +Introduction +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The SMMUv3 supports two stages of translation. Each stage of translation=20 +can be +independently enabled. An incoming address is logically translated from=20 +VA to +IPA in stage 1, then the IPA is input to stage 2 which translates the IPA = to +the output PA. Stage 1 translation support is required to provide=20 +isolation between different +devices within OS. XEN already supports Stage 2 translation but there is no +support for Stage 1 translation. +This design proposal outlines the introduction of Stage-1 SMMUv3 support=20 +in Xen for ARM guests. + +Motivation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +ARM systems utilizing SMMUv3 require stage-1 address translation to=20 +ensure secure DMA and +guest managed I/O memory mappings. +With stage-1 enabled, guest manages IOVA to IPA mappings through its own=20 +IOMMU driver. + +This feature enables: + +- Stage-1 translation for the guest domain +- Device passthrough with per-device I/O address space + +Design Overview +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +These changes provide emulated SMMUv3 support: + +- **SMMUv3 Stage-1 Translation**: stage-1 and nested translation support + in SMMUv3 driver. +- **vIOMMU Abstraction**: Virtual IOMMU framework for guest stage-1 + handling. +- **Register/Command Emulation**: SMMUv3 register emulation and command + queue handling. +- **Device Tree Extensions**: Adds `iommus` and virtual SMMUv3 nodes to + device trees for dom0 and dom0less scenarios. +- **Build Configuration**: Introduces a Kconfig arguments + (CONFIG_ARM_VIRTUAL_IOMMU, CONFIG_VIRTUAL_ARM_SMMU_V3) for build-time + enablement. + +Depending on the domain type, the emulated IOMMU model is the following: + +- For the hardware domain, the host layout is re-used. The number of expos= ed + IOMMUs to hardware domain is equal to number of physical IOMMUs + present (1-1 mapping). +- For non-hardware domain, a single vIOMMU device is exposed to the guest = and + mapped to one or more physical IOMMUs through a Xen-managed translation = layer + +The vIOMMU feature provides a generic framework together with a backend +implementation specific to the target IOMMU type. The backend is responsib= le +for implementing the hardware-specific data structures and command handling +logic (currently only SMMUv3 is supported). + +This modular design allows the stage-1 support to be reused +for other IOMMU architectures in the future. + +With stage-1 support, Xen supports three SMMUv3 translation models: + +1. Stage-2-only: Used when the SMMU hardware does not support stage-1 + translation or when nested translation is disabled. +2. Stage-1-only: Used when the SMMU hardware supports stage-1 but not stag= e-2 + translation. This is a special mode restricted to trusted, direct-mapped + guests. +3. Nested: The default mode when the SMMU hardware supports both stage-1 a= nd + stage-2 translation and nesting is enabled. + +vIOMMU architecture +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Responsibilities: + +Guest: + - Configures stage-1 via vIOMMU commands. + - Handles stage-1 faults received from Xen. + +Xen: + - Emulates the IOMMU interface (registers, commands, events). + - Provides vSID->pSID mappings. + - Programs stage-1/stage-2 configuration in the physical IOMMU. + - Propagate stage-1 faults to guest. + +The stage-1 context is shared between streams assigned to the same device. +This follows the Linux SMMUv3 driver model, where the IOMMU domain is asso= ciated +with the master/device, while the individual SIDs are represented by separ= ate +STEs pointing to the same translation context. This is considered sufficie= nt for +the current SMMUv3 driver model, although the SMMUv3 architecture does not +forbid having separate translation contexts for different SIDs. + +vIOMMU commands and faults are transmitted between guest and Xen via +command and event queues (one command/event queue created per guest). + +vIOMMU command Flow: + +:: + + Guest: + smmu_cmd(vSID, IOVA -> IPA) + + Xen: + trap MMIO read/write + translate vSID->pSID + store stage-1 state + program pIOMMU for (pSID, IPA -> PA) + +All hardware programming of the physical IOMMU is performed exclusively by= Xen. + +vIOMMU Stage-1 fault handling flow: + +:: + + Xen: + receives stage-1 fault + triggers vIOMMU callback + injects virtual fault + + Guest: + receives and handles fault + +Register access +--------------- + +Guest accesses to SMMUV3 registers are trapped via MMIO regions. vIOMMU em= ulates +a subset of SMMUv3 registers relevant to currently supported features. +Unsupported registers are handled as RAZ (Read-As-Zero) and WI (Write-Igno= red) +for the register read and write operations, respectively. + +vSMMUv3 is a partially emulated resource for the guest domain. Some +feature register bits (SMMU_IDR) are reflecting what the underlying HW act= ually +support while the rest is preset in the emulation layer to limit guest from +using features which are not supported by the emulation. Also, implementer +identification register is fully emulated, providing generic ARM implement= er +ID values, to avoid activating errata/quirk paths in the guest SMMUv3 driv= er. + +Supported SMMUv3 Commands +------------------------- + +The vIOMMU implementation currently supports a subset of the SMMUv3 +architectural command set required for stage-1 translation management. + +Commands are submitted by the guest through the virtual Command Queue +(CMDQ) and consumed by Xen, which translates them into operations on the +physical SMMUv3 hardware. + +Some commands are fully handled by the emulation layer, while others are +currently treated as architectural no-ops because the required behavior +is either implicitly guaranteed by Xen or not yet modeled explicitly. + +Emulation handled commands: + +- CMD_CFGI_STE +- CMD_TLBI_NH_ASID +- CMD_TLBI_NSNH_ALL +- CMD_TLBI_NH_VA + +No-op/Implicitly handled commands: + +- CMD_SYNC +- CMD_PREFETCH_CFG +- CMD_CFGI_CD +- CMD_CFGI_CD_ALL +- CMD_CFGI_ALL + +Command Handling Model +---------------------- + +The guest submits commands through the virtual CMDQ interface. + +Xen: + +- Validates commands +- Translates virtual identifiers (vSID->pSID) where required +- Programs the physical SMMU +- Performs synchronization + +The physical SMMU executes the resulting invalidation or configuration +operations. + +Unsupported Commands +-------------------- + +Commands associated with currently unsupported architectural features +are not implemented. + +This includes commands related to: + +- PRI +- ATS +- Address/Range TLB invalidation (currently, all TLBI commands perform com= plete + domain TLB invalidation) +- Advanced stall/retry semantics +- CD runtime update/sync + +vSID Mapping Layer +------------------ + +Each non-hardware domain-visible Stream ID (vSID) is mapped by Xen to a ph= ysical +Stream ID (pSID). The mapping is maintained per-domain. The allocation pol= icy +guarantees vSID uniqueness within a domain while allowing reuse of pSIDs f= or +different pIOMMUs. + +* Platform devices receive individually allocated vSIDs. +* PCI devices receive a contiguous vSID range derived from RID space. + + +Supported Device Model +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Currently, the vIOMMU framework supports only devices described via the +Device Tree (DT) model. This includes platform devices and basic PCI +devices support instantiated through the vPCI DT node. ACPI-described +devices are not supported. + +Guest assigned platform devices are mapped via `iommus` property: + +:: + + <&pIOMMU pSID> -> <&vIOMMU vSID> + +PCI devices use RID-based mapping via the root complex `iommu-map`: + +:: + + + +PCI Topology Assumptions and Constraints: + +- RID space must be contiguous +- Pre-defined continuous pSID space (0-0x1000) +- No runtime PCI reconfiguration +- Single root complex assumed +- Mapping is fixed at guest DT construction + +Constraints for PCI devices will be addressed as part of the future work on +this feature. + +Security Considerations +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Stage-1 translation provides isolation between guest devices by +enforcing a per-device I/O address space, preventing unauthorized DMA. +With the introduction of emulated IOMMU, additional protection +mechanisms are required to minimize security risks. + +1. Observation: +--------------- +Support for Stage-1 translation in SMMUv3 introduces new data structures=20 +(`s1_cfg` alongside `s2_cfg`) +and logic to write both Stage-1 and Stage-2 entries in the Stream Table=20 +Entry (STE), including an `abort` +field to handle partial configuration states. + +**Risk:** +Without proper handling, a partially applied configuration +might leave guest DMA mappings in an inconsistent state, potentially +enabling unauthorized access or causing cross-domain interference. + +**Mitigation:** *(Handled by design)* +This feature introduces logic that writes both `s1_cfg` and `s2_cfg` to +STE and manages the `abort` field - only considering +configuration if fully attached. This ensures incomplete or invalid +device configurations are safely ignored by the hypervisor. + +2. Observation: +--------------- +Guests can now invalidate Stage-1 caches; invalidation needs forwarding +to SMMUv3 hardware to maintain coherence. + +**Risk:** +Failing to propagate cache invalidation could allow stale mappings, +enabling access to old mappings and possibly +data leakage or misrouting between devices assigned to the same guest. + +**Mitigation:** +The guest must issue appropriate invalidation commands whenever +its stage-1 I/O mappings are modified to ensure that translation caches +remain coherent. + +3. Observation: +--------------- +Introducing optional per-guest enabled features (`viommu` argument in xl=20 +guest config) means some guests +may opt-out. + +**Risk:** +Guests without vIOMMU enabled (stage-2 only) could potentially dominate +access to the physical command and event queues, since they bypass the +emulation layer and processing is faster comparing to vIOMMU-enabled guest= s. + +**Mitigation:** +Audit the impact of emulation overhead effect on IOMMU processing fairness +in a multi-guest environment. +Consider enabling/disabling stage-1 on a system level, instead of per-doma= in. + +4. Observation: +--------------- +Guests have the ability to issue Stage-1 IOMMU commands like cache=20 +invalidation, stream table entries +configuration, etc. An adversarial guest may issue a high volume of=20 +commands in rapid succession. + +**Risk:** +Excessive commands requests can cause high hypervisor CPU consumption=20 +and disrupt scheduling, +leading to degraded system responsiveness and potential=20 +denial-of-service scenarios. + +**Mitigation:** + +- Implement vIOMMU commands execution restart and continuation support: + + - Introduce processing budget with only a limited amount of commands + handled per invocation. + - If additional commands remain pending after the budget is exhausted, + defer further processing and resume it asynchronously, e.g. via a + per-domain tasklet. + +- Batch multiple commands of same type to reduce emulation overhead: + + - Inspect the command queue and group commands that can be processed + together (e.g. multiple successive invalidation requests or STE + updates for the same SID). + - Execute the entire batch in one go, reducing repeated accesses to + guest memory and emulation overhead per command. + - This reduces CPU time spent in the vIOMMU command processing loop. + The optimization is applicable only when consecutive commands of the + same type operate on the same SID/context. + +5. Observation: +--------------- +Some guest commands issued towards vIOMMU are propagated to pIOMMU=20 +command queue (e.g. TLB invalidate). + +**Risk:** +Excessive commands requests from abusive guest can cause flooding of=20 +physical IOMMU command queue, +leading to degraded pIOMMU responsiveness on commands issued from other=20 +guests. + +**Mitigation:** + +- Batch commands that are propagated to the pIOMMU command queue and + implement batch execution pause/continuation. + Rely on the same mechanisms as in the previous observation + (command continuation and batching of pIOMMU-related commands of the same + type and context). +- If possible, implement domain penalization by adding a per-domain budget + for vIOMMU/pIOMMU usage: + + - Apply per-domain dynamic budgeting of allowed IOMMU commands to + execute per invocation, reducing the budget for guests with + excessive command requests over a longer period of time + - Combine with command continuation mechanism + +6. Observation: +--------------- +The vIOMMU feature includes an event queue used to forward IOMMU events +to the guest (e.g. translation faults, invalid Stream IDs, permission erro= rs). +A malicious guest may misconfigure its IOMMU state or intentionally trigger +faults at a high rate. + +**Risk:** +Occurrence of IOMMU events with high frequency can cause Xen to flood the +event queue and disrupt scheduling with +high hypervisor CPU load for events handling. + +**Mitigation:** + +- Implement fail-safe state by disabling events forwarding when faults=20 + are occurred with high frequency and + not processed by guest: + + - Introduce a per-domain pending event counter. + - Stop forwarding events to the guest once the number of unprocessed + events reaches a predefined threshold. + +- Consider disabling the emulated event queue for untrusted guests. +- Note that this risk is more general and may also apply to stage-2-only + guests. This section addresses mitigations in the emulated IOMMU layer + only. Mitigation of physical event queue flooding should also be conside= red + in the target pIOMMU driver. + +7. Observation: +--------------- +vIOMMU `CFGI_STE` commands can trigger serialized STE programming on the p= IOMMU +while `xen_domain->lock`, `devices_lock` and `cmd_queue_lock` are held, wi= th +local interrupts disabled. STE programming may issue multiple polling CMD_= SYNC +operations, each with a one-second timeout. + +**Risk:** +An abusive guest can issue CFGI_STE commands that cause multiple CMD_SYNC +operations to reach their polling timeout. This can keep a pCPU with inter= rupts +disabled for a significant period of time, delaying interrupt handling and +potentially degrading the responsiveness of Xen and other domains running = on +the same pCPU. + +**Mitigation:** + +- Implement pinning or otherwise maintaining the lifetime of the required + objects before releasing the relevant locks, allowing the + serialized STE programming to be performed without holding locks and with + local interrupts enabled. +- Consider redesigning the SMMUv3 command processing and locking model in + future improvements to avoid performing potentially long-running pIOMMU + operations while holding locks and with local interrupts disabled. + +8. Observation: +--------------- +The vIOMMU feature supports stage-1-only translation for SMMU hardware +that does not support stage-2 translation. + +**Risk:** +When stage-1-only mode is enabled for an untrusted guest, there is no +stage-2 translation to restrict device DMA accesses to the memory assigned +to that guest. Consequently, a malicious guest could configure stage-1 +mappings to access arbitrary physical memory, potentially compromising +isolation and accessing memory or configuration belonging to other domains. + +**Mitigation:** + +- Xen allows stage-1-only mode exclusively for direct-mapped domains. +- The integrator must ensure that only trusted guests are configured as + direct-mapped domains with IOMMU access enabled. + +Performance Impact +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +With iommu stage-1 and nested translation inclusion, performance=20 +overhead is introduced comparing to existing, +stage-2 only usage in Xen. Once mappings are established, translations=20 +should not introduce significant overhead. +Emulated paths may introduce moderate overhead, primarily affecting=20 +device initialization and event/command handling. +Testing is performed on Renesas R-Car platform. +Performance is mostly impacted by emulated vIOMMU operations, results=20 +shown in the following table. + ++-------------------------------+---------------------------------+ +| vIOMMU Operation | Execution time in guest | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| Reg read | median: 645ns, worst-case: 2us | ++-------------------------------+---------------------------------+ +| Reg write | median: 630ns, worst-case: 1us | ++-------------------------------+---------------------------------+ +| Invalidate TLB | median: 2us, worst-case: 10us | ++-------------------------------+---------------------------------+ +| Invalidate STE | median: 5us worst_case: 100us | ++-------------------------------+---------------------------------+ + +With vIOMMU exposed to guest, guest OS has to initialize IOMMU device +and configure stage-1 mappings for the devices +attached to it. +Following table shows initialization stages which impact stage-1 enabled=20 +guest boot time and compares it with +stage-1 disabled guest. + +NOTE: Device probe execution time varies depending on device complexity. +A USB host controller was selected as the test device in this case. + ++---------------------+-----------------------+------------------------+ +| Stage | Stage-1 Enabled Guest | Stage-1 Disabled Guest | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| IOMMU Init | ~10ms | / | ++---------------------+-----------------------+------------------------+ +| Dev Attach / Mapping| ~100ms | ~90ms | ++---------------------+-----------------------+------------------------+ + +For devices configured with dynamic DMA mappings, DMA allocate/map/unmap=20 +operations performance is +also impacted on stage-1 enabled guests. +Dynamic DMA mapping operation trigger emulated IOMMU functions like mmio=20 +write/read and TLB invalidations. + ++---------------+---------------------------+--------------------------+ +| DMA Op | Stage-1 Enabled Guest | Stage-1 Disabled Guest | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| dma_alloc | median: 20us, worst: 5ms | median: 8us, worst: 60us | ++---------------+---------------------------+--------------------------+ +| dma_free | median: 500us, worst: 10ms| median: 6us, worst: 30us | ++---------------+---------------------------+--------------------------+ +| dma_map | median: 12us, worst: 60us | median: 3us, worst: 20us | ++---------------+---------------------------+--------------------------+ +| dma_unmap | median: 400us, worst: 5ms | median: 5us, worst: 20us | ++---------------+---------------------------+--------------------------+ + +Testing +=3D=3D=3D=3D=3D=3D=3D + +- QEMU-based ARM system tests for Stage-1 translation. +- Actual hardware validation to ensure compatibility with real SMMUv3=20 + implementations. +- Unit/Functional tests validating correct translations (not implemented). + +Migration and Compatibility +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + +This optional feature defaults to disabled (CONFIG_ARM_VIRTUAL_IOMMU=3Dn, +CONFIG_VIRTUAL_ARM_SMMU_V3=3Dn). + +Future improvements +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +- Implement the proposed mitigations to address security risks that are=20 + not covered by the current design + (events batching, commands execution continuation) +- PCI support +- Support for other IOMMU HW (Renesas, RISC-V, etc.) + +References +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +- Original feature implemented by Rahul Singh: + +https://patchwork.kernel.org/project/xen-devel/cover/cover.1669888522.git.= rahul.singh@arm.com/=20 + +- SMMUv3 architecture documentation +- Existing vIOMMU code patterns (KVM, QEMU) \ No newline at end of file --=20 2.43.0