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charset="utf-8" The boot CPU pending table must use the memory attributes selected by ITS quirks. gicv3_lpi_init_host_lpis() is therefore called after gicv3_its_init(). However, gicv3_its_init() also programs and enables each ITS before host LPI state is allocated. No ITS commands are submitted at that point, but this ordering relies on that implementation detail. Split per-ITS initialization into preparation and activation phases. First map and disable every ITS and collect its quirks. Then initialize host LPI state. Only after that, allocate and program the ITS tables and command queue, and enable each ITS. The subsequent gicv3_cpu_init() sequence remains unchanged: it programs the Redistributor LPI tables, enables LPIs, and then submits the first MAPC and SYNC commands. Suggested-by: Julien Grall Signed-off-by: Mykola Kvach --- Changes in v3: - New patch implementing the post-4.22 initialization order discussed during review of the ordering fix. Link: https://patchew.org/Xen/341edd8de63dcd84ccc6e7b6c03e9e8fc7105184.1781= 847061.git.mykola._5Fkvach@epam.com/ --- xen/arch/arm/gic-v3-its.c | 32 ++++++++++++++++++++++----- xen/arch/arm/gic-v3.c | 15 ++----------- xen/arch/arm/include/asm/gic_v3_its.h | 4 ++-- 3 files changed, 31 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 325835b0ad..972825bf06 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -549,10 +550,9 @@ static int gicv3_disable_its(struct host_its *hw_its) return -ETIMEDOUT; } =20 -static int gicv3_its_init_single_its(struct host_its *hw_its) +static int __init gicv3_its_prepare_single_its(struct host_its *hw_its) { - uint64_t reg; - int i, ret; + int ret; =20 hw_its->its_base =3D ioremap_nocache(hw_its->addr, hw_its->size); if ( !hw_its->its_base ) @@ -564,6 +564,14 @@ static int gicv3_its_init_single_its(struct host_its *= hw_its) =20 gicv3_its_enable_quirks(hw_its); =20 + return 0; +} + +static int __init gicv3_its_init_single_its(struct host_its *hw_its) +{ + uint64_t reg; + int i, ret; + reg =3D readq_relaxed(hw_its->its_base + GITS_TYPER); hw_its->devid_bits =3D GITS_TYPER_DEVICE_ID_BITS(reg); hw_its->evid_bits =3D GITS_TYPER_EVENT_ID_BITS(reg); @@ -1189,7 +1197,7 @@ static void gicv3_its_acpi_init(void) =20 #endif =20 -int gicv3_its_init(void) +int __init gicv3_its_init(unsigned int host_lpi_bits) { struct host_its *hw_its; int ret; @@ -1201,13 +1209,27 @@ int gicv3_its_init(void) =20 list_for_each_entry(hw_its, &host_its_list, entry) { - ret =3D gicv3_its_init_single_its(hw_its); + ret =3D gicv3_its_prepare_single_its(hw_its); if ( ret ) return ret; } =20 gicv3_its_validate_quirks(); =20 + if ( list_empty(&host_its_list) ) + return 0; + + ret =3D gicv3_lpi_init_host_lpis(host_lpi_bits); + if ( ret ) + return ret; + + list_for_each_entry(hw_its, &host_its_list, entry) + { + ret =3D gicv3_its_init_single_its(hw_its); + if ( ret ) + return ret; + } + return 0; } =20 diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index acdac22953..6bc3e313be 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1984,20 +1984,9 @@ static int __init gicv3_init(void) =20 if ( gic_dist_supports_lpis() ) { - res =3D gicv3_its_init(); + res =3D gicv3_its_init(intid_bits); if ( res ) - panic("GICv3: ITS: initialization failed: %d\n", res); - - /* - * Host LPI allocation uses ITS-derived memory attributes, so defe= r it - * until after gicv3_its_init() has discovered ITS workarounds. - */ - if ( gicv3_its_host_has_its() ) - { - res =3D gicv3_lpi_init_host_lpis(intid_bits); - if ( res ) - panic("GICv3: LPI initialization failed: %d\n", res); - } + panic("GICv3: ITS/LPI initialization failed: %d\n", res); } =20 res =3D gicv3_cpu_init(); diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/a= sm/gic_v3_its.h index 02c083f210..e1322b94f8 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -156,7 +156,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base); =20 /* Initialize the host structures for LPIs and the host ITSes. */ int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits); -int gicv3_its_init(void); +int gicv3_its_init(unsigned int host_lpi_bits); =20 /* Store the physical address and ID for each redistributor as read from D= T. */ void gicv3_set_redist_address(paddr_t address, unsigned int redist_id); @@ -245,7 +245,7 @@ static inline int gicv3_lpi_init_host_lpis(unsigned int= host_lpi_bits) return 0; } =20 -static inline int gicv3_its_init(void) +static inline int gicv3_its_init(unsigned int host_lpi_bits) { return 0; } --=20 2.53.0 From nobody Thu Sep 24 19:02:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" ITS quirks can impose restrictions on memory accessed by the ITS itself and on shared host LPI/Redistributor state. These scopes are not identical, so a single global ITS quirk state makes the host LPI policy depend implicitly on the quirks seen while initializing host ITSes. Add per-ITS quirk_flags to struct host_its and keep a separate host_lpi_flags state in the LPI code. The quirk table now records the ITS-private and host LPI scopes explicitly through its_flags and lpi_flags. The R-Car Gen4 quirk applies the same memory restrictions to both scopes, preserving the existing R-Car memory policy without relying on an implicit aggregation step. This also removes the assumption that all host ITSes must expose the same quirk state. ITS-derived host LPI restrictions are accumulated only from quirk entries that explicitly set lpi_flags. Use per-ITS quirk_flags for GITS_CBASER, GITS_BASER, and ITT allocations. Use host_lpi_flags when allocating the property and pending tables and when programming GICR_PROPBASER and GICR_PENDBASER. Memory-related quirk bits are named GICV3_QUIRK_MEM_* and are translated by shared gicv3_mem_get_*() helpers. Collect both scopes during the ITS preparation pass, before host LPI state is allocated. Keep init-only annotations and includes in the implementation files rather than the public header. Signed-off-by: Mykola Kvach --- Changes in v3: - Collect quirk flags during the ITS preparation pass added earlier. - Keep init-only annotations and includes in implementation files. Changes in v2: - Replace v1's single global ITS quirk flags and same-quirk validation with explicit per-ITS and host LPI quirk scopes. - Drop the v1 ITS pre-initialization approach from this patch. In v2, host LPI allocation was moved after ITS initialization by a separate patch. - Drop DT dma-noncoherent handling from this patch; firmware-provided non-coherency is handled separately with explicit ITS-node and GIC-node scopes. - Keep host_lpi_flags owned by gic-v3-lpi.c and update it only with quirk flags that explicitly apply to host LPI/Redistributor state. - Rename the current memory-related bits to GICV3_QUIRK_MEM_* and use shared gicv3_mem_get_*() helpers for register attributes and allocation flags. --- xen/arch/arm/gic-v3-its.c | 111 ++++++++++++-------------- xen/arch/arm/gic-v3-lpi.c | 45 +++++++++-- xen/arch/arm/include/asm/gic_v3_its.h | 18 +++-- 3 files changed, 100 insertions(+), 74 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 972825bf06..454fd0e0ef 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -52,43 +52,40 @@ struct its_device { struct pending_irq *pend_irqs; /* One struct per event */ }; =20 -/* - * It is unlikely that a platform implements ITSes with different quirks, - * so assume they all share the same. - */ struct its_quirk { const char *desc; - bool (*init)(struct host_its *hw_its); uint32_t iidr; uint32_t mask; + uint32_t its_flags; + /* + * lpi_flags are ORed into the global host LPI policy and must only + * contain additive restrictions. Non-additive LPI quirks need explicit + * handling. + */ + uint32_t lpi_flags; }; =20 -static uint32_t __ro_after_init its_quirk_flags; - -static bool gicv3_its_enable_quirk_gen4(struct host_its *hw_its) -{ - its_quirk_flags |=3D HOST_ITS_WORKAROUND_NC_NS | - HOST_ITS_WORKAROUND_32BIT_ADDR; - - return true; -} - static const struct its_quirk its_quirks[] =3D { { .desc =3D "R-Car Gen4", .iidr =3D 0x0201743b, .mask =3D 0xffffffffU, - .init =3D gicv3_its_enable_quirk_gen4, + .its_flags =3D GICV3_QUIRK_MEM_NC_NS | GICV3_QUIRK_MEM_32BIT_ADDR, + .lpi_flags =3D GICV3_QUIRK_MEM_NC_NS | GICV3_QUIRK_MEM_32BIT_ADDR, }, { /* Sentinel. */ } }; =20 -static const struct its_quirk *gicv3_its_find_quirk(uint32_t iidr) +static const struct its_quirk *__init gicv3_its_find_quirk(uint32_t iidr) { const struct its_quirk *quirks =3D its_quirks; =20 + /* + * The first matching quirk wins. More specific quirks must be listed + * before broader IIDR-only entries. + */ for ( ; quirks->desc; quirks++ ) { if ( quirks->iidr =3D=3D (quirks->mask & iidr) ) @@ -98,53 +95,38 @@ static const struct its_quirk *gicv3_its_find_quirk(uin= t32_t iidr) return NULL; } =20 -static void gicv3_its_enable_quirks(struct host_its *hw_its) +static void __init gicv3_its_collect_quirks(struct host_its *hw_its) { uint32_t iidr =3D readl_relaxed(hw_its->its_base + GITS_IIDR); const struct its_quirk *quirk =3D gicv3_its_find_quirk(iidr); =20 - if ( quirk && quirk->init(hw_its) ) - printk("GICv3: enabling workaround for ITS: %s\n", quirk->desc); -} - -static void gicv3_its_validate_quirks(void) -{ - const struct its_quirk *quirk =3D NULL, *prev =3D NULL; - const struct host_its *hw_its; - - if ( list_empty(&host_its_list) ) - return; - - hw_its =3D list_first_entry(&host_its_list, struct host_its, entry); - prev =3D gicv3_its_find_quirk(readl_relaxed(hw_its->its_base + GITS_II= DR)); - - list_for_each_entry(hw_its, &host_its_list, entry) + if ( quirk ) { - quirk =3D gicv3_its_find_quirk(readl_relaxed(hw_its->its_base + GI= TS_IIDR)); - BUG_ON(quirk !=3D prev); - prev =3D quirk; + hw_its->quirk_flags |=3D quirk->its_flags; + gicv3_lpi_update_host_flags(quirk->lpi_flags); + printk("GICv3: enabling workaround for ITS: %s\n", quirk->desc); } } =20 -uint64_t gicv3_its_get_cacheability(void) +uint64_t gicv3_mem_get_cacheability(uint32_t flags) { - if ( its_quirk_flags & HOST_ITS_WORKAROUND_NC_NS ) + if ( flags & GICV3_QUIRK_MEM_NC_NS ) return GIC_BASER_CACHE_nC; =20 return GIC_BASER_CACHE_RaWaWb; } =20 -uint64_t gicv3_its_get_shareability(void) +uint64_t gicv3_mem_get_shareability(uint32_t flags) { - if ( its_quirk_flags & HOST_ITS_WORKAROUND_NC_NS ) + if ( flags & GICV3_QUIRK_MEM_NC_NS ) return GIC_BASER_NonShareable; =20 return GIC_BASER_InnerShareable; } =20 -unsigned int gicv3_its_get_memflags(void) +unsigned int gicv3_mem_get_alloc_flags(uint32_t flags) { - if ( its_quirk_flags & HOST_ITS_WORKAROUND_32BIT_ADDR ) + if ( flags & GICV3_QUIRK_MEM_32BIT_ADDR ) return MEMF_bits(32); =20 return 0; @@ -391,13 +373,17 @@ static void *its_map_cbaser(struct host_its *its) uint64_t reg; unsigned int order; void *buffer; + uint64_t cacheability =3D gicv3_mem_get_cacheability(its->quirk_flags); + uint64_t shareability =3D gicv3_mem_get_shareability(its->quirk_flags); + unsigned int memflags =3D gicv3_mem_get_alloc_flags(its->quirk_flags); =20 - reg =3D gicv3_its_get_shareability() << GITS_BASER_SHAREABILITY_SHIFT; - reg |=3D GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_= SHIFT; - reg |=3D gicv3_its_get_cacheability() << GITS_BASER_INNER_CACHEABILITY= _SHIFT; + reg =3D MASK_INSR(shareability, GITS_BASER_SHAREABILITY_MASK); + reg |=3D MASK_INSR(GIC_BASER_CACHE_SameAsInner, + GITS_BASER_OUTER_CACHEABILITY_MASK); + reg |=3D MASK_INSR(cacheability, GITS_BASER_INNER_CACHEABILITY_MASK); =20 order =3D get_order_from_bytes(max(ITS_CMD_QUEUE_SZ, SZ_64K)); - buffer =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + buffer =3D alloc_xenheap_pages(order, memflags); if ( !buffer ) return NULL; =20 @@ -438,8 +424,8 @@ static void *its_map_cbaser(struct host_its *its) /* The ITS BASE registers work with page sizes of 4K, 16K or 64K. */ #define BASER_PAGE_BITS(sz) ((sz) * 2 + 12) =20 -static int its_map_baser(void __iomem *basereg, uint64_t regc, - unsigned int nr_items) +static int its_map_baser(struct host_its *its, void __iomem *basereg, + uint64_t regc, unsigned int nr_items) { uint64_t attr, reg; unsigned int entry_size =3D GITS_BASER_ENTRY_SIZE(regc); @@ -447,10 +433,14 @@ static int its_map_baser(void __iomem *basereg, uint6= 4_t regc, unsigned int table_size; unsigned int order; void *buffer; + uint64_t cacheability =3D gicv3_mem_get_cacheability(its->quirk_flags); + uint64_t shareability =3D gicv3_mem_get_shareability(its->quirk_flags); + unsigned int memflags =3D gicv3_mem_get_alloc_flags(its->quirk_flags); =20 - attr =3D gicv3_its_get_shareability() << GITS_BASER_SHAREABILITY_SHIF= T; - attr |=3D GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY= _SHIFT; - attr |=3D gicv3_its_get_cacheability() << GITS_BASER_INNER_CACHEABILIT= Y_SHIFT; + attr =3D MASK_INSR(shareability, GITS_BASER_SHAREABILITY_MASK); + attr |=3D MASK_INSR(GIC_BASER_CACHE_SameAsInner, + GITS_BASER_OUTER_CACHEABILITY_MASK); + attr |=3D MASK_INSR(cacheability, GITS_BASER_INNER_CACHEABILITY_MASK); =20 /* * Setup the BASE register with the attributes that we like. Then read @@ -464,7 +454,7 @@ retry: table_size =3D min(table_size, 256U << BASER_PAGE_BITS(pagesz)); =20 order =3D get_order_from_bytes(max(table_size, BIT(BASER_PAGE_BITS(pag= esz), U))); - buffer =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + buffer =3D alloc_xenheap_pages(order, memflags); if ( !buffer ) return -ENOMEM; =20 @@ -562,7 +552,7 @@ static int __init gicv3_its_prepare_single_its(struct h= ost_its *hw_its) if ( ret ) return ret; =20 - gicv3_its_enable_quirks(hw_its); + gicv3_its_collect_quirks(hw_its); =20 return 0; } @@ -592,18 +582,19 @@ static int __init gicv3_its_init_single_its(struct ho= st_its *hw_its) case GITS_BASER_TYPE_NONE: continue; case GITS_BASER_TYPE_DEVICE: - ret =3D its_map_baser(basereg, reg, BIT(hw_its->devid_bits, UL= )); + ret =3D its_map_baser(hw_its, basereg, reg, + BIT(hw_its->devid_bits, UL)); if ( ret ) return ret; break; case GITS_BASER_TYPE_COLLECTION: - ret =3D its_map_baser(basereg, reg, num_possible_cpus()); + ret =3D its_map_baser(hw_its, basereg, reg, num_possible_cpus(= )); if ( ret ) return ret; break; /* In case this is a GICv4, provide a (dummy) vPE table as well. */ case GITS_BASER_TYPE_VCPU: - ret =3D its_map_baser(basereg, reg, 1); + ret =3D its_map_baser(hw_its, basereg, reg, 1); if ( ret ) return ret; break; @@ -738,6 +729,7 @@ int gicv3_its_map_guest_device(struct domain *d, struct its_device *dev =3D NULL; struct rb_node **new =3D &d->arch.vgic.its_devices.rb_node, *parent = =3D NULL; int i, ret =3D -ENOENT; /* "i" must be signed to check for >=3D 0= below. */ + unsigned int memflags; unsigned int order; =20 hw_its =3D gicv3_its_find_by_doorbell(host_doorbell); @@ -801,8 +793,9 @@ int gicv3_its_map_guest_device(struct domain *d, ret =3D -ENOMEM; =20 /* An Interrupt Translation Table needs to be 256-byte aligned. */ + memflags =3D gicv3_mem_get_alloc_flags(hw_its->quirk_flags); order =3D get_order_from_bytes(max(nr_events * hw_its->itte_size, 256U= L)); - itt_addr =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + itt_addr =3D alloc_xenheap_pages(order, memflags); if ( !itt_addr ) goto out_unlock; =20 @@ -1214,8 +1207,6 @@ int __init gicv3_its_init(unsigned int host_lpi_bits) return ret; } =20 - gicv3_its_validate_quirks(); - if ( list_empty(&host_its_list) ) return 0; =20 diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 9ee338edc2..accfd48a74 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -78,9 +79,29 @@ struct lpi_redist_data { =20 static DEFINE_PER_CPU(struct lpi_redist_data, lpi_redist); =20 +/* + * Host LPI flags are scoped to shared LPI/Redistributor state, not to an + * ITS instance. Arm IHI 0069H.b section 5.1.1 says "LPI configuration is + * global". Section 12.11.33 (GICR_PROPBASER) makes mismatched values + * UNPREDICTABLE for Redistributors that share an LPI Configuration table + * while GICR_CTLR.EnableLPIs =3D=3D 1. Section 12.11.32 (GICR_PENDBASER) + * similarly makes mismatched OuterCache, Shareability or InnerCache values + * across Redistributors UNPREDICTABLE while GICR_CTLR.EnableLPIs =3D=3D 1. + * + * Keep this policy in the LPI code and accumulate only explicit LPI/RD + * restrictions into it. Per-ITS restrictions stay in host_its::quirk_flags + * for GITS_CBASER, GITS_BASER and ITT memory. + */ +static uint32_t __ro_after_init host_lpi_flags; + #define MAX_NR_HOST_LPIS (lpi_data.max_host_lpi_ids - LPI_OFFSET) #define HOST_LPIS_PER_PAGE (PAGE_SIZE / sizeof(union host_lpi)) =20 +void __init gicv3_lpi_update_host_flags(uint32_t flags) +{ + host_lpi_flags |=3D flags; +} + static union host_lpi *gic_get_host_lpi(uint32_t plpi) { union host_lpi *block; @@ -228,6 +249,7 @@ static int gicv3_lpi_allocate_pendtable(unsigned int cp= u) { void *pendtable; unsigned int order; + unsigned int memflags =3D gicv3_mem_get_alloc_flags(host_lpi_flags); =20 if ( per_cpu(lpi_redist, cpu).pending_table ) return -EBUSY; @@ -239,7 +261,7 @@ static int gicv3_lpi_allocate_pendtable(unsigned int cp= u) * physically contiguous memory. */ order =3D get_order_from_bytes(max(lpi_data.max_host_lpi_ids / 8, (uns= igned long)SZ_64K)); - pendtable =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + pendtable =3D alloc_xenheap_pages(order, memflags); if ( !pendtable ) return -ENOMEM; =20 @@ -262,6 +284,8 @@ static int gicv3_lpi_set_pendtable(void __iomem *rdist_= base) { const void *pendtable =3D this_cpu(lpi_redist).pending_table; uint64_t val; + uint64_t cacheability =3D gicv3_mem_get_cacheability(host_lpi_flags); + uint64_t shareability =3D gicv3_mem_get_shareability(host_lpi_flags); =20 /* * The memory should have been allocated while preparing the CPU (or @@ -275,9 +299,10 @@ static int gicv3_lpi_set_pendtable(void __iomem *rdist= _base) =20 ASSERT(!(virt_to_maddr(pendtable) & ~GENMASK(51, 16))); =20 - val =3D gicv3_its_get_cacheability() << GICR_PENDBASER_INNER_CACHEABI= LITY_SHIFT; - val |=3D GIC_BASER_CACHE_SameAsInner << GICR_PENDBASER_OUTER_CACHEABIL= ITY_SHIFT; - val |=3D gicv3_its_get_shareability() << GICR_PENDBASER_SHAREABILITY_S= HIFT; + val =3D MASK_INSR(cacheability, GICR_PENDBASER_INNER_CACHEABILITY_MAS= K); + val |=3D MASK_INSR(GIC_BASER_CACHE_SameAsInner, + GICR_PENDBASER_OUTER_CACHEABILITY_MASK); + val |=3D MASK_INSR(shareability, GICR_PENDBASER_SHAREABILITY_MASK); val |=3D GICR_PENDBASER_PTZ; val |=3D virt_to_maddr(pendtable); =20 @@ -304,10 +329,13 @@ static int gicv3_lpi_set_proptable(void __iomem * rdi= st_base) { uint64_t reg; unsigned int order; + uint64_t cacheability =3D gicv3_mem_get_cacheability(host_lpi_flags); + uint64_t shareability =3D gicv3_mem_get_shareability(host_lpi_flags); =20 - reg =3D gicv3_its_get_cacheability() << GICR_PROPBASER_INNER_CACHEABI= LITY_SHIFT; - reg |=3D GIC_BASER_CACHE_SameAsInner << GICR_PROPBASER_OUTER_CACHEABIL= ITY_SHIFT; - reg |=3D gicv3_its_get_shareability() << GICR_PROPBASER_SHAREABILITY_S= HIFT; + reg =3D MASK_INSR(cacheability, GICR_PROPBASER_INNER_CACHEABILITY_MAS= K); + reg |=3D MASK_INSR(GIC_BASER_CACHE_SameAsInner, + GICR_PROPBASER_OUTER_CACHEABILITY_MASK); + reg |=3D MASK_INSR(shareability, GICR_PROPBASER_SHAREABILITY_MASK); =20 /* * The property table is shared across all redistributors, so allocate @@ -317,9 +345,10 @@ static int gicv3_lpi_set_proptable(void __iomem * rdis= t_base) { /* The property table holds one byte per LPI. */ void *table; + unsigned int memflags =3D gicv3_mem_get_alloc_flags(host_lpi_flags= ); =20 order =3D get_order_from_bytes(max(lpi_data.max_host_lpi_ids, (uns= igned long)SZ_4K)); - table =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + table =3D alloc_xenheap_pages(order, memflags); =20 if ( !table ) return -ENOMEM; diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/a= sm/gic_v3_its.h index e1322b94f8..9230705181 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -110,8 +110,9 @@ #define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0) #define HOST_ITS_USES_PTA (1U << 1) =20 -#define HOST_ITS_WORKAROUND_NC_NS (1U << 0) -#define HOST_ITS_WORKAROUND_32BIT_ADDR (1U << 1) +/* GICv3 memory-related quirk flags. */ +#define GICV3_QUIRK_MEM_NC_NS (1U << 0) +#define GICV3_QUIRK_MEM_32BIT_ADDR (1U << 1) =20 /* We allocate LPIs on the hosts in chunks of 32 to reduce handling overhe= ad. */ #define LPI_BLOCK 32U @@ -128,6 +129,11 @@ struct host_its { unsigned int itte_size; spinlock_t cmd_lock; void *cmd_buf; + /* + * Workaround flags scoped to this ITS instance, including memory + * accessed through GITS_CBASER, GITS_BASER and ITT memory. + */ + uint32_t quirk_flags; unsigned int flags; }; =20 @@ -157,6 +163,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base); /* Initialize the host structures for LPIs and the host ITSes. */ int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits); int gicv3_its_init(unsigned int host_lpi_bits); +void gicv3_lpi_update_host_flags(uint32_t flags); =20 /* Store the physical address and ID for each redistributor as read from D= T. */ void gicv3_set_redist_address(paddr_t address, unsigned int redist_id); @@ -199,10 +206,9 @@ struct pending_irq *gicv3_assign_guest_event(struct do= main *d, void gicv3_lpi_update_host_entry(uint32_t host_lpi, int domain_id, uint32_t virt_lpi); =20 -/* ITS quirks handling. */ -uint64_t gicv3_its_get_cacheability(void); -uint64_t gicv3_its_get_shareability(void); -unsigned int gicv3_its_get_memflags(void); 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charset="utf-8" ITS quirks are matched only by IIDR and mask fields stored in each table entry. That is too coarse when the same GIC IP block appears on several platforms but a workaround is valid only for some of them. Replace the fixed IIDR fields with a generic match(hw_its, data) callback and an opaque data pointer. Add an IIDR matcher as a reusable building block and use it from the R-Car Gen4 matcher after checking the Renesas machine compatibles. This intentionally narrows the R-Car Gen4 quirk. Previously every ITS with IIDR 0x0201743b matched. Now it matches only a DT-discovered ITS on an r8a779f0 or r8a779g0 machine. ACPI-discovered ITSes and the same IIDR on other platforms no longer match. Keep first-match semantics explicit. Assert that non-sentinel entries provide a matcher and that IIDR matching receives match data. Retain runtime guards so malformed entries cannot cause a NULL function call or data dereference in non-debug builds. Place the matcher data and table in init-only read-only sections. The matched entry still supplies separate ITS and LPI flags; this patch only changes how the entry is selected. Signed-off-by: Mykola Kvach --- Changes in v3: - Document the intentional narrowing of the R-Car Gen4 match. - Add the non-debug NULL-data guard. - Put the matcher data and table in init-only read-only sections. Changes in v2: - Replace v1's optional platform callback plus fixed IIDR/mask fields with a single generic match(hw_its, data) selector. - Add a reusable IIDR matcher and use it after the R-Car Gen4 machine-compatible checks. - Document that the R-Car Gen4 quirk remains DT-only. - Keep the split ITS and host LPI quirk scopes when applying the matched entry. - Document first-match ordering in the lookup path and guard against entries without a match callback or IIDR match data. --- xen/arch/arm/gic-v3-its.c | 73 +++++++++++++++++++++++++++++++-------- 1 file changed, 58 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 454fd0e0ef..f52232ca40 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -54,8 +54,8 @@ struct its_device { =20 struct its_quirk { const char *desc; - uint32_t iidr; - uint32_t mask; + bool (*match)(const struct host_its *hw_its, const void *data); + const void *data; uint32_t its_flags; /* * lpi_flags are ORed into the global host LPI policy and must only @@ -65,11 +65,52 @@ struct its_quirk { uint32_t lpi_flags; }; =20 -static const struct its_quirk its_quirks[] =3D { +struct its_quirk_match_iidr { + uint32_t iidr; + uint32_t mask; +}; + +static bool __init gicv3_its_match_iidr(const struct host_its *hw_its, + const void *data) +{ + const struct its_quirk_match_iidr *match; + uint32_t iidr; + + ASSERT(data); + + if ( !data ) + return false; + + match =3D data; + iidr =3D readl_relaxed(hw_its->its_base + GITS_IIDR); + + return (iidr & match->mask) =3D=3D match->iidr; +} + +static bool __init gicv3_its_match_quirk_gen4(const struct host_its *hw_it= s, + const void *data) +{ + if ( !hw_its->dt_node ) + return false; + + if ( !dt_machine_is_compatible("renesas,r8a779f0") && + !dt_machine_is_compatible("renesas,r8a779g0") ) + return false; + + return gicv3_its_match_iidr(hw_its, data); +} + +static const struct its_quirk_match_iidr rcar_gen4_iidr __initconst =3D { + /* Implementer 0x43b identifies Arm Ltd. */ + .iidr =3D 0x0201743b, + .mask =3D 0xffffffffU, +}; + +static const struct its_quirk its_quirks[] __initconstrel =3D { { - .desc =3D "R-Car Gen4", - .iidr =3D 0x0201743b, - .mask =3D 0xffffffffU, + .desc =3D "R-Car Gen4", + .match =3D gicv3_its_match_quirk_gen4, + .data =3D &rcar_gen4_iidr, .its_flags =3D GICV3_QUIRK_MEM_NC_NS | GICV3_QUIRK_MEM_32BIT_ADDR, .lpi_flags =3D GICV3_QUIRK_MEM_NC_NS | GICV3_QUIRK_MEM_32BIT_ADDR, }, @@ -78,18 +119,21 @@ static const struct its_quirk its_quirks[] =3D { } }; =20 -static const struct its_quirk *__init gicv3_its_find_quirk(uint32_t iidr) +static const struct its_quirk *__init gicv3_its_find_quirk( + const struct host_its *hw_its) { - const struct its_quirk *quirks =3D its_quirks; + const struct its_quirk *quirk; =20 /* - * The first matching quirk wins. More specific quirks must be listed - * before broader IIDR-only entries. + * The first matching quirk wins. Entries that match a specific platfo= rm + * must be listed before broader IIDR-only entries. */ - for ( ; quirks->desc; quirks++ ) + for ( quirk =3D its_quirks; quirk->desc; quirk++ ) { - if ( quirks->iidr =3D=3D (quirks->mask & iidr) ) - return quirks; + ASSERT(quirk->match); + + if ( quirk->match && quirk->match(hw_its, quirk->data) ) + return quirk; } =20 return NULL; @@ -97,8 +141,7 @@ static const struct its_quirk *__init gicv3_its_find_qui= rk(uint32_t iidr) =20 static void __init gicv3_its_collect_quirks(struct host_its *hw_its) { - uint32_t iidr =3D readl_relaxed(hw_its->its_base + GITS_IIDR); - const struct its_quirk *quirk =3D gicv3_its_find_quirk(iidr); + const struct its_quirk *quirk =3D gicv3_its_find_quirk(hw_its); =20 if ( quirk ) { --=20 2.53.0 From nobody Thu Sep 24 19:02:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" The DT dma-noncoherent property describes the bus coherency of the device represented by the node. On an ITS subnode, that is memory accessed by that ITS. Add GICV3_QUIRK_MEM_NC_NS to the corresponding host_its and use it when programming GITS_CBASER and GITS_BASER. On the top-level GIC node, the property describes the Redistributor side of the LPI path. Collect it in gicv3_lpi_init_host_lpis() and apply it only to the host LPI policy used when allocating the property and pending tables and when programming GICR_PROPBASER and GICR_PENDBASER. Mark the function init-only because firmware attributes are collected only during boot. Do not inherit the property between parent and child nodes: ITS-node non-coherency does not change the global host LPI policy, and GIC-node non-coherency does not change per-ITS quirk_flags. ACPI is unchanged; this patch only consumes the DT dma-noncoherent property. Signed-off-by: Mykola Kvach --- Changes in v3: - Keep the ITS init annotations with the earlier initialization patch. - Drop the redundant aggregate host-LPI-flags message. Changes in v2: - Split v1's dma-noncoherent handling into explicit ITS-node and GIC-node scopes. - Apply an ITS subnode property only to the matching host_its quirk_flags. - Collect the top-level GIC property from gic-v3-lpi.c before host LPI allocations use host_lpi_flags. --- xen/arch/arm/gic-v3-its.c | 17 +++++++++++++++++ xen/arch/arm/gic-v3-lpi.c | 20 +++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index f52232ca40..6734f94e7c 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -139,6 +139,21 @@ static const struct its_quirk *__init gicv3_its_find_q= uirk( return NULL; } =20 +static void __init gicv3_its_collect_fw_attrs(struct host_its *hw_its) +{ + /* + * An ITS subnode property describes memory transactions made by that = ITS. + * Do not inherit it into the global host LPI/Redistributor policy. + */ + if ( !hw_its->dt_node || + !dt_property_read_bool(hw_its->dt_node, "dma-noncoherent") ) + return; + + hw_its->quirk_flags |=3D GICV3_QUIRK_MEM_NC_NS; + printk("GICv3: ITS @%#"PRIpaddr" marked dma-noncoherent\n", + hw_its->addr); +} + static void __init gicv3_its_collect_quirks(struct host_its *hw_its) { const struct its_quirk *quirk =3D gicv3_its_find_quirk(hw_its); @@ -149,6 +164,8 @@ static void __init gicv3_its_collect_quirks(struct host= _its *hw_its) gicv3_lpi_update_host_flags(quirk->lpi_flags); printk("GICv3: enabling workaround for ITS: %s\n", quirk->desc); } + + gicv3_its_collect_fw_attrs(hw_its); } =20 uint64_t gicv3_mem_get_cacheability(uint32_t flags) diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index accfd48a74..1cf49430ea 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -7,7 +7,9 @@ * Copyright (C) 2016,2017 - ARM Ltd */ =20 +#include #include +#include #include #include #include @@ -102,6 +104,20 @@ void __init gicv3_lpi_update_host_flags(uint32_t flags) host_lpi_flags |=3D flags; } =20 +static void __init gicv3_lpi_collect_fw_attrs(void) +{ + /* + * A top-level GIC node property describes the Redistributor side of t= he + * LPI path. Do not inherit it into per-ITS policy. + */ + if ( !acpi_disabled || + !dt_property_read_bool(dt_interrupt_controller, "dma-noncoherent"= ) ) + return; + + gicv3_lpi_update_host_flags(GICV3_QUIRK_MEM_NC_NS); + printk("GICv3: Redistributors marked dma-noncoherent\n"); +} + static union host_lpi *gic_get_host_lpi(uint32_t plpi) { union host_lpi *block; @@ -443,7 +459,7 @@ integer_param("max_lpi_bits", max_lpi_bits); * to the page with the actual "union host_lpi" entries. Our LPI limit * avoids excessive memory usage. */ -int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) +int __init gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) { unsigned int nr_lpi_ptrs; int rc; @@ -451,6 +467,8 @@ int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) /* We rely on the data structure being atomically accessible. */ BUILD_BUG_ON(sizeof(union host_lpi) > sizeof(unsigned long)); =20 + gicv3_lpi_collect_fw_attrs(); + /* * An implementation needs to support at least 14 bits of LPI IDs. * Tell the user about it, the actual number is reported below. --=20 2.53.0