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([45.12.25.69]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bddc5ece286sm655205266b.40.2026.05.27.17.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 17:28:10 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779928090; x=1780532890; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yg8AqMmDF3yKBovZvD64poEMRLvOHDqQeZLyKNm919c=; b=pVIZ6yWmUuxFV+PnDoNVq32g0EshANmCGlQcwcmeXIi8HsadwDFH/IWmVY6w8TBKUR TERLhTItBXCUjwtua0ZqFaO6mtuo5fFBtfmGtmMctgGX+6ayo7Ai1gwk5HEcIR44eb5i 60AKXq+WGCaOjgxIgLRI/ywSHs6hzjQtuQ0P/aU2LcEMWL6Cfx1n2x0UvdYfaORmsmWN SRnJJoP1nne62LlzTf8khZcRrf4M/K9e1pkKnzu75IMtIss7RgRGo0ahJ0q3sSi6ULR6 AIQG+Xt+qwjOC0YOg5+JjDApenccfPicJddRqt9R01SF7yVM0BGBvNCvIPZOSEkNId6h fM8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779928090; x=1780532890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Yg8AqMmDF3yKBovZvD64poEMRLvOHDqQeZLyKNm919c=; b=sw6TmDGJce2pXlS+lJY2R32bKw9qHZgkXpFP/H8G/NeLAP8m8QLXj24IPNTuGkVjpx l7KVkbnzvQzAEfEAyjZSnRpUX+yZZf+NJLn0dmLZVh+XNIZKaYI+hUHsJp0e7bUIGOfa poVTpjf9gseipVUHH6eTpye9nlqvVmsiHDcjSvGYtu89v4u5LI1ApwQCwOhOp5nu+jHt Am6zTKRWotdboHjO8pW+/V7XQvu1oNtb8wwxj0T+wzQRrDnXY82PS9adv/aQXxtbMo7/ g2p42xr8myvtTelbkZpFGuiHIXw3naS/WvPgiiClZUu7sU7UPtEGm8nSHUO6R4VtDB/a BkJA== X-Gm-Message-State: AOJu0YzsX/FpUoEL51jPhib5xEV4+1z7c4zcx91oVsbvJVNsxn0yLKrb O49bVaaYgHri1XMraQ11RWyoysyVWO8YodTxD8v/nIgvg4VlQvbdHX3VW76q2g== X-Gm-Gg: Acq92OGbZjIEhEqbYQcvbPps4/aHialt35SZymC0PZawb/vFb7G8nYLP5n+X6yNtnbN cDI6es6Vsb9jF6XrDxgi5xzRE4bQh71gSCxGNyU9Fs7L+7YTUlq77l0Y/nop7ylNmHMbGixNZtn rTF/Plg4tyyRTON63chu13L55zA8heP9R2rMUwP0p1aEAxK1DxZpTFFvgs6Qmhmhdl/OJIENFE9 vsUqzv2Wc4kAqlcoub0ipCPd3H7XI10HpvbVJk/TJP/CYXSOsYObBN81ebfa/AlfyGEdAQ9BlZW 3k/swIZvhNUV/0120Ucp8GpJkDa54+6rVJ3lfkcQKfPjdFSvbuID1sRm9/LUVfCdk45lYKmRYgJ eBEso5+iy/jQg1Nd3/vzbC/6Qb6Kz21Eap0PepZVkXjlGoyik90sBLAfZaupeV7piHD4IjsSAo7 wjuLYu/R+BMJgzTpJ8s1EOdovUZmjT5xhsxm1M X-Received: by 2002:a17:907:c80c:b0:bc9:d864:2735 with SMTP id a640c23a62f3a-bdd2aada46fmr1592794266b.34.1779928090335; Wed, 27 May 2026 17:28:10 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Luca Fancellu , Oleksii Kurochko Subject: [PATCH for-4.22 v2 1/4] xen/arm: gic: defer host LPI allocation until after ITS init Date: Thu, 28 May 2026 03:25:49 +0300 Message-ID: <112419d3ea48ca328849c8f6647909d3eb667b40.1779922874.git.mykola_kvach@epam.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1779928090-8C67DD75-5CF5C166/0/0 X-purgate-type: clean X-purgate-size: 2517 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779928128372158500 Content-Type: text/plain; charset="utf-8" From: Mykola Kvach gicv3_lpi_init_host_lpis() allocates host LPI state, including the host LPI lookup table, CPU notifier state and the boot CPU pending table. Those allocations use gicv3_its_get_memflags(). ITS workarounds are discovered from gicv3_its_init(), so allocating host LPI state from gicv3_dist_init() can happen before the memory restrictions required by the ITS are known. On affected systems this can leave Redistributor LPI state allocated and programmed with the default memory policy. Move host LPI initialization after gicv3_its_init(), and only run it when a host ITS was found. The old call ignored the return value. Now that the call is made from gicv3_init(), check it and panic on failure because Redistributor LPI initialization relies on that state being available. Signed-off-by: Mykola Kvach --- Changes in v2: - Replace the v1 ITS pre-initialization hook with the less invasive approach suggested during review: move the existing host LPI initialization after gicv3_its_init(). - Check gicv3_lpi_init_host_lpis() and panic on failure, matching the fatal nature of host LPI setup once ITS initialization succeeded. --- xen/arch/arm/gic-v3.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 17ff85ef5d..acdac22953 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -764,9 +764,6 @@ static void __init gicv3_dist_init(void) type =3D readl_relaxed(GICD + GICD_TYPER); nr_lines =3D 32 * ((type & GICD_TYPE_LINES) + 1); =20 - if ( type & GICD_TYPE_LPIS ) - gicv3_lpi_init_host_lpis(GICD_TYPE_ID_BITS(type)); - /* Only 1020 interrupts are supported */ nr_lines =3D min(1020U, nr_lines); gicv3_info.nr_lines =3D nr_lines; @@ -1990,6 +1987,17 @@ static int __init gicv3_init(void) res =3D gicv3_its_init(); if ( res ) panic("GICv3: ITS: initialization failed: %d\n", res); + + /* + * Host LPI allocation uses ITS-derived memory attributes, so defe= r it + * until after gicv3_its_init() has discovered ITS workarounds. + */ + if ( gicv3_its_host_has_its() ) + { + res =3D gicv3_lpi_init_host_lpis(intid_bits); + if ( res ) + panic("GICv3: LPI initialization failed: %d\n", res); + } } =20 res =3D gicv3_cpu_init(); --=20 2.43.0 From nobody Sat May 30 11:21:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779928119; cv=none; d=zohomail.com; s=zohoarc; b=UVNhB/lnETXqEP90IiUf283/eXgedRsoe99uxSZcAylmB7dBYTCpaVRmA00xgLgfdx6gwrvnsjFqr1Y9U/rXJ7hzyDoTVpQGzV02ILys41z0HkfEkyRf7ltsbxe4hufM6oqzYMf82n4X/METFJtWfIHyWnKH9CpzxQOFxjRDolo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779928119; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qdjncDbrY3UNar+wQG0hF6uZxmjzXxeMKUR7WBbGASk=; b=VzRU2iSTGv4vwI6JaRfjdg9NJyh9T6VHEQ14SMbtQwGGky2BnBoRbmS+lzEa5GZEtsqmY1Yg0NDWS1rwUJCTc0qMN3j9WSBDrhrgxfaOritTahaLJYVLpjt2E5uBlI3v/UT6c7YGM+kd4SYUkodLm56y/gyj36OIA72n50MDLj0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1779928119912768.9025568129728; Wed, 27 May 2026 17:28:39 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1320865.1587984 (Exim 4.92) (envelope-from ) id 1wSObe-0007hx-HI; Thu, 28 May 2026 00:28:14 +0000 Received: by outflank-mailman (output) from mailman id 1320865.1587984; Thu, 28 May 2026 00:28:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wSObe-0007hq-ED; Thu, 28 May 2026 00:28:14 +0000 Received: by outflank-mailman (input) for mailman id 1320865; Thu, 28 May 2026 00:28:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wSObc-0007Hq-UH for xen-devel@lists.xenproject.org; Thu, 28 May 2026 00:28:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wSObc-000CGb-Ac for xen-devel@lists.xenproject.org; Thu, 28 May 2026 02:28:12 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 6a178bd3-2eae-0a2a0a5409dd-0a2a45068b06-18 for ; Thu, 28 May 2026 02:28:12 +0200 Received: from [209.85.218.50] (helo=mail-ej1-f50.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 6a178c1c-7371-0a2a45060019-d155da32ed7b-3 for ; Thu, 28 May 2026 02:28:12 +0200 Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-bce386d5b85so1842002666b.1 for ; Wed, 27 May 2026 17:28:12 -0700 (PDT) Received: from EPUAKYIW02F7.. ([45.12.25.69]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bddc5ece286sm655205266b.40.2026.05.27.17.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 17:28:10 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779928092; x=1780532892; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qdjncDbrY3UNar+wQG0hF6uZxmjzXxeMKUR7WBbGASk=; b=YMDvnVDBPtJoplOHMb2+wFUi/+pkS+kqRPY/yY5MxJScCmoValPvq8CfQrts38EA6E J2RbtR8+aC0hoN9k2+dEmI+FOD9C1KqZrOBvK3o2tj/ip41jNn6IFakU4tcGJR6usdnt t99wGVD8gdd63h/sP3obtzvsfbtvUZ1lrjrx2uRvNMahHBZfSVZyPlSbP853Him+aqCO x8bKy47oQ/vhf7U+HjnleCGokbPKpT03mNjWqNNWqW7WQaELg5N3hENJ3i8rb6e3hAgw oz2pRdQ0KEmSwzmM40aotX3keRglTFBsvfPZuTHORNOegFR8X/DBBbMnPPiZQBR9h+nN gqBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779928092; x=1780532892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=qdjncDbrY3UNar+wQG0hF6uZxmjzXxeMKUR7WBbGASk=; b=Hd6RAf4sXwbnj2tCLj7EX93ABNcsXXCkLniw3PVdm7bxR2jgP7U18o/CU1CUqoKDbD 4ZDrdvrlT+ptiOXoLllnReiL9DyEdcETnPmAq124qoD9J1Hk008jZLtx7fE511Ry0tmC rdir4dI59Umgu9Kr/MVEYtCYn+klCYDfp8ZwjI+qazOis2xxY7SFNGMuDzHmE6pFgKSt uA5whJJgl1loK+WFliuqlwVWnJPjQM2MKDAzLQN/y03mEqpuWrWg2J3M2pfJdYzC5mfD h5bCcexsQot7uUXGx6jyBdeRlf/X6/vy6hlN8kbttNy/kRYrHh+nBHlTj705VgdcgkJr 5gEQ== X-Gm-Message-State: AOJu0Yz1hQqHdW4VWjPJt8rxLh7g7ft5nlqpyABikm8HYSTX9EE3wGZC bDwXnnZ5AsGVpo2g7hdVg0wYYG8Vk7WFH6XayZc1u0NS2PnHVmAmT7xwXho6CQ== X-Gm-Gg: Acq92OEEonm8TKLhMby5ZnyhqdZ407u9VvUSglbI/tyGAMnBjfY9mIG92qpFQjIL5af 1kgT7cUpQ82pL0VGyZ/sIOqXQwnd5I6jgPJiIPbTb1TgHLFlSThsZ1eNRmVY4o9Z0qQYzAfUq0I i1042/eDq6xW6KHjiFy98mIkenoB4nLpdl/e9mY/D2dLDLqB0njxpEcUcR87WyoiyqU96+Qfurg cH2wlwm6tLTPTAz7F41tqawMqvoE5ig5lN4XMul34NMVl7MFdmoJHrjnTn8ylySG3l7E394xB2H cnZlnKYkaVPfjSVZg8KAGLB5zouAF47eR2+Zn3fyqVu5qWUhDSItSD+dp1p/WhS3Wx/YkwVTgzc hQwheZToMTNYfBn8wfUx1MeEfDX2MVdnts8sH0O4WT/b6J55RYqhxGuyTJuKX84YkVpj/na6l0x 09RUDM3XBvSMiZSC8GUijqtMY1jPSvsqDhRq4k X-Received: by 2002:a17:907:72d2:b0:bdb:4cf3:7035 with SMTP id a640c23a62f3a-bdd253390b1mr1374526266b.4.1779928091403; Wed, 27 May 2026 17:28:11 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Luca Fancellu , Volodymyr Babchuk Subject: [PATCH v2 2/4] xen/arm: its: separate ITS and host LPI quirk scopes Date: Thu, 28 May 2026 03:25:50 +0300 Message-ID: <5edcb9ec3e643133d115f009d0d942869ffb6955.1779922874.git.mykola_kvach@epam.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1779928092-8FB93D75-D9199EAC/0/0 X-purgate-type: clean X-purgate-size: 18511 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779928122904154100 Content-Type: text/plain; charset="utf-8" From: Mykola Kvach ITS quirks can impose restrictions on memory accessed by the ITS itself and on shared host LPI/Redistributor state. These scopes are not identical, so a single global ITS quirk state makes the host LPI policy depend implicitly on the quirks seen while initializing host ITSes. Add per-ITS quirk_flags to struct host_its and keep a separate host_lpi_flags state in the LPI code. The quirk table now records the ITS-private and host LPI scopes explicitly through its_flags and lpi_flags. The R-Car Gen4 quirk applies the same memory-related restrictions to both scopes, preserving the existing behavior without relying on an implicit aggregation step. This also removes the old assumption that all host ITSes must expose the same quirk state. Host LPI restrictions are accumulated only from quirk entries that explicitly set lpi_flags. Use per-ITS quirk_flags for GITS_CBASER, GITS_BASER and ITT allocations. Use host_lpi_flags directly in gic-v3-lpi.c for GICR_PROPBASER and GICR_PENDBASER setup. Memory-related quirk bits are named GICV3_QUIRK_MEM_* and are translated by shared gicv3_mem_get_*() helpers. Signed-off-by: Mykola Kvach --- Changes in v2: - Replace v1's single global ITS quirk flags and same-quirk validation with explicit per-ITS and host LPI quirk scopes. - Drop the v1 ITS pre-initialization approach from this patch; host LPI allocation ordering is fixed separately by moving it after ITS init. - Drop DT dma-noncoherent handling from this patch; firmware-provided non-coherency is handled separately with explicit ITS-node and GIC-node scopes. - Keep host_lpi_flags owned by gic-v3-lpi.c and update it only with quirk flags that explicitly apply to host LPI/Redistributor state. - Rename the current memory-related bits to GICV3_QUIRK_MEM_* and use shared gicv3_mem_get_*() helpers for register attributes and allocation flags. --- xen/arch/arm/gic-v3-its.c | 113 ++++++++++++-------------- xen/arch/arm/gic-v3-lpi.c | 44 ++++++++-- xen/arch/arm/include/asm/gic_v3_its.h | 19 +++-- 3 files changed, 101 insertions(+), 75 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 7560d46c6d..dc48a84789 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -51,99 +51,81 @@ struct its_device { struct pending_irq *pend_irqs; /* One struct per event */ }; =20 -/* - * It is unlikely that a platform implements ITSes with different quirks, - * so assume they all share the same. - */ struct its_quirk { const char *desc; - bool (*init)(struct host_its *hw_its); uint32_t iidr; uint32_t mask; + uint32_t its_flags; + /* + * lpi_flags are ORed into the global host LPI policy and must only + * contain additive restrictions. Non-additive LPI quirks need explicit + * handling. + */ + uint32_t lpi_flags; }; =20 -static uint32_t __ro_after_init its_quirk_flags; - -static bool gicv3_its_enable_quirk_gen4(struct host_its *hw_its) -{ - its_quirk_flags |=3D HOST_ITS_WORKAROUND_NC_NS | - HOST_ITS_WORKAROUND_32BIT_ADDR; - - return true; -} - static const struct its_quirk its_quirks[] =3D { { .desc =3D "R-Car Gen4", .iidr =3D 0x0201743b, .mask =3D 0xffffffffU, - .init =3D gicv3_its_enable_quirk_gen4, + .its_flags =3D GICV3_QUIRK_MEM_NC_NS | GICV3_QUIRK_MEM_32BIT_ADDR, + .lpi_flags =3D GICV3_QUIRK_MEM_NC_NS | GICV3_QUIRK_MEM_32BIT_ADDR, }, { /* Sentinel. */ } }; =20 -static struct its_quirk* gicv3_its_find_quirk(uint32_t iidr) +static const struct its_quirk *__init gicv3_its_find_quirk(uint32_t iidr) { const struct its_quirk *quirks =3D its_quirks; =20 + /* + * The first matching quirk wins. More specific quirks must be listed + * before broader IIDR-only entries. + */ for ( ; quirks->desc; quirks++ ) { if ( quirks->iidr =3D=3D (quirks->mask & iidr) ) - return (struct its_quirk *)quirks; + return quirks; } =20 return NULL; } =20 -static void gicv3_its_enable_quirks(struct host_its *hw_its) +static void __init gicv3_its_collect_quirks(struct host_its *hw_its) { uint32_t iidr =3D readl_relaxed(hw_its->its_base + GITS_IIDR); const struct its_quirk *quirk =3D gicv3_its_find_quirk(iidr); =20 - if ( quirk && quirk->init(hw_its) ) - printk("GICv3: enabling workaround for ITS: %s\n", quirk->desc); -} - -static void gicv3_its_validate_quirks(void) -{ - const struct its_quirk *quirk =3D NULL, *prev =3D NULL; - const struct host_its *hw_its; - - if ( list_empty(&host_its_list) ) - return; - - hw_its =3D list_first_entry(&host_its_list, struct host_its, entry); - prev =3D gicv3_its_find_quirk(readl_relaxed(hw_its->its_base + GITS_II= DR)); - - list_for_each_entry(hw_its, &host_its_list, entry) + if ( quirk ) { - quirk =3D gicv3_its_find_quirk(readl_relaxed(hw_its->its_base + GI= TS_IIDR)); - BUG_ON(quirk !=3D prev); - prev =3D quirk; + hw_its->quirk_flags |=3D quirk->its_flags; + gicv3_lpi_update_host_flags(quirk->lpi_flags); + printk("GICv3: enabling workaround for ITS: %s\n", quirk->desc); } } =20 -uint64_t gicv3_its_get_cacheability(void) +uint64_t gicv3_mem_get_cacheability(uint32_t flags) { - if ( its_quirk_flags & HOST_ITS_WORKAROUND_NC_NS ) + if ( flags & GICV3_QUIRK_MEM_NC_NS ) return GIC_BASER_CACHE_nC; =20 return GIC_BASER_CACHE_RaWaWb; } =20 -uint64_t gicv3_its_get_shareability(void) +uint64_t gicv3_mem_get_shareability(uint32_t flags) { - if ( its_quirk_flags & HOST_ITS_WORKAROUND_NC_NS ) + if ( flags & GICV3_QUIRK_MEM_NC_NS ) return GIC_BASER_NonShareable; =20 return GIC_BASER_InnerShareable; } =20 -unsigned int gicv3_its_get_memflags(void) +unsigned int gicv3_mem_get_alloc_flags(uint32_t flags) { - if ( its_quirk_flags & HOST_ITS_WORKAROUND_32BIT_ADDR ) + if ( flags & GICV3_QUIRK_MEM_32BIT_ADDR ) return MEMF_bits(32); =20 return 0; @@ -390,13 +372,17 @@ static void *its_map_cbaser(struct host_its *its) uint64_t reg; unsigned int order; void *buffer; + uint64_t cacheability =3D gicv3_mem_get_cacheability(its->quirk_flags); + uint64_t shareability =3D gicv3_mem_get_shareability(its->quirk_flags); + unsigned int memflags =3D gicv3_mem_get_alloc_flags(its->quirk_flags); =20 - reg =3D gicv3_its_get_shareability() << GITS_BASER_SHAREABILITY_SHIFT; - reg |=3D GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY_= SHIFT; - reg |=3D gicv3_its_get_cacheability() << GITS_BASER_INNER_CACHEABILITY= _SHIFT; + reg =3D MASK_INSR(shareability, GITS_BASER_SHAREABILITY_MASK); + reg |=3D MASK_INSR(GIC_BASER_CACHE_SameAsInner, + GITS_BASER_OUTER_CACHEABILITY_MASK); + reg |=3D MASK_INSR(cacheability, GITS_BASER_INNER_CACHEABILITY_MASK); =20 order =3D get_order_from_bytes(max(ITS_CMD_QUEUE_SZ, SZ_64K)); - buffer =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + buffer =3D alloc_xenheap_pages(order, memflags); if ( !buffer ) return NULL; =20 @@ -437,8 +423,8 @@ static void *its_map_cbaser(struct host_its *its) /* The ITS BASE registers work with page sizes of 4K, 16K or 64K. */ #define BASER_PAGE_BITS(sz) ((sz) * 2 + 12) =20 -static int its_map_baser(void __iomem *basereg, uint64_t regc, - unsigned int nr_items) +static int its_map_baser(struct host_its *its, void __iomem *basereg, + uint64_t regc, unsigned int nr_items) { uint64_t attr, reg; unsigned int entry_size =3D GITS_BASER_ENTRY_SIZE(regc); @@ -446,10 +432,14 @@ static int its_map_baser(void __iomem *basereg, uint6= 4_t regc, unsigned int table_size; unsigned int order; void *buffer; + uint64_t cacheability =3D gicv3_mem_get_cacheability(its->quirk_flags); + uint64_t shareability =3D gicv3_mem_get_shareability(its->quirk_flags); + unsigned int memflags =3D gicv3_mem_get_alloc_flags(its->quirk_flags); =20 - attr =3D gicv3_its_get_shareability() << GITS_BASER_SHAREABILITY_SHIF= T; - attr |=3D GIC_BASER_CACHE_SameAsInner << GITS_BASER_OUTER_CACHEABILITY= _SHIFT; - attr |=3D gicv3_its_get_cacheability() << GITS_BASER_INNER_CACHEABILIT= Y_SHIFT; + attr =3D MASK_INSR(shareability, GITS_BASER_SHAREABILITY_MASK); + attr |=3D MASK_INSR(GIC_BASER_CACHE_SameAsInner, + GITS_BASER_OUTER_CACHEABILITY_MASK); + attr |=3D MASK_INSR(cacheability, GITS_BASER_INNER_CACHEABILITY_MASK); =20 /* * Setup the BASE register with the attributes that we like. Then read @@ -463,7 +453,7 @@ retry: table_size =3D min(table_size, 256U << BASER_PAGE_BITS(pagesz)); =20 order =3D get_order_from_bytes(max(table_size, BIT(BASER_PAGE_BITS(pag= esz), U))); - buffer =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + buffer =3D alloc_xenheap_pages(order, memflags); if ( !buffer ) return -ENOMEM; =20 @@ -562,7 +552,7 @@ static int gicv3_its_init_single_its(struct host_its *h= w_its) if ( ret ) return ret; =20 - gicv3_its_enable_quirks(hw_its); + gicv3_its_collect_quirks(hw_its); =20 reg =3D readq_relaxed(hw_its->its_base + GITS_TYPER); hw_its->devid_bits =3D GITS_TYPER_DEVICE_ID_BITS(reg); @@ -584,18 +574,19 @@ static int gicv3_its_init_single_its(struct host_its = *hw_its) case GITS_BASER_TYPE_NONE: continue; case GITS_BASER_TYPE_DEVICE: - ret =3D its_map_baser(basereg, reg, BIT(hw_its->devid_bits, UL= )); + ret =3D its_map_baser(hw_its, basereg, reg, + BIT(hw_its->devid_bits, UL)); if ( ret ) return ret; break; case GITS_BASER_TYPE_COLLECTION: - ret =3D its_map_baser(basereg, reg, num_possible_cpus()); + ret =3D its_map_baser(hw_its, basereg, reg, num_possible_cpus(= )); if ( ret ) return ret; break; /* In case this is a GICv4, provide a (dummy) vPE table as well. */ case GITS_BASER_TYPE_VCPU: - ret =3D its_map_baser(basereg, reg, 1); + ret =3D its_map_baser(hw_its, basereg, reg, 1); if ( ret ) return ret; break; @@ -730,6 +721,7 @@ int gicv3_its_map_guest_device(struct domain *d, struct its_device *dev =3D NULL; struct rb_node **new =3D &d->arch.vgic.its_devices.rb_node, *parent = =3D NULL; int i, ret =3D -ENOENT; /* "i" must be signed to check for >=3D 0= below. */ + unsigned int memflags; unsigned int order; =20 hw_its =3D gicv3_its_find_by_doorbell(host_doorbell); @@ -793,8 +785,9 @@ int gicv3_its_map_guest_device(struct domain *d, ret =3D -ENOMEM; =20 /* An Interrupt Translation Table needs to be 256-byte aligned. */ + memflags =3D gicv3_mem_get_alloc_flags(hw_its->quirk_flags); order =3D get_order_from_bytes(max(nr_events * hw_its->itte_size, 256U= L)); - itt_addr =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + itt_addr =3D alloc_xenheap_pages(order, memflags); if ( !itt_addr ) goto out_unlock; =20 @@ -1206,8 +1199,6 @@ int gicv3_its_init(void) return ret; } =20 - gicv3_its_validate_quirks(); - return 0; } =20 diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 9ee338edc2..35f93e4756 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -78,9 +78,29 @@ struct lpi_redist_data { =20 static DEFINE_PER_CPU(struct lpi_redist_data, lpi_redist); =20 +/* + * Host LPI flags are scoped to shared LPI/Redistributor state, not to an + * ITS instance. Arm IHI 0069H.b section 5.1.1 says "LPI configuration is + * global". Section 12.11.33 (GICR_PROPBASER) makes mismatched values + * UNPREDICTABLE for Redistributors that share an LPI Configuration table + * while GICR_CTLR.EnableLPIs =3D=3D 1. Section 12.11.32 (GICR_PENDBASER) + * similarly makes mismatched OuterCache, Shareability or InnerCache values + * across Redistributors UNPREDICTABLE while GICR_CTLR.EnableLPIs =3D=3D 1. + * + * Keep this policy in the LPI code and accumulate only explicit LPI/RD + * restrictions into it. Per-ITS restrictions stay in host_its::quirk_flags + * for GITS_CBASER, GITS_BASER and ITT memory. + */ +static uint32_t __ro_after_init host_lpi_flags; + #define MAX_NR_HOST_LPIS (lpi_data.max_host_lpi_ids - LPI_OFFSET) #define HOST_LPIS_PER_PAGE (PAGE_SIZE / sizeof(union host_lpi)) =20 +void __init gicv3_lpi_update_host_flags(uint32_t flags) +{ + host_lpi_flags |=3D flags; +} + static union host_lpi *gic_get_host_lpi(uint32_t plpi) { union host_lpi *block; @@ -228,6 +248,7 @@ static int gicv3_lpi_allocate_pendtable(unsigned int cp= u) { void *pendtable; unsigned int order; + unsigned int memflags =3D gicv3_mem_get_alloc_flags(host_lpi_flags); =20 if ( per_cpu(lpi_redist, cpu).pending_table ) return -EBUSY; @@ -239,7 +260,7 @@ static int gicv3_lpi_allocate_pendtable(unsigned int cp= u) * physically contiguous memory. */ order =3D get_order_from_bytes(max(lpi_data.max_host_lpi_ids / 8, (uns= igned long)SZ_64K)); - pendtable =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + pendtable =3D alloc_xenheap_pages(order, memflags); if ( !pendtable ) return -ENOMEM; =20 @@ -262,6 +283,8 @@ static int gicv3_lpi_set_pendtable(void __iomem *rdist_= base) { const void *pendtable =3D this_cpu(lpi_redist).pending_table; uint64_t val; + uint64_t cacheability =3D gicv3_mem_get_cacheability(host_lpi_flags); + uint64_t shareability =3D gicv3_mem_get_shareability(host_lpi_flags); =20 /* * The memory should have been allocated while preparing the CPU (or @@ -275,9 +298,10 @@ static int gicv3_lpi_set_pendtable(void __iomem *rdist= _base) =20 ASSERT(!(virt_to_maddr(pendtable) & ~GENMASK(51, 16))); =20 - val =3D gicv3_its_get_cacheability() << GICR_PENDBASER_INNER_CACHEABI= LITY_SHIFT; - val |=3D GIC_BASER_CACHE_SameAsInner << GICR_PENDBASER_OUTER_CACHEABIL= ITY_SHIFT; - val |=3D gicv3_its_get_shareability() << GICR_PENDBASER_SHAREABILITY_S= HIFT; + val =3D MASK_INSR(cacheability, GICR_PENDBASER_INNER_CACHEABILITY_MAS= K); + val |=3D MASK_INSR(GIC_BASER_CACHE_SameAsInner, + GICR_PENDBASER_OUTER_CACHEABILITY_MASK); + val |=3D MASK_INSR(shareability, GICR_PENDBASER_SHAREABILITY_MASK); val |=3D GICR_PENDBASER_PTZ; val |=3D virt_to_maddr(pendtable); =20 @@ -304,10 +328,13 @@ static int gicv3_lpi_set_proptable(void __iomem * rdi= st_base) { uint64_t reg; unsigned int order; + uint64_t cacheability =3D gicv3_mem_get_cacheability(host_lpi_flags); + uint64_t shareability =3D gicv3_mem_get_shareability(host_lpi_flags); =20 - reg =3D gicv3_its_get_cacheability() << GICR_PROPBASER_INNER_CACHEABI= LITY_SHIFT; - reg |=3D GIC_BASER_CACHE_SameAsInner << GICR_PROPBASER_OUTER_CACHEABIL= ITY_SHIFT; - reg |=3D gicv3_its_get_shareability() << GICR_PROPBASER_SHAREABILITY_S= HIFT; + reg =3D MASK_INSR(cacheability, GICR_PROPBASER_INNER_CACHEABILITY_MAS= K); + reg |=3D MASK_INSR(GIC_BASER_CACHE_SameAsInner, + GICR_PROPBASER_OUTER_CACHEABILITY_MASK); + reg |=3D MASK_INSR(shareability, GICR_PROPBASER_SHAREABILITY_MASK); =20 /* * The property table is shared across all redistributors, so allocate @@ -317,9 +344,10 @@ static int gicv3_lpi_set_proptable(void __iomem * rdis= t_base) { /* The property table holds one byte per LPI. */ void *table; + unsigned int memflags =3D gicv3_mem_get_alloc_flags(host_lpi_flags= ); =20 order =3D get_order_from_bytes(max(lpi_data.max_host_lpi_ids, (uns= igned long)SZ_4K)); - table =3D alloc_xenheap_pages(order, gicv3_its_get_memflags()); + table =3D alloc_xenheap_pages(order, memflags); =20 if ( !table ) return -ENOMEM; diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/a= sm/gic_v3_its.h index fc5a84892c..3e8dcc4ae9 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -105,13 +105,15 @@ #define GICV3_ITS_SIZE SZ_128K =20 #include +#include #include =20 #define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0) #define HOST_ITS_USES_PTA (1U << 1) =20 -#define HOST_ITS_WORKAROUND_NC_NS (1U << 0) -#define HOST_ITS_WORKAROUND_32BIT_ADDR (1U << 1) +/* GICv3 memory-related quirk flags. */ +#define GICV3_QUIRK_MEM_NC_NS (1U << 0) +#define GICV3_QUIRK_MEM_32BIT_ADDR (1U << 1) =20 /* We allocate LPIs on the hosts in chunks of 32 to reduce handling overhe= ad. */ #define LPI_BLOCK 32U @@ -128,6 +130,11 @@ struct host_its { unsigned int itte_size; spinlock_t cmd_lock; void *cmd_buf; + /* + * Workaround flags scoped to this ITS instance, including memory + * accessed through GITS_CBASER, GITS_BASER and ITT memory. + */ + uint32_t quirk_flags; unsigned int flags; }; =20 @@ -157,6 +164,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base); /* Initialize the host structures for LPIs and the host ITSes. */ int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits); int gicv3_its_init(void); +void __init gicv3_lpi_update_host_flags(uint32_t flags); =20 /* Store the physical address and ID for each redistributor as read from D= T. */ void gicv3_set_redist_address(paddr_t address, unsigned int redist_id); @@ -199,10 +207,9 @@ struct pending_irq *gicv3_assign_guest_event(struct do= main *d, void gicv3_lpi_update_host_entry(uint32_t host_lpi, int domain_id, uint32_t virt_lpi); =20 -/* ITS quirks handling. */ -uint64_t gicv3_its_get_cacheability(void); -uint64_t gicv3_its_get_shareability(void); -unsigned int gicv3_its_get_memflags(void); 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That is too coarse for integrations where the same GIC IP block can appear in several platforms but the workaround is only valid for a subset of boards. Replace the fixed IIDR fields with a generic match(hw_its, data) callback and an opaque data pointer. Add an IIDR matcher as a reusable building block and use it from the R-Car Gen4 matcher after checking the Renesas machine compatibles. The R-Car Gen4 platform refinement is DT-only; ACPI-discovered ITSes do not match it. Keep first-match semantics explicit. Assert that non-sentinel entries provide a matcher and that IIDR matching receives match data, but keep runtime guards so a malformed table entry does not become a NULL function call or NULL data dereference in non-debug builds. The matched entry still supplies separate ITS and LPI flags; this patch only changes how the entry is selected. Signed-off-by: Mykola Kvach --- Changes in v2: - Replace v1's optional platform callback plus fixed IIDR/mask fields with a single generic match(hw_its, data) selector. - Add a reusable IIDR matcher and use it after the R-Car Gen4 machine-compatible checks. - Document that the R-Car Gen4 quirk remains DT-only. - Keep the split ITS and host LPI quirk scopes when applying the matched entry. - Document first-match ordering in the lookup path and guard against entries without a match callback or IIDR match data. --- xen/arch/arm/gic-v3-its.c | 67 +++++++++++++++++++++++++++++++-------- 1 file changed, 53 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index dc48a84789..e055914763 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -53,8 +53,8 @@ struct its_device { =20 struct its_quirk { const char *desc; - uint32_t iidr; - uint32_t mask; + bool (*match)(const struct host_its *hw_its, const void *data); + const void *data; uint32_t its_flags; /* * lpi_flags are ORed into the global host LPI policy and must only @@ -64,11 +64,48 @@ struct its_quirk { uint32_t lpi_flags; }; =20 +struct its_quirk_match_iidr { + uint32_t iidr; + uint32_t mask; +}; + +static bool __init gicv3_its_match_iidr(const struct host_its *hw_its, + const void *data) +{ + const struct its_quirk_match_iidr *match; + uint32_t iidr; + + ASSERT(data); + + match =3D data; + iidr =3D readl_relaxed(hw_its->its_base + GITS_IIDR); + + return (iidr & match->mask) =3D=3D match->iidr; +} + +static bool __init gicv3_its_match_quirk_gen4(const struct host_its *hw_it= s, + const void *data) +{ + if ( !hw_its->dt_node ) + return false; + + if ( !dt_machine_is_compatible("renesas,r8a779f0") && + !dt_machine_is_compatible("renesas,r8a779g0") ) + return false; + + return gicv3_its_match_iidr(hw_its, data); +} + +static const struct its_quirk_match_iidr rcar_gen4_iidr =3D { + .iidr =3D 0x0201743b, + .mask =3D 0xffffffffU, +}; + static const struct its_quirk its_quirks[] =3D { { - .desc =3D "R-Car Gen4", - .iidr =3D 0x0201743b, - .mask =3D 0xffffffffU, + .desc =3D "R-Car Gen4", + .match =3D gicv3_its_match_quirk_gen4, + .data =3D &rcar_gen4_iidr, .its_flags =3D GICV3_QUIRK_MEM_NC_NS | GICV3_QUIRK_MEM_32BIT_ADDR, .lpi_flags =3D GICV3_QUIRK_MEM_NC_NS | GICV3_QUIRK_MEM_32BIT_ADDR, }, @@ -77,18 +114,21 @@ static const struct its_quirk its_quirks[] =3D { } }; =20 -static const struct its_quirk *__init gicv3_its_find_quirk(uint32_t iidr) +static const struct its_quirk *__init gicv3_its_find_quirk( + const struct host_its *hw_its) { - const struct its_quirk *quirks =3D its_quirks; + const struct its_quirk *quirk; =20 /* - * The first matching quirk wins. More specific quirks must be listed - * before broader IIDR-only entries. + * The first matching quirk wins. Entries that match a specific platfo= rm + * must be listed before broader IIDR-only entries. */ - for ( ; quirks->desc; quirks++ ) + for ( quirk =3D its_quirks; quirk->desc; quirk++ ) { - if ( quirks->iidr =3D=3D (quirks->mask & iidr) ) - return quirks; + ASSERT(quirk->match); + + if ( quirk->match && quirk->match(hw_its, quirk->data) ) + return quirk; } =20 return NULL; @@ -96,8 +136,7 @@ static const struct its_quirk *__init gicv3_its_find_qui= rk(uint32_t iidr) =20 static void __init gicv3_its_collect_quirks(struct host_its *hw_its) { - uint32_t iidr =3D readl_relaxed(hw_its->its_base + GITS_IIDR); - const struct its_quirk *quirk =3D gicv3_its_find_quirk(iidr); + const struct its_quirk *quirk =3D gicv3_its_find_quirk(hw_its); =20 if ( quirk ) { --=20 2.43.0 From nobody Sat May 30 11:21:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779928124; cv=none; d=zohomail.com; s=zohoarc; b=hNw66FqPScajbLavOw5q6ZqAJ5SFuBR6upgGUjErEWUUq6q89M2rmMq+Sz1g0MPY+xD8Ys/S6QaUbAemdZv8YxzSE5/w/QKq0oAxLk1ps+JruuQtZ2n3Oupp7Y7x9KpvPGA4GEnAV93MTpv+XSjPCV5uZb1vo4EQSJOuQElIPC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779928124; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bPfJ90vz5LA/T++PBxy4wc5LMm+G5DLn0jpA+XJFuNE=; b=cGYYYFVWwGQC9hdKg2s/QH0jP+NCgGKAZwb7COMzWgLVyHvYc0wkWuqrkTHfwOInjvVrK46CmpLitxEqt+pOvKUzFSbcC5bdcCZBXXoArwoOVPKi4SBZIV3W0xqcHvKp/tDrgOt4kGp3081ADSp31+ATRLw8f3OxoYlvu0XWzIA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1779928124751697.8836460637028; Wed, 27 May 2026 17:28:44 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1320867.1588003 (Exim 4.92) (envelope-from ) id 1wSObi-0008AJ-42; Thu, 28 May 2026 00:28:18 +0000 Received: by outflank-mailman (output) from mailman id 1320867.1588003; Thu, 28 May 2026 00:28:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wSObi-0008A6-02; Thu, 28 May 2026 00:28:18 +0000 Received: by outflank-mailman (input) for mailman id 1320867; Thu, 28 May 2026 00:28:16 +0000 Received: from mx.expurgate.net ([194.145.224.20]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wSObg-0007lo-3E for xen-devel@lists.xenproject.org; Thu, 28 May 2026 00:28:16 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wSObe-006N05-BN for xen-devel@lists.xenproject.org; Thu, 28 May 2026 02:28:14 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 6a178bc5-e002-0a2a0a5209dd-0a2a4508c6ae-38 for ; Thu, 28 May 2026 02:28:14 +0200 Received: from [209.85.208.42] (helo=mail-ed1-f42.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 6a178c1e-63b5-0a2a45080019-d155d02ab409-3 for ; Thu, 28 May 2026 02:28:14 +0200 Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-68aad378a26so928249a12.0 for ; Wed, 27 May 2026 17:28:14 -0700 (PDT) Received: from EPUAKYIW02F7.. ([45.12.25.69]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bddc5ece286sm655205266b.40.2026.05.27.17.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 17:28:13 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779928094; x=1780532894; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bPfJ90vz5LA/T++PBxy4wc5LMm+G5DLn0jpA+XJFuNE=; b=BXD4QNGsvIDsUXTrirQe9itgDHx3UchKuz7kh5pCGLXeN+YKcTho3L72dPg+VLFTzu A9X0jzfHWOQP2QLnPKT62qb/kxXs/vsvF44WhGE1M/Ad4y4vt3Ym95NsHXhZhza65ngQ mynaFabY+teMH8tOddVhPfHZ2OahGTothJLVaiWO6vLaOTrrML56kobXJLL3hBBPnqRk MCdV6hQs3TqJIuazdF+yGRsnurJ1KW1N6ZcIn+mEW+vcxDAdV15Rk3li3ETvwLp7pibG sOy7kmD8kh0azeZKDMRel5WO4yjKVq+j+be/lJ+2sRh7aE0CSgVaomCHI/Oua+yRGoIH 5aLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779928094; x=1780532894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=bPfJ90vz5LA/T++PBxy4wc5LMm+G5DLn0jpA+XJFuNE=; b=PQKnwF+CLO8wDTohClNDGRyEhmQ3g/XrS86aQrpVUloLi2SsIQ8cJIuLdvJkhE5G9D MDo2m7qXsFFd23ntkbsv5F/DOsFaHzlflh+Pw42p/GQ+S5yay1pE7rMOg1nTD/DGUFug Qdoroq5qZK1NheG6aZE6mAck/jBmveuwm4qvr/NCIRGJUWOAsJeXDDh3ClO1ii4TmaZp NdWIpGVAnwHsXc3FmGJkTRLYTkK1jj9wGDO0wSp8nM4YgM8mhvLNLiNe2dJ3Lz77DPCd vT5/uABpTrmDNMjlu3yaq3AWjbycCvXzgf+BfDrblIsw7/kqRi+r6Ssb6vBk4W8fpqc+ mG6Q== X-Gm-Message-State: AOJu0Yyk0R2g6OGvQ5/jYRikrVWlwPHsvfTdlky3XIC9G/FPI5J6NWnH nRVsXOQFsudmF3Qe0+KIVyMXAQvS/lQCrBzimVn/gX7C9q+HzkRsplH4e3rk/g== X-Gm-Gg: Acq92OGHgy3kHozN49LBSs1sWjgg0EGlaMyUqKWLDge2ARVkQY4ZsJAmIluaY4zn5RI S7ryjI7V5tjr0i1JrhlGC8iyOGNHVLRf6thtbRRVsirURGgvb5nFh9WM+9pqNmAkshM2e5qWqsB dXBpl9cnpMlkjnxsCQHAJMgnn2vgpWNzjx/l3qGR+sXBdAY0p4fPXmM6BLOqz2NczlfIqAN7Uq6 hoLxosWrm/ujqdHIVHVTH5bpmgLnAIPwUBNQnzj1QVxBjnfyKTXofh/yozsdsQBRVlAkngMXThc lA0Q1YzxoOeRhp5v95Rahym/uEyoO6vF7aqE1MEJTOBMkfJroOdzla8PqcFSWMrO9gpbEcvdrKa egipMO94GahEczt59W0LaKC4cZqrOYqVTB8Q7B5QUe2cZCpNq72mDJ8JJKSmVIP6S91Qnv53EKu yyV+NAt9Ov/eXhn4eYRkt8iBSk80iE7M7DfGnM X-Received: by 2002:a17:907:b5a9:b0:bd5:7a3:a58b with SMTP id a640c23a62f3a-bdd269b6a00mr1129029066b.46.1779928093812; Wed, 27 May 2026 17:28:13 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Luca Fancellu , Volodymyr Babchuk Subject: [PATCH v2 4/4] xen/arm: its: handle dma-noncoherent on GIC and ITS nodes Date: Thu, 28 May 2026 03:25:52 +0300 Message-ID: <43b0e8f6b25588ba1cfc22d367e5ed6b303a4978.1779922874.git.mykola_kvach@epam.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c1860d/1779928094-BFD7BDB1-690D32EC/0/0 X-purgate-type: clean X-purgate-size: 5082 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779928127171154100 Content-Type: text/plain; charset="utf-8" From: Mykola Kvach The DT dma-noncoherent property describes the bus coherency of the device represented by the node. On an ITS subnode, that is memory accessed by that ITS, so add GICV3_QUIRK_MEM_NC_NS to the corresponding host_its before programming GITS tables and allocating ITTs. When the property is present on the top-level GIC node, it describes the Redistributor side of the LPI path. Collect it in gicv3_lpi_init_host_lpis() and apply it only to the host LPI policy used for GICR_PROPBASER and GICR_PENDBASER setup. Do not inherit the property between parent and child nodes: ITS-node non-coherency does not change the global host LPI policy, and GIC-node non-coherency does not change per-ITS quirk_flags. ACPI is left unchanged; this patch only consumes the DT dma-noncoherent property. Signed-off-by: Mykola Kvach --- Changes in v2: - Split v1's dma-noncoherent handling into explicit ITS-node and GIC-node scopes. - Apply an ITS subnode property only to the matching host_its quirk_flags. - Collect the top-level GIC property from gic-v3-lpi.c before host LPI allocations use host_lpi_flags. --- xen/arch/arm/gic-v3-its.c | 21 +++++++++++++++++++-- xen/arch/arm/gic-v3-lpi.c | 22 +++++++++++++++++++++- 2 files changed, 40 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index e055914763..606b127487 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -134,6 +134,21 @@ static const struct its_quirk *__init gicv3_its_find_q= uirk( return NULL; } =20 +static void __init gicv3_its_collect_fw_attrs(struct host_its *hw_its) +{ + /* + * An ITS subnode property describes memory transactions made by that = ITS. + * Do not inherit it into the global host LPI/Redistributor policy. + */ + if ( !hw_its->dt_node || + !dt_property_read_bool(hw_its->dt_node, "dma-noncoherent") ) + return; + + hw_its->quirk_flags |=3D GICV3_QUIRK_MEM_NC_NS; + printk("GICv3: ITS @%#"PRIpaddr" marked dma-noncoherent\n", + hw_its->addr); +} + static void __init gicv3_its_collect_quirks(struct host_its *hw_its) { const struct its_quirk *quirk =3D gicv3_its_find_quirk(hw_its); @@ -144,6 +159,8 @@ static void __init gicv3_its_collect_quirks(struct host= _its *hw_its) gicv3_lpi_update_host_flags(quirk->lpi_flags); printk("GICv3: enabling workaround for ITS: %s\n", quirk->desc); } + + gicv3_its_collect_fw_attrs(hw_its); } =20 uint64_t gicv3_mem_get_cacheability(uint32_t flags) @@ -578,7 +595,7 @@ static int gicv3_disable_its(struct host_its *hw_its) return -ETIMEDOUT; } =20 -static int gicv3_its_init_single_its(struct host_its *hw_its) +static int __init gicv3_its_init_single_its(struct host_its *hw_its) { uint64_t reg; int i, ret; @@ -1221,7 +1238,7 @@ static void gicv3_its_acpi_init(void) =20 #endif =20 -int gicv3_its_init(void) +int __init gicv3_its_init(void) { struct host_its *hw_its; int ret; diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 35f93e4756..c6f17b9b2d 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -7,7 +7,9 @@ * Copyright (C) 2016,2017 - ARM Ltd */ =20 +#include #include +#include #include #include #include @@ -101,6 +103,20 @@ void __init gicv3_lpi_update_host_flags(uint32_t flags) host_lpi_flags |=3D flags; } =20 +static void __init gicv3_lpi_collect_fw_attrs(void) +{ + /* + * A top-level GIC node property describes the Redistributor side of t= he + * LPI path. Do not inherit it into per-ITS policy. + */ + if ( !acpi_disabled || + !dt_property_read_bool(dt_interrupt_controller, "dma-noncoherent"= ) ) + return; + + gicv3_lpi_update_host_flags(GICV3_QUIRK_MEM_NC_NS); + printk("GICv3: GIC node marked dma-noncoherent for host LPI tables\n"); +} + static union host_lpi *gic_get_host_lpi(uint32_t plpi) { union host_lpi *block; @@ -442,7 +458,7 @@ integer_param("max_lpi_bits", max_lpi_bits); * to the page with the actual "union host_lpi" entries. Our LPI limit * avoids excessive memory usage. */ -int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) +int __init gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) { unsigned int nr_lpi_ptrs; int rc; @@ -450,6 +466,10 @@ int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bit= s) /* We rely on the data structure being atomically accessible. */ BUILD_BUG_ON(sizeof(union host_lpi) > sizeof(unsigned long)); =20 + gicv3_lpi_collect_fw_attrs(); + if ( host_lpi_flags ) + printk("GICv3: host LPI workaround flags: %#x\n", host_lpi_flags); + /* * An implementation needs to support at least 14 bits of LPI IDs. * Tell the user about it, the actual number is reported below. --=20 2.43.0