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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4887e80a6ebsm66704905e9.6.2026.03.31.12.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 12:04:28 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774983869; x=1775588669; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nt869+EoqKBeJ1+vQp/e7NBob2COQX9inHC/KN2XaZ0=; b=UMkObwboCxrUBhe1t0ckBDjMcYVnKr9kZOB1iJA9J/h9QJVbP1yTi+2HPacA7M+9zv 7Q+Fj2TSakAwckXIzjAv2Y17uCdTtCVHXJPtOQQnD9NhW8nVmzi3Aeoo2T4iEVBpzaTm WHkx9ee29l/NJ4jyRJhRCfZpPY8FH8BVpW1P4MWhqRMBFSiA0vy3Fr9RHTg0XWKWNXUx gcUknjGbN0urpQ6wyzVvQVPDnsR60x7O591+JFhlNAnGetx0rfPeEOBpSBDICyzmjwO7 lkPqcLx6Q6mUPOsbCk8RPyxAonp3JN34eFJWgYiFvpyFVbVi4XiuVWcsjONiuwx4Jf8r xJEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774983869; x=1775588669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Nt869+EoqKBeJ1+vQp/e7NBob2COQX9inHC/KN2XaZ0=; b=aBKxJB/BHyy5U/JrVbnsCJFZqp9x4EkwB0iisVXWt2t7E0nFZMrpON2Fi7KUWfqzMO k/CnWwxa88rRtS4GV3bf7e0TYOYKERFcnuJJc/cG8ODmXJX4HK9SjwhwcUQsclKwJ4zb +XqQ3suAqdp+4HOJamBLK8HhBhZUk7lW3Zy0lAj1eMvbqDDwTB22XNCyxyrundm3vNCH mpUc8Bm9nhUHAPbcwdkShExkP8rGO0uHMGw5iQSvVmpmtP+kd2NI0JQ45/n/EochtLr2 V/EYEhYuE9KxfWRHYOifiZfL8ip5zkH9F+qhcqWhEPSxVVTKbpax/exBGgFOKEJCh37N BRHA== X-Gm-Message-State: AOJu0YyuvaHCryNGeF1TkvjZBEgIcS+QVBUwP/AQwvQE7KFE64IsM+po jnPFW3EnEM6eOzpkc6SZVzLslf46Kh9IiK9SQ0bSxjQyy+rZgb7gMAdpiqiNsg== X-Gm-Gg: ATEYQzx/EDp/4F1L90xKzfCRbhboYsDJHSIxP8b1I9KsL+TBmWcBWDughPMCQm091dJ kX99EgyZ0LYAJ0rd3S0JK9jw4u8OhhAdrRR6ErDlmyCGWEHxrimef/Oef3oGvybb5Vxo3hXQRAi tB/69GTtdjNEvbHJQVC9X2/ikSPSOUaMOMyHLxvX7Aqt1CmeqKR2xM80Qv7J6iSZoTcgcaGlk6e oGh3fj2JL+9afoVPYiiWD3KfZeCAnym11/0/tfUywiOwrA0DwuvBhc0hfN4qKhjcJq2qwrNo68J GfVrYwh1LjAUfSQnf5cd8paI3BfS6GNuSmPVu8p7j92kG2Nlbu+SNyOgKDYq8xzQXDIvpqrXPNG pzE3NVS6M6NzGpYyAKPODMVwV9xN1olata061MF1k2OUx59jfyBWO2XcVH05seEw87Q4PL2fPgz HygbM19xsbt059Sh+Jk/Tjrxg7IQ5IzB02v7ko1Zu/tLhwxGrLzALuaAm6ZyDYl40+Yw== X-Received: by 2002:a05:600c:5303:b0:485:34b3:8587 with SMTP id 5b1f17b1804b1-48883562deamr9647415e9.10.1774983868536; Tue, 31 Mar 2026 12:04:28 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v2 1/4] xen/riscv: add exception table support Date: Tue, 31 Mar 2026 21:04:16 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1774983869-22484488-AF78F8D6/10/73395122804 X-purgate-type: spam X-purgate-size: 11353 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1774983901179158500 Content-Type: text/plain; charset="utf-8" Introduce exception table handling for RISC-V so faults from selected instructions can be recovered via fixup handlers instead of being treated as fatal. Add the RISC-V exception table format, sorting at boot to allow binary search used furthuer, and lookup from the trap handler. Update the linker script to emit the .ex_table section using introduced common EX_TABLE macro shared with other architectures. Also, reduce __start___ex_table alignment from 8 to 4 bytes to match the natural alignment of struct exception_table_entry, which contains two int32_t fields. Add inclusion of asm/extable.h to asm/bug.h to deal with compilation issue of common/virtual_region.c, which require declaration of __start___ex_table and __stop___ex_table. This implementation is based on Linux 6.16. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Corrected the name for __start_ex_table identifier in the commit message. - Droped plural where extables is used. - Added inclusuion of to deal with compilation (nothing declares __start___ex_table and __stop___ex_table) of common/virtual_reg= ion.c. - Use long for delta variable inside swap_ex in extable.c. - To take into acoount live-patching code: - s/sort_extable/sort_exception_tables. - Introduce sort_exception_table() as liveaptch code requires it and re-use it inside sort_exception_tables(). - Drop cmp_ex_search() and rename cmp_ex_sort() to cmp_ex(). Rename local variable l and r inside cmp_ex(). - Identation fixes. - prefer sizeof() over sizeof() in calls of bsearch() and sort(). - Return back defintion of asm_extable() for __ASSEMBLER__ case. - Correct the comment above declaration of struct exception_table_entry. - Drop else in do_trap() before "if ( fixup_exception() )" to visually sepa= rate the set of checks. - Align start of exception table section by 4-bytes as exception table stru= ct contains two 4 bytes integers. - Make extable.o compile unconditionally. - Drop ifdef HAS_EX_TABLE in extable.h as extable.o is always compiled. - Drop ifdef around defintion of EX_TABLE. - Drop __init for cmp_ex as it is now used in fixup_exception() which isn't marked as __init. - Return void instead of bool for ex_handler_fixup() as this function always returns true. - Update the comment above defintion of struct exception_table_entry() to be more accurate. - Add inclusion of asm/extable.h to asm/bug.h to deal with compilation issue of common/virtual_region.c, which require declaration of __start___ex_tab= le and __stop___ex_table. --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/Makefile | 1 + xen/arch/riscv/extable.c | 85 ++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/bug.h | 2 + xen/arch/riscv/include/asm/extable.h | 58 +++++++++++++++++++ xen/arch/riscv/setup.c | 3 + xen/arch/riscv/traps.c | 5 ++ xen/arch/riscv/xen.lds.S | 3 + xen/arch/x86/xen.lds.S | 6 +- xen/include/xen/xen.lds.h | 6 ++ 10 files changed, 165 insertions(+), 5 deletions(-) create mode 100644 xen/arch/riscv/extable.c create mode 100644 xen/arch/riscv/include/asm/extable.h diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 89876b32175d..a5e87c1757f7 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -4,6 +4,7 @@ config RISCV select GENERIC_BUG_FRAME select GENERIC_UART_INIT select HAS_DEVICE_TREE_DISCOVERY + select HAS_EX_TABLE select HAS_PMAP select HAS_UBSAN select HAS_VMAP diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index ffbd7062e214..04f02ad89cba 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -3,6 +3,7 @@ obj-y +=3D cpufeature.o obj-y +=3D domain.o obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o +obj-y +=3D extable.o obj-y +=3D imsic.o obj-y +=3D intc.o obj-y +=3D irq.o diff --git a/xen/arch/riscv/extable.c b/xen/arch/riscv/extable.c new file mode 100644 index 000000000000..882ae9508d19 --- /dev/null +++ b/xen/arch/riscv/extable.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define EX_FIELD(ptr, field) ((unsigned long)&(ptr)->field + (ptr)->field) + +static inline unsigned long ex_insn(const struct exception_table_entry *ex) +{ + return EX_FIELD(ex, insn); +} + +static inline unsigned long ex_fixup(const struct exception_table_entry *e= x) +{ + return EX_FIELD(ex, fixup); +} + +static void __init cf_check swap_ex(void *a, void *b) +{ + struct exception_table_entry *x =3D a, *y =3D b, tmp; + long delta =3D b - a; + + tmp =3D *x; + x->insn =3D y->insn + delta; + y->insn =3D tmp.insn - delta; + + x->fixup =3D y->fixup + delta; + y->fixup =3D tmp.fixup - delta; +} + +static int cf_check cmp_ex(const void *a, const void *b) +{ + const unsigned long insn_a =3D ex_insn(a); + const unsigned long insn_b =3D ex_insn(b); + + /* avoid overflow */ + return (insn_a > insn_b) - (insn_a < insn_b); +} + +void init_or_livepatch sort_exception_table(struct exception_table_entry *= start, + const struct exception_table_entry *stop) +{ + sort(start, stop - start, sizeof(*start), cmp_ex, swap_ex); +} + +void __init sort_exception_tables(void) +{ + sort_exception_table(__start___ex_table, __stop___ex_table); +} + +static void ex_handler_fixup(const struct exception_table_entry *ex, + struct cpu_user_regs *regs) +{ + regs->sepc =3D ex_fixup(ex); +} + +bool fixup_exception(struct cpu_user_regs *regs) +{ + unsigned long pc =3D regs->sepc; + const struct virtual_region *region =3D find_text_region(pc); + const struct exception_table_entry *ex; + struct exception_table_entry key; + + if ( !region || !region->ex ) + return false; + + key.insn =3D pc - (unsigned long)&key.insn; + + ex =3D bsearch(&key, region->ex, region->ex_end - region->ex, sizeof(k= ey), + cmp_ex); + + if ( !ex ) + return false; + + ex_handler_fixup(ex, regs); + + return true; +} diff --git a/xen/arch/riscv/include/asm/bug.h b/xen/arch/riscv/include/asm/= bug.h index 6ec8adc528a9..e6f286881662 100644 --- a/xen/arch/riscv/include/asm/bug.h +++ b/xen/arch/riscv/include/asm/bug.h @@ -9,6 +9,8 @@ =20 #ifndef __ASSEMBLER__ =20 +#include + #define BUG_INSTR "unimp" =20 /* diff --git a/xen/arch/riscv/include/asm/extable.h b/xen/arch/riscv/include/= asm/extable.h new file mode 100644 index 000000000000..4f50f84e69f2 --- /dev/null +++ b/xen/arch/riscv/include/asm/extable.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ASM__RISCV__ASM_EXTABLE_H +#define ASM__RISCV__ASM_EXTABLE_H + +#ifdef __ASSEMBLER__ + +#define ASM_EXTABLE(insn, fixup) \ + .pushsection .ex_table, "a"; \ + .balign 4; \ + .long ((insn) - .); \ + .long ((fixup) - .); \ + .popsection; + +.macro asm_extable, insn, fixup + ASM_EXTABLE(\insn, \fixup) +.endm + +#else /* __ASSEMBLER__ */ + +#include +#include + +struct cpu_user_regs; + +#define ASM_EXTABLE(insn, fixup) \ + ".pushsection .ex_table, \"a\"\n" \ + ".balign 4\n" \ + ".long ((" #insn ") - .)\n" \ + ".long ((" #fixup ") - .)\n" \ + ".popsection\n" + +/* + * The exception table consists of pairs of relative offsets: the first + * is the relative offset to an instruction that is allowed to fault, + * and the second is the relative offset at which the program should + * continue. No general-purpose registers are modified by the exception + * handling mechanism itself, so it is up to the fixup code to handle + * any necessary state cleanup. + * + * The exception table and fixup code live out of line with the main + * instruction path. This means when everything is well, we don't even + * have to jump over them. Further, they do not intrude on our cache or + * tlb entries. + */ +struct exception_table_entry { + int32_t insn, fixup; +}; + +extern struct exception_table_entry __start___ex_table[]; +extern struct exception_table_entry __stop___ex_table[]; + +void sort_exception_tables(void); +bool fixup_exception(struct cpu_user_regs *regs); + +#endif /* __ASSEMBLY__ */ + +#endif /* ASM__RISCV__ASM_EXTABLE_H */ diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index cae49bb29626..56a0907a855f 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -19,6 +19,7 @@ =20 #include =20 +#include #include #include #include @@ -81,6 +82,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 smp_prepare_boot_cpu(); =20 + sort_exception_tables(); + set_cpuid_to_hartid(0, bootcpu_id); =20 trap_init(); diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 326f2be62823..d35c013e1399 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -12,6 +12,7 @@ #include #include =20 +#include #include #include #include @@ -217,6 +218,10 @@ void do_trap(struct cpu_user_regs *cpu_regs) =20 break; } + + if ( fixup_exception(cpu_regs) ) + break; + fallthrough; default: if ( cause & CAUSE_IRQ_FLAG ) diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index 331a7d63d3c9..65f136dce9f7 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -74,6 +74,9 @@ SECTIONS .data.ro_after_init : { __ro_after_init_start =3D .; *(.data.ro_after_init) + + EX_TABLE + . =3D ALIGN(PAGE_SIZE); __ro_after_init_end =3D .; } : text diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S index c326538ebbb2..b9e888e5962f 100644 --- a/xen/arch/x86/xen.lds.S +++ b/xen/arch/x86/xen.lds.S @@ -113,11 +113,7 @@ SECTIONS __ro_after_init_start =3D .; *(.data.ro_after_init) =20 - . =3D ALIGN(8); - /* Exception table */ - __start___ex_table =3D .; - *(.ex_table) - __stop___ex_table =3D .; + EX_TABLE =20 . =3D ALIGN(PAGE_SIZE); __ro_after_init_end =3D .; diff --git a/xen/include/xen/xen.lds.h b/xen/include/xen/xen.lds.h index 136849ecd515..ea11e3fb6213 100644 --- a/xen/include/xen/xen.lds.h +++ b/xen/include/xen/xen.lds.h @@ -219,4 +219,10 @@ #define VPCI_ARRAY #endif =20 +#define EX_TABLE \ + . =3D ALIGN(4); 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Introduce csr_read_safe() which attempts to read a CSR and relies on the exception table mechanism to safely recover if the access faults. This helper allows Xen to probe CSR availability without taking a fatal trap and will be used for feature detection during early boot as we can't always rely on what is in riscv,isa string in DTS. While touching the header, reorder the include directives to follow the usual Xen style. Signed-off-by: Oleksii Kurochko --- Changes in v2: - s/extables.h/extable.h. - s/csr_allowed_read/csr_read_safe() to follow the common nomenclature. - asm/asm_inline in csr_allowed_safe(). - Drop the comment inside csr_allowed_safe(). - Add ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT - Drop memory clobber as a memory which is going to be changed is explicit= ly mentioned in output list. - Rename local variable error to allowed. --- xen/arch/riscv/include/asm/csr.h | 36 +++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/= csr.h index 01876f828981..1d47f70f7251 100644 --- a/xen/arch/riscv/include/asm/csr.h +++ b/xen/arch/riscv/include/asm/csr.h @@ -6,8 +6,10 @@ #ifndef ASM__RISCV__CSR_H #define ASM__RISCV__CSR_H =20 -#include #include + +#include +#include #include =20 #ifndef __ASSEMBLER__ @@ -78,6 +80,38 @@ : "memory" ); \ }) =20 +static always_inline bool csr_read_safe(unsigned long csr, + unsigned long *val) +{ +#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT + asm_inline goto ( + "1: csrr %[val], %[csr]\n" + ASM_EXTABLE(1b, %l[fault]) + : [val] "=3D&r" (*val) + : [csr] "i" (csr) + : + : fault ); + + return true; + + fault: + return false; +#else + bool allowed =3D false; + + asm_inline volatile ( + "1: csrr %[val], %[csr]\n" + " li %[allowed], 1\n" + "2:\n" + ASM_EXTABLE(1b, 2b) + : [val] "=3D&r" (*val), [allowed] "+r" (allowed) + : [csr] "i" (csr) + : ); + + return allowed; +#endif +} + #endif /* __ASSEMBLER__ */ =20 #endif /* ASM__RISCV__CSR_H */ --=20 2.53.0 From nobody Wed Apr 1 23:29:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1774983893; cv=none; d=zohomail.com; s=zohoarc; b=UTKWyl6KvzQvRiI80K9UWlw/LxX29zaW+ZZcUCxOn4kMjysxQywFRWw8+9isshplOoif85V8fqNMLL/6lzGXh1Vfi2ZwMLXRQxMDHHsSU4ee6C8Q/HlplWn3V3Rzc9P1zzLUXYc72EucTE4396iw56Pl+eGJcFwuGrgX2H02ie8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774983893; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vDr/6yFSh7ffXnt3TkKTvjWGoxscpXmm0MBYPU21APE=; b=FBVcrHeaC6JPm5NGjorhislCE6TRRHANM+PBdUfmb21qXCV0DF8pCj6imDBAGZDViiLGbCbwy8kt5iQPY5EDMLNJ1FZuCkv4WXRa1Ra5aKl3B5t7N5FK0NV/fslwbbbaPOSValX07DmrQMxB1/MZN4sk0QBM8KHaSGXYSWmKOBo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1774983893451407.1404607935731; Tue, 31 Mar 2026 12:04:53 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1269260.1558365 (Exim 4.92) (envelope-from ) id 1w7eOA-0005Cb-99; Tue, 31 Mar 2026 19:04:34 +0000 Received: by outflank-mailman (output) from mailman id 1269260.1558365; Tue, 31 Mar 2026 19:04:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7eOA-0005CN-5v; Tue, 31 Mar 2026 19:04:34 +0000 Received: by outflank-mailman (input) for mailman id 1269260; Tue, 31 Mar 2026 19:04:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w7eO8-0004oP-6q for xen-devel@lists.xenproject.org; Tue, 31 Mar 2026 19:04:32 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7eO7-002qYo-J1 for xen-devel@lists.xenproject.org; Tue, 31 Mar 2026 21:04:31 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cc1aa3-2eae-0a2a0a5409dd-0a2a450ba5fc-44 for ; Tue, 31 Mar 2026 21:04:31 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.55.2) (envelope-from ) id 69cc1abf-ef63-0a2a450b0019-d1558036a919-3 for ; Tue, 31 Mar 2026 21:04:31 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-486fe36cfabso1092635e9.1 for ; Tue, 31 Mar 2026 12:04:31 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Additionally, SSTC can no longer be reliably disabled by removing the "sstc" string from riscv,isa, as OpenSBI probes support by attempting to access CSR_STIMECMP. Introduce a runtime probe in Xen to determine whether SSTC is available. The probe attempts to read CSR_STIMECMP using csr_read_safe(). If the access succeeds, SSTC is considered available; if a trap occurs, it is treated as unsupported. When SSTC is detected, Xen may use it internally to program timers. However, the extension is not exposed to guests because the required context switch handling for the SSTC CSRs is not yet implemented. To prevent guests from using SSTC, RISCV_ISA_EXT_sstc is cleared from the riscv_isa bitmap and in future patches from riscv_isa DTS property. As a result, the corresponding HENVCFG bit is not set and guests fall back to the SBI timer interface. Timer requests are then handled by Xen via the usual SBI interception path. Introduce set_xen_timer() to abstract how the timer is programmed, either via the SSTC extension or an SBI call. This also reduces the number of if statements in reprogram_timer(). The set_xen_timer function pointer is selected based on csr_read_safe() rather than riscv_isa_extension(). The latter reflects features supported by both Xen and the guest, while SSTC is currently only supported for Xen. Therefore, relying solely on riscv_isa_extension() would not reliably determine whether SSTC can be used. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/cpufeature.c | 33 ++++++++++++++++++++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/riscv_encoding.h | 2 ++ xen/arch/riscv/time.c | 34 ++++++++++++--------- xen/arch/riscv/vtimer.c | 7 ++++- 5 files changed, 62 insertions(+), 15 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 03e27b037be0..823af53ca18e 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -17,6 +17,7 @@ #include =20 #include +#include =20 #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -139,6 +140,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_e= xt[] =3D { RISCV_ISA_EXT_DATA(smaia), RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), + RISCV_ISA_EXT_DATA(sstc), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), }; @@ -483,6 +485,7 @@ void __init riscv_fill_hwcap(void) unsigned int i; const size_t req_extns_amount =3D ARRAY_SIZE(required_extensions); bool all_extns_available =3D true; + unsigned long tmp; =20 riscv_fill_hwcap_from_isa_string(); =20 @@ -495,6 +498,36 @@ void __init riscv_fill_hwcap(void) panic("HW capabilities parsing failed: %s\n", failure_msg); } =20 + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) + { + printk("SSTC is detected but is supported only for Xen usage not f= or " + "a guest\n"); + + /* + * As SSTC for guest isn't supported it is needed temprorary to: + * + * 1. Clear bit RISCV_ISA_EXT_sstc in riscv_isa as theoretuically = it + * could be that OpenSBI (it doesn't pass it now) or whatever r= an + * before Xen will add SSTC to riscv,isa string. This bit clear + * won't allow guest to use SSTC extension as vtimer context + * switch and restore isn't ready for that. + */ + __clear_bit(RISCV_ISA_EXT_sstc, riscv_isa); + + /* + * 2. A VS-timer interrupt becomes pending whenever the value of + * (time + htimedelta) is greater than or equal to vstimecmp CS= R. + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to + * ULONG_MAX. + * + * It should be dropped when SSTC for guests will be supported. + */ + csr_write(CSR_VSTIMECMP, ULONG_MAX); +#ifdef CONFIG_RISCV_32 + csr_write(CSR_VSTIMECMPH, ULONG_MAX); +#endif + } + for ( i =3D 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext =3D required_extensions[i]; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index ef02a3e26d2c..0c48d57a03bb 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -38,6 +38,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_smaia, RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, + RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index dd15731a86fa..d0d60ba15e62 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -396,6 +396,8 @@ #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSTIMECMPH 0x25d =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ #define CSR_HVIEN 0x608 diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 7efa76fdbcb1..42d547a03e0f 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -13,6 +13,18 @@ unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 +static int cf_check sstc_set_xen_timer(uint64_t deadline) +{ + csr_write(CSR_STIMECMP, deadline); +#ifdef CONFIG_RISCV_32 + csr_write(CSR_STIMECMPH, deadline >> 32); +#endif + + return 0; +} + +static int (* __ro_after_init set_xen_timer)(uint64_t deadline); + s_time_t get_s_time(void) { uint64_t ticks =3D get_cycles() - boot_clock_cycles; @@ -61,20 +73,7 @@ int reprogram_timer(s_time_t timeout) if ( deadline <=3D now ) return 0; =20 - /* - * TODO: When the SSTC extension is supported, it would be preferable = to - * use the supervisor timer registers directly here for better - * performance, since an SBI call and mode switch would no longer - * be required. - * - * This would also reduce reliance on a specific SBI implementat= ion. - * For example, it is not ideal to panic() if sbi_set_timer() re= turns - * a non-zero value. Currently it can return 0 or -ENOSUPP, and - * without SSTC we still need an implementation because only the - * M-mode timer is available, and it can only be programmed in - * M-mode. - */ - if ( (rc =3D sbi_set_timer(deadline)) ) + if ( (rc =3D set_xen_timer(deadline)) ) panic("%s: timer wasn't set because: %d\n", __func__, rc); =20 /* Enable timer interrupt */ @@ -85,10 +84,17 @@ int reprogram_timer(s_time_t timeout) =20 void __init preinit_xen_time(void) { + unsigned long tmp; + if ( acpi_disabled ) preinit_dt_xen_time(); else panic("%s: ACPI isn't supported\n", __func__); =20 boot_clock_cycles =3D get_cycles(); + + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) + set_xen_timer =3D sstc_set_xen_timer; + else + set_xen_timer =3D sbi_set_timer; } diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index afd8a53a7387..c065052afeb7 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -4,6 +4,7 @@ #include #include =20 +#include #include =20 static void vtimer_expired(void *data) @@ -75,12 +76,16 @@ void vtimer_ctxt_switch_from(struct vcpu *p) { ASSERT(!is_idle_vcpu(p)); =20 - /* Nothing to do at the moment as SSTC isn't supported now. */ + BUG_ON(riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc)); + + /* Nothing to do at the moment as SSTC for guests isn't supported now = */ } =20 void vtimer_ctxt_switch_to(struct vcpu *n) { ASSERT(!is_idle_vcpu(n)); =20 + BUG_ON(riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc)); + migrate_timer(&n->arch.vtimer.timer, n->processor); } --=20 2.53.0 From nobody Wed Apr 1 23:29:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1774983893; cv=none; d=zohomail.com; s=zohoarc; b=nhxNbPaV609WIiu3LPEnNO1xILt7a/wEL9uC+huAhDr980zCOdF0RcTDDkF5NJwF97H08rIylbAgT0NQ+5teoMSZxBpVRlJ+btZiLK2eA9c9DKSMrVx6+wA9E2V+NYnI2xhadZd110RqtN6a7JXBIqmXKMhJyO8p6pJs8GXONMg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1774983893; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5wIJCzxQUgbccKwE9h7kA0JQ/lmT/FyjEkSXHOWHMIM=; b=g3aym+Lhs2mvg3cIRPq4eXZcfdmSRSNGNezKjgQCdSlKM63Z97AS4xG0dw3BcbNIX/KLk+ITFMfBg7XGi4GbGtc9YoL5D66c8FdirdSQsxkGlEmhwJeKUZeCdmnEoD5rjDANLW9AGqvEs7hC+N1qf+vhgpE6TOTbCf8jXJS7OZg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1774983893186645.9499081253201; Tue, 31 Mar 2026 12:04:53 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1269262.1558371 (Exim 4.92) (envelope-from ) id 1w7eOA-0005JW-OM; Tue, 31 Mar 2026 19:04:34 +0000 Received: by outflank-mailman (output) from mailman id 1269262.1558371; Tue, 31 Mar 2026 19:04:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7eOA-0005Ip-Ji; Tue, 31 Mar 2026 19:04:34 +0000 Received: by outflank-mailman (input) for mailman id 1269262; Tue, 31 Mar 2026 19:04:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w7eO9-0004zj-BA for xen-devel@lists.xenproject.org; Tue, 31 Mar 2026 19:04:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7eO8-001kxS-NR for xen-devel@lists.xenproject.org; Tue, 31 Mar 2026 21:04:32 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cc1ac0-bab6-0a2a0a5309dd-0a2a450ba29c-0 for ; Tue, 31 Mar 2026 21:04:32 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.55.2) (envelope-from ) id 69cc1ac0-ef63-0a2a450b0019-d1558035cc59-3 for ; Tue, 31 Mar 2026 21:04:32 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-48540d21f7dso73088655e9.0 for ; Tue, 31 Mar 2026 12:04:32 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Drop 3d argument of INIT_CSR_MASK() and INIT_RO_ONE_MASK() to reduce risk of incomplete editing after copy-and-paste, or other typo-ing. Use _VALID_ infix instead of _AVAIL_ as the mask identifies architecturally defined bits, not bits available for software use. Suggested-by: Jan Beulich Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- xen/arch/riscv/domain.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index c327f44d07ca..c77be3b827eb 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -42,10 +42,10 @@ struct csr_masks { =20 static struct csr_masks __ro_after_init csr_masks; =20 -#define HEDELEG_AVAIL_MASK ULONG_MAX -#define HIDELEG_AVAIL_MASK ULONG_MAX -#define HENVCFG_AVAIL_MASK _UL(0xE0000003000000FF) -#define HSTATEEN0_AVAIL_MASK _UL(0xDE00000000000007) +#define HEDELEG_VALID_MASK ULONG_MAX +#define HIDELEG_VALID_MASK ULONG_MAX +#define HENVCFG_VALID_MASK 0xe0000003000000ffUL +#define HSTATEEN0_VALID_MASK 0xde00000000000007UL =20 void __init init_csr_masks(void) { @@ -57,25 +57,26 @@ void __init init_csr_masks(void) * fields that must be preserved. Any write to the full register must * therefore retain the original values of those fields. */ -#define INIT_CSR_MASK(csr, field, mask) do { \ - register_t old =3D csr_read_set(CSR_ ## csr, mask); \ +#define INIT_CSR_MASK(csr, field) do { \ + register_t old =3D csr_read_set(CSR_ ## csr, csr ## _VALID_MASK); \ csr_masks.field =3D csr_swap(CSR_ ## csr, old); \ } while (0) =20 -#define INIT_RO_ONE_MASK(csr, field, mask) do { \ - register_t old =3D csr_read_clear(CSR_ ## csr, mask); \ - csr_masks.ro_one.field =3D csr_swap(CSR_ ## csr, old) & mask; \ +#define INIT_RO_ONE_MASK(csr, field) do { \ + register_t old =3D csr_read_clear(CSR_ ## csr, csr ## _VALID_MASK)= ; \ + csr_masks.ro_one.field =3D csr_swap(CSR_ ## csr, old) & \ + csr ## _VALID_MASK; \ } while (0) =20 - INIT_CSR_MASK(HEDELEG, hedeleg, HEDELEG_AVAIL_MASK); - INIT_CSR_MASK(HIDELEG, hideleg, HIDELEG_AVAIL_MASK); + INIT_CSR_MASK(HEDELEG, hedeleg); + INIT_CSR_MASK(HIDELEG, hideleg); =20 - INIT_CSR_MASK(HENVCFG, henvcfg, HENVCFG_AVAIL_MASK); + INIT_CSR_MASK(HENVCFG, henvcfg); =20 if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) { - INIT_CSR_MASK(HSTATEEN0, hstateen0, HSTATEEN0_AVAIL_MASK); - INIT_RO_ONE_MASK(HSTATEEN0, hstateen0, HSTATEEN0_AVAIL_MASK); + INIT_CSR_MASK(HSTATEEN0, hstateen0); + INIT_RO_ONE_MASK(HSTATEEN0, hstateen0); } =20 #undef INIT_CSR_MASK --=20 2.53.0