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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-66350b86008sm1394733a12.28.2026.03.13.09.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:46 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f2a23535-1efb-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773420287; x=1774025087; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yfsWIAex3jEpm8GQ6vF4++T74O/B/5LjYy46X+zBd0E=; b=CC7GYogW2mcvpVF9v+qXkIgNbWXtWjm/LXSnMAHo5Qr5DyQQDsyyFufada7WvyZJBz O8g1uNNl6VVvSrhl9obFNJQqw6sQ6pqYMx5QLe3JU5bRxJGSmSjCOc3XMgkAl6kAAd4/ MelV/nsty13qKMAs/VWUxR1hNltNFU2gec6vAW06fRDq+hPujeoUPAVG9MOP+FkFgrxX +XjWP/G1nkcUBSz4CoqfA1t3UxwxL+AtRvUqfA+v+2VdeFttiNeebvXtM9KTsUG9d+59 +uU78SQaGogLw6XO10fHIXHyYD3HEHh18wnDb13J3ZVOPcrRp8a33BK1nYv2ERd8jHpF cSpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773420287; x=1774025087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=yfsWIAex3jEpm8GQ6vF4++T74O/B/5LjYy46X+zBd0E=; b=I5fxY3N8SBLCVxj6XtiUKIsd0vqNepLNZWKfU1jqdofcEllAHWllk5k0DouUHmARrI Z/f9cGJLxQ5kE7AKPZCmtuNm+flMp9DRyrYIoKy1epRzqgG1x6hjlNDtfcyKTf1kmzTF B7d4FMczzu95zRVxPIrXZTnqKDAxNsHgiug58zZyMzC0eRm4wcl1oy/icMD7QFPlRQiJ p+IlrcNoTYOLGJs5ocTKe1e+qQIVK3YWr69UDbLKAlL2eQ7UzQsm9ORRgTdy8/uy1D2T 7VF6x2Emwh3lorxWqRw9qNG4oikI7Q6Q1ejjUCfNOUJgoEKd1pbyAMzD/IOisr3ksqQd qHsA== X-Gm-Message-State: AOJu0YxvYQi/P6hQZs/fdwwha2RpBvYeJ+F/26lyJJvcfVH8VwTDb7nv y7wBl4Kpk2cS9hALfEsEUT4n0caPScVhEXc3KoiSKnuBzxd3qGWR6wEsJ9vfZQ== X-Gm-Gg: ATEYQzxgIKCa/Nv3rEadHEnoukAvuAyrPF36xxEzuUilUY+xn1ykHybXwQ9M3qfwIaf qStV8/CR8PVRcR9EjhdHPwAqJClqOcwSLt9kSyDJckm18HkiUW36MPqnw1ONfexuXjQFdRyDo98 Of4KQJJuZ0bTh5zGochPX3D4VB4AML/sjbmx3fOnA0ftzyg5EGI4MKywZcbp6zYCwLt14jwBNHO 1w901QwH8Ygfn77Uk/c59grqLlHD2kuteVVllbwiNXF+29nDu1NdYc9OWZ8MDHyw94RyulJFbRB jGXZlPI7vH47jeBUA/338lbBjlGVIDwmul4XqQWJCr014uxbX8SQdGJr66rOzzBD0X53GtkwSfh 3JWHfi5gWAAGdeEWFyrX1QTcIwIC3PwABKaas+VADkzm1nX0QI0YNmrmLdv1ldhjE4gWY8jwyPo 57hWBe6dFiyBBpkKihIkLE9H6gNzyQRZ5K/rEqcxieH4eFISQ5pot17d5QsV/uaCKGKg== X-Received: by 2002:a05:6402:5414:b0:659:5c63:e103 with SMTP id 4fb4d7f45d1cf-663ba9b6e96mr2330711a12.11.1773420287152; Fri, 13 Mar 2026 09:44:47 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 1/4] xen/riscv: add exception table support Date: Fri, 13 Mar 2026 17:44:35 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773420311381154100 Content-Type: text/plain; charset="utf-8" Introduce exception table handling for RISC-V so faults from selected instructions can be recovered via fixup handlers instead of being treated as fatal. Add the RISC-V exception table format, sorting at boot to allow binary search used furthuer, and lookup from the trap handler. Update the linker script to emit the .ex_table section using introduced common EX_TABLE macro shared with other architectures. Also, the __start___ext_table is aligned now by POINTER_ALIGN instead of just using hard-coded 8 as there is no too much sense to align __start___ext_table by 8 for 32-bit systems. This implementation is based on Linux 6.16. Signed-off-by: Oleksii Kurochko --- Open question: With some renaming the following could be generic, at least, between x86 and RISC-V: - ASM_EXTABLE() definition - All what is conencted with sort_extable(). - With some change of how x86 searchs an extension this cmp_ex_search() could also go to common file. Does it make sense to introduce xen/extable.h and common/extable.c? --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/Makefile | 1 + xen/arch/riscv/extables.c | 85 +++++++++++++++++++++++++++ xen/arch/riscv/include/asm/extables.h | 72 +++++++++++++++++++++++ xen/arch/riscv/setup.c | 3 + xen/arch/riscv/traps.c | 3 + xen/arch/riscv/xen.lds.S | 3 + xen/arch/x86/xen.lds.S | 6 +- xen/include/xen/xen.lds.h | 10 ++++ 9 files changed, 179 insertions(+), 5 deletions(-) create mode 100644 xen/arch/riscv/extables.c create mode 100644 xen/arch/riscv/include/asm/extables.h diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 89876b32175d..a5e87c1757f7 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -4,6 +4,7 @@ config RISCV select GENERIC_BUG_FRAME select GENERIC_UART_INIT select HAS_DEVICE_TREE_DISCOVERY + select HAS_EX_TABLE select HAS_PMAP select HAS_UBSAN select HAS_VMAP diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index ffbd7062e214..6b3f3ed90bdb 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -3,6 +3,7 @@ obj-y +=3D cpufeature.o obj-y +=3D domain.o obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o +obj-$(CONFIG_HAS_EX_TABLE) +=3D extables.o obj-y +=3D imsic.o obj-y +=3D intc.o obj-y +=3D irq.o diff --git a/xen/arch/riscv/extables.c b/xen/arch/riscv/extables.c new file mode 100644 index 000000000000..5e6e453ead29 --- /dev/null +++ b/xen/arch/riscv/extables.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include +#include + +#define EX_FIELD(ptr, field) ((unsigned long)&(ptr)->field + (ptr)->field) + +static inline unsigned long ex_insn(const struct exception_table_entry *ex) +{ + return EX_FIELD(ex, insn); +} + +static inline unsigned long ex_fixup(const struct exception_table_entry *e= x) +{ + return EX_FIELD(ex, fixup); +} + +static void __init cf_check swap_ex(void *a, void *b) +{ + struct exception_table_entry *x =3D a, *y =3D b, tmp; + int delta =3D b - a; + + tmp =3D *x; + x->insn =3D y->insn + delta; + y->insn =3D tmp.insn - delta; + + x->fixup =3D y->fixup + delta; + y->fixup =3D tmp.fixup - delta; +} + +static int __init cf_check cmp_ex_sort(const void *a, const void *b) +{ + const unsigned long l =3D ex_insn(a); + const unsigned long r =3D ex_insn(b); + + /* avoid overflow */ + return (l > r) - (l < r); +} + +void __init sort_extable(void) +{ + sort(__start___ex_table, __stop___ex_table - __start___ex_table, + sizeof(struct exception_table_entry), cmp_ex_sort, swap_ex); +} + +static int cf_check cmp_ex_search(const void *key, const void *elt) +{ + const unsigned long k =3D *(const unsigned long *)key; + const unsigned long insn =3D ex_insn(elt); + + /* avoid overflow */ + return (k > insn) - (k < insn); +} + +static bool ex_handler_fixup(const struct exception_table_entry *ex, + struct cpu_user_regs *regs) +{ + regs->sepc =3D ex_fixup(ex); + + return true; +} + +bool fixup_exception(struct cpu_user_regs *regs) +{ + unsigned long pc =3D regs->sepc; + const struct virtual_region *region =3D find_text_region(pc); + const struct exception_table_entry *ex; + + if ( !region || !region->ex ) + return false; + + ex =3D bsearch(&pc, region->ex, region->ex_end - region->ex, + sizeof(struct exception_table_entry), cmp_ex_search); + + if ( !ex ) + return false; + + return ex_handler_fixup(ex, regs); +} diff --git a/xen/arch/riscv/include/asm/extables.h b/xen/arch/riscv/include= /asm/extables.h new file mode 100644 index 000000000000..139764f3808d --- /dev/null +++ b/xen/arch/riscv/include/asm/extables.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ASM__RISCV__ASM_EXTABLES_H +#define ASM__RISCV__ASM_EXTABLES_H + +#ifdef __ASSEMBLER__ + +#define ASM_EXTABLE(insn, fixup) \ + .pushsection .ex_table, "a"; \ + .balign 4; \ + .long ((insn) - .); \ + .long ((fixup) - .); \ + .popsection; +.endm + +#else /* __ASSEMBLER__ */ + +#include +#include + +struct cpu_user_regs; + +#define ASM_EXTABLE(insn, fixup) \ + ".pushsection .ex_table, \"a\"\n" \ + ".balign 4\n" \ + ".long ((" #insn ") - .)\n" \ + ".long ((" #fixup ") - .)\n" \ + ".popsection\n" + +/* + * The exception table consists of pairs of relative offsets: the first + * is the relative offset to an instruction that is allowed to fault, + * and the second is the relative offset at which the program should + * continue. No registers are modified, so it is entirely up to the + * continuation code to figure out what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ +struct exception_table_entry { + int32_t insn, fixup; +}; + +extern struct exception_table_entry __start___ex_table[]; +extern struct exception_table_entry __stop___ex_table[]; + +#ifdef CONFIG_HAS_EX_TABLE + +void sort_extable(void); +bool fixup_exception(struct cpu_user_regs *regs); + +#else /* CONFIG_HAS_EX_TABLE */ + +static inline void sort_extable(void) +{ + printk("%s: We don't support .ex_table\n", __func__); +} + +static inline bool fixup_exception(struct cpu_user_regs *regs) +{ + dprintk("%s: We don't support .ex_table\n", __func__); + + return false; +} + +#endif /* CONFIG_HAS_EX_TABLE */ + +#endif /* __ASSEMBLY__ */ + +#endif /* ASM__RISCV__ASM_EXTABLES_H */ diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index cae49bb29626..4be6aa5a434e 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -19,6 +19,7 @@ =20 #include =20 +#include #include #include #include @@ -81,6 +82,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 smp_prepare_boot_cpu(); =20 + sort_extable(); + set_cpuid_to_hartid(0, bootcpu_id); =20 trap_init(); diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 326f2be62823..242af0a7a5f3 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -12,6 +12,7 @@ #include #include =20 +#include #include #include #include @@ -217,6 +218,8 @@ void do_trap(struct cpu_user_regs *cpu_regs) =20 break; } + else if ( fixup_exception(cpu_regs) ) + break; fallthrough; default: if ( cause & CAUSE_IRQ_FLAG ) diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index 331a7d63d3c9..65f136dce9f7 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -74,6 +74,9 @@ SECTIONS .data.ro_after_init : { __ro_after_init_start =3D .; *(.data.ro_after_init) + + EX_TABLE + . =3D ALIGN(PAGE_SIZE); __ro_after_init_end =3D .; } : text diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S index c326538ebbb2..b9e888e5962f 100644 --- a/xen/arch/x86/xen.lds.S +++ b/xen/arch/x86/xen.lds.S @@ -113,11 +113,7 @@ SECTIONS __ro_after_init_start =3D .; *(.data.ro_after_init) =20 - . =3D ALIGN(8); - /* Exception table */ - __start___ex_table =3D .; - *(.ex_table) - __stop___ex_table =3D .; + EX_TABLE =20 . =3D ALIGN(PAGE_SIZE); __ro_after_init_end =3D .; diff --git a/xen/include/xen/xen.lds.h b/xen/include/xen/xen.lds.h index 136849ecd515..85800f942aae 100644 --- a/xen/include/xen/xen.lds.h +++ b/xen/include/xen/xen.lds.h @@ -219,4 +219,14 @@ #define VPCI_ARRAY #endif =20 +#ifdef CONFIG_HAS_EX_TABLE +#define EX_TABLE \ + . =3D ALIGN(POINTER_ALIGN); \ + __start___ex_table =3D .; \ + *(.ex_table) \ + __stop___ex_table =3D .; +#else +#define EX_TABLE +#endif + #endif /* __XEN_LDS_H__ */ --=20 2.53.0 From nobody Mon Mar 23 19:50:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-66350b86008sm1394733a12.28.2026.03.13.09.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:47 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f339755f-1efb-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773420288; x=1774025088; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iuU0sIa/VVlWbkh1TAky3TiyUmxNd2Qh9VKL5gjHn0k=; b=loPICnzuKd343iWNPlJjaz33BKshEr3w55lwx81Vx1L8DJlYD+Xj8yZ1WWxL6m8w1c QmKkrkGz8odl2XG4ygR8VIIbhQ8or1AwgN+NaJDU4OuCxB/u0PLBbUiD5eigJS3zS1Kl gMdKaWIZHTzG/Dpd0nz5DvkgxfFygAZHoEbFSsCDTA6qbVAglL6hUi3liDJbvxVtKtev L5oQ90PillVZuhth7ofS7r7H4seGToHKYlneB56Fs5slSc1jOC6XGpyCnq7pTwJqTeyz sYYOL9LYIHRhpH9wUsr+gG9aAXbEUfA0LQV7+9u0laOV4Cn8Duqh5IhvaoJgqG7FnMxV NRlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773420288; x=1774025088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=iuU0sIa/VVlWbkh1TAky3TiyUmxNd2Qh9VKL5gjHn0k=; b=qXLo0fT1mShYtzutR/wqxW4lwYM3NANAnhEbvZ1DE4Cx3MXyJns21rTjD8LYaYS5RB xij4EXh2vycupr1/t/m2T6YExNuWrmYEXIhfGMWSwisR08GxeXMaEg2ZtfzS9/PZjjBJ yjeJ0H1SDkPNRx+X6RNPC+MesSHVuoWRbLiAoiPslMYXjdzos+Pkt89rPSknf5sR81VM DPBCCDgN4HhcKc1dZ1xYBLkej0mf/uKkhsogvbGV8KCE4U5L9FtRSbsA29r/pKn/TTA8 jurHppnQFcTyAhUcks0tl7oLlnv4CRGgo5+oMMhq1PBRe1TtbchANk4bJuHSTdMRvEhL wp3A== X-Gm-Message-State: AOJu0YzoX3UOlwXEPt8sU9Xqt8Bji6bDNnybHunoUI4JmZr7SfIo5aZq p1OQ7dim268B3SJwERwQhpg7+yKgk9RLx71ieK1dBT+g/aWUwcsUiJDJddAMUg== X-Gm-Gg: ATEYQzynBJVmfcAzl4RaWR68gt42aLpUM464+JwyErMi7VtSE2CcqGapHrvKV0hcOQ+ RkEYHvJWrLeqfkLETQPwHPrui9bEAzYeqbLmJVwsq5/AlfQVXMZ3bzuwZeUthGvJW7KI1TF+p6P 8+ZhDZ7aLZJww1r7KH3F2mZi4yH2lrURDCFR4ICO0ccgIQO086d8SM2QoQ5zW/C5Dmh4WNg46PN fX2WgGAJddiMpaov+tAXHXb4mQvBnUsVDzRJJ6VrmvkwCrRNIG8Gs+O6b/YlfSMKrJtd7Klv5Lb yDU03z3NkC0PBgaR5Jy8407yX9IopAEDxlzEPKXVAYz5KuI2I3y3Sb5LuZ7lnK/FyeurnObgiYg yflk5SUcsVi+9OYe/c0AEQ2NxgHb3DayMhXJTIQashCs9Tn5tUUoYNSkdPNY2ZQmJqtIm2alIlm VM4o/AIgAQHU4rSVexi0yNbOOFRr66YIJhy+j0asQl1VUHv9unUKMrrzaqkzGi1y9WaTS8itOyE iAnLAw7 X-Received: by 2002:a05:6402:1e96:b0:662:fd15:1ae with SMTP id 4fb4d7f45d1cf-663babf76afmr2209158a12.21.1773420288310; Fri, 13 Mar 2026 09:44:48 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 2/4] xen/riscv: add csr_allowed_read() helper Date: Fri, 13 Mar 2026 17:44:36 +0100 Message-ID: <2ea34e564533accb33ccee66b4a8c7a750733ae0.1773419622.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773420311267154100 Content-Type: text/plain; charset="utf-8" Accessing some CSRs may trap when the corresponding extension is not implemented or enabled. Introduce csr_allowed_read() which attempts to read a CSR and relies on the exception table mechanism to safely recover if the access faults. This helper allows Xen to probe CSR availability without taking a fatal trap and will be used for feature detection during early boot as we can't always rely on what is in riscv,isa string in DTS. While touching the header, reorder the include directives to follow the usual Xen style. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/csr.h | 34 +++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/= csr.h index 01876f828981..b9bee3d25d21 100644 --- a/xen/arch/riscv/include/asm/csr.h +++ b/xen/arch/riscv/include/asm/csr.h @@ -6,8 +6,10 @@ #ifndef ASM__RISCV__CSR_H #define ASM__RISCV__CSR_H =20 -#include #include + +#include +#include #include =20 #ifndef __ASSEMBLER__ @@ -78,6 +80,36 @@ : "memory" ); \ }) =20 +static always_inline bool csr_allowed_read(unsigned long csr, + unsigned long *val) +{ + bool error =3D false; + + /* + * Use "+" as a constraint instead of "=3D" to ensure the compiler pas= ses the + * initial value into the asm volatile block. Otherwise, if the instru= ction + * (at label 1) faults, the variable 'error' may contain an undefined = value + * instead of 0. + * If reading of CSR register was failed, we don't care about val, so = "=3D" + * constraint could be used in asm volatile block to not force always = init. + * val argument before being passed to csr_allowed_read() functions. + * + * This avoids the need for an additional instruction inside the asm b= lock + * to explicitly initialize 'error' to 0 before executing the potentia= lly + * faulting instruction. + */ + asm volatile ( + "1: csrr %[val], %[csr]\n" + " li %[err], 1\n" + "2:\n" + ASM_EXTABLE(1b, 2b) + : [val] "=3D&r" (*val), [err] "+&r" (error) + : [csr] "i" (csr) + : "memory" ); + + return error; +} + #endif /* __ASSEMBLER__ */ =20 #endif /* ASM__RISCV__CSR_H */ --=20 2.53.0 From nobody Mon Mar 23 19:50:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773420310; cv=none; d=zohomail.com; s=zohoarc; b=Uas9uWN2rM37r1gmHODevVOJJXKv0oITNZuWJhoWsh6YI9XV7JZ8CGZBT7ef8ZIHVaVP5IGQiZrMRxIgtFP0g3xq0cJkuJ5rPwxwlfDUFk6duKpG2E0MFvhlNelb29QgfkfiifmJwD1745VC6M5KVb8JdavFNLTvw8rzMbT+ZJM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773420310; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=egLBPEab6gTvn7B0yNjcrbib+hRrlZdbL6l46eIKhHg=; b=OP/5qrLitKjXS+DY4YeKOydoSxzda+jtCnOPmRVew091sCMAV6VM2/p6v87ZRpYCACMW6UkdalUAcBkSTxVh3nvH25XkAEZWqpfgaYxpO9EuDj9Q/nNC8eOPMFaFcWQSR/m8noBcghk0lC5TPXqagdJ0LNXRtd/iEprT6XVeWr4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773420310338594.3887681633149; Fri, 13 Mar 2026 09:45:10 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1254119.1550111 (Exim 4.92) (envelope-from ) id 1w15d7-0004XD-1Y; Fri, 13 Mar 2026 16:44:53 +0000 Received: by outflank-mailman (output) from mailman id 1254119.1550111; Fri, 13 Mar 2026 16:44:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w15d6-0004Wr-RJ; Fri, 13 Mar 2026 16:44:52 +0000 Received: by outflank-mailman (input) for mailman id 1254119; Fri, 13 Mar 2026 16:44:51 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w15d5-00048B-Pw for xen-devel@lists.xenproject.org; Fri, 13 Mar 2026 16:44:51 +0000 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [2a00:1450:4864:20::52c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id f435c1fd-1efb-11f1-b164-2bf370ae4941; Fri, 13 Mar 2026 17:44:50 +0100 (CET) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-66174cf4549so4941958a12.0 for ; Fri, 13 Mar 2026 09:44:50 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-66350b86008sm1394733a12.28.2026.03.13.09.44.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:49 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f435c1fd-1efb-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773420290; x=1774025090; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=egLBPEab6gTvn7B0yNjcrbib+hRrlZdbL6l46eIKhHg=; b=PCUXyVC2uvQ+ozJDii+Px996LuQlkOdk6UdUymyowukD2LOJ9Y9Xh6VCnXDU1SsZWv cbED5sVTUp4c6OWXy6D3a5vGhkXWGB6HaLuZhG+kdVl8TqehOzuZT3GuBmBIA6pjMCNd PZfZ2vvo1PLdFUQQmH4AfVAiQ6olhGuK8yMxAdp93aKomX6QhBuOr7QWqcXWeuth5pcH dxQiRUvtAOZM7T1PcSaGqKPrG1rWMIquN2SFsjyMAqsxHfFqiH2PBPuCX85ql6v/UCkF 5hSHgaVwK1RBlb/QSsr9dsirgXKgTNN72LPncm5c3CGdkzOt/qdw59lRPid0VdIoMlBf QMPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773420290; x=1774025090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=egLBPEab6gTvn7B0yNjcrbib+hRrlZdbL6l46eIKhHg=; b=iliqa567zrjuUQUKokjcwy1wUU/wNh6/IkJfSpjYNrp3kYeBDfN9eTTwqgPXSKoMB2 n626ljDoQiiopCMZnzfV44i1z31I4y+0Rj1nUtmPxaaEX/X6wdUigCdZosehiZz7O/vo FoTIqZuyJXiKW2Ly1Q37ebL/71uOLR27PV8gI2j5tRo5nbjxG7Yh/Aq1Nr2AqTCSTni4 THHeICHnriMbRQF1awHK8yyv6pNh76Lc1fqdkopmjXx0XhjXSym+x9hNEXlxeISm+DNb Wb8rSnPy57YNrQYaTHX01Br73/4GxfJWjNJjI0bTbKGUUP4CW40u5XzVWD3JqGZwzRCT E08A== X-Gm-Message-State: AOJu0YwXo4CIYIB/SxQSVFcLlFsWYSu/JxarOq63jmFjevymYmi03gy6 mdXOGdXFbkIaTzwqaQIEkfpoWoIE3XwDlfVk5rIqjqaltq9do+gzW5bmVR9yNg== X-Gm-Gg: ATEYQzy5tUsM8Uq3Iz8Vu+Q7MjIja0I184M2Q7bsqvebAtoGlaCp9i3ol/7qyrjI93i sVPRAQaBDhMH25F24/e/6oIqkpxtxPUBedrfzkZbF1JlqVlSbTCqEO7f+/7BXh57WpI7BSX2omg P7SM726+hAY9eNymaIEtClHCzWWsjr9ql/3MVfXz3HAvG9tMgm2R8eLOBFviMRfhXosTrzRQbMC kRLuhgCyKHkXLJL+tyo/7Xdq/Qc1Qv4Zkdd2nv+JrIwPhVbVnyMtd3FhNKsqM/EylS+y4Ia7EFy izTIXSIxwwTtB06N9RQY2nIFuLqivQ9T8Fa2Z0YmlvmJ0sOYpnpmpgiT5ru5Tl+s+MZmBCFuuCC LQetyXaNwuCzBsPLPrAcGQu2GQ6sWK7XizflZUe8v3w3Em6GZBTSH8oEW5A6r9pEtnpVv0Nr+qo utgJFzH83KPFCmhA0B4/pq81VQHxc0uzbVTB+jH4wsfVWRfl0cTG7DBh/zZ328P01+QA== X-Received: by 2002:a05:6402:42cc:b0:660:f351:758d with SMTP id 4fb4d7f45d1cf-663b6f7ffafmr2600176a12.7.1773420289901; Fri, 13 Mar 2026 09:44:49 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 3/4] xen/riscv: allow Xen to use SSTC while hiding it from guests Date: Fri, 13 Mar 2026 17:44:37 +0100 Message-ID: <0f0849b53625f9f9f939000f29579e264e522fd2.1773419622.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773420311431158500 Content-Type: text/plain; charset="utf-8" OpenSBI currently does not advertise the SSTC extension via the device tree. Additionally, SSTC can no longer be reliably disabled by removing the "sstc" string from riscv,isa, as OpenSBI probes support by attempting to access CSR_STIMECMP. Introduce a runtime probe in Xen to determine whether SSTC is available. The probe attempts to read CSR_STIMECMP using csr_allowed_read(). If the access succeeds, SSTC is considered available; if a trap occurs, it is treated as unsupported. When SSTC is detected, Xen may use it internally to program timers. However, the extension is not exposed to guests because the required context switch handling for the SSTC CSRs is not yet implemented. To prevent guests from using SSTC, RISCV_ISA_EXT_sstc is cleared from the riscv_isa bitmap. As a result, the corresponding HENVCFG bit is not set and guests fall back to the SBI timer interface. Timer requests are then handled by Xen via the usual SBI interception path. Introduce set_xen_timer() to abstract how the timer is programmed, either via the SSTC extension or an SBI call. This also reduces the number of if statements in reprogram_timer(). The set_xen_timer function pointer is selected based on csr_allowed_read() rather than riscv_isa_extension(). The latter reflects features supported by both Xen and the guest, while SSTC is currently only supported for Xen. Therefore, relying solely on riscv_isa_extension() would not reliably determine whether SSTC can be used. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/cpufeature.c | 33 +++++++++++++++++++ xen/arch/riscv/domain.c | 3 ++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/riscv_encoding.h | 2 ++ xen/arch/riscv/time.c | 36 +++++++++++++-------- xen/arch/riscv/vtimer.c | 7 +++- 6 files changed, 67 insertions(+), 15 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 03e27b037be0..a7aa2358b73b 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -17,6 +17,7 @@ #include =20 #include +#include =20 #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -139,6 +140,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_e= xt[] =3D { RISCV_ISA_EXT_DATA(smaia), RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), + RISCV_ISA_EXT_DATA(sstc), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), }; @@ -483,6 +485,7 @@ void __init riscv_fill_hwcap(void) unsigned int i; const size_t req_extns_amount =3D ARRAY_SIZE(required_extensions); bool all_extns_available =3D true; + unsigned long tmp; =20 riscv_fill_hwcap_from_isa_string(); =20 @@ -495,6 +498,36 @@ void __init riscv_fill_hwcap(void) panic("HW capabilities parsing failed: %s\n", failure_msg); } =20 + if ( csr_allowed_read(CSR_STIMECMP, &tmp) ) + { + printk("SSTC is detected but is supported only for Xen usage not f= or " + "a guest.\n"); + + /* + * As SSTC for guest isn't supported it is needed temprorary to: + * + * 1. Clear bit RISCV_ISA_EXT_sstc in riscv_isa as theoretuically = it + * could be that OpenSBI (it doesn't pass it now) or whatever r= an + * before Xen will add SSTC to riscv,isa string. This bit clear + * willn't allow guest to use SSTC extension as vtimer context + * switch and restore isn't ready for that. + */ + __clear_bit(RISCV_ISA_EXT_sstc, riscv_isa); + + /* + * 2. A VS-timer interrupt becomes pending whenever the value of + * (time + htimedelta) is greater than or equal to vstimecmp CS= R. + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to + * -1. + * + * It should be dropped when SSTC for guests will be supported. + */ + csr_write(CSR_VSTIMECMP, ULONG_MAX); +#ifdef CONFIG_RISCV_32 + csr_write(CSR_VSTIMECMPH, ULONG_MAX); +#endif + } + for ( i =3D 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext =3D required_extensions[i]; diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index c327f44d07ca..5f15dda88c8e 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -99,6 +99,9 @@ static void vcpu_csr_init(struct vcpu *v) if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) ) v->arch.henvcfg =3D ENVCFG_PBMTE & csr_masks.henvcfg; =20 + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) + v->arch.henvcfg |=3D ENVCFG_STCE & csr_masks.henvcfg; + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) { /* Allow guest to access CSR_SENVCFG */ diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index ef02a3e26d2c..0c48d57a03bb 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -38,6 +38,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_smaia, RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, + RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index dd15731a86fa..7fc379cab588 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -396,6 +396,8 @@ #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 +#define CSR_VSTIMECMP 0x24D +#define CSR_VSTIMECMPH 0x25D =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ #define CSR_HVIEN 0x608 diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 7efa76fdbcb1..98eca2887d5c 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -13,6 +13,20 @@ unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 +static int cf_check sstc_set_xen_timer(uint64_t deadline) +{ +#ifdef CONFIG_RISCV_32 + csr_write(CSR_STIMECMP, deadline & 0xFFFFFFFF); + csr_write(CSR_STIMECMPH, deadline >> 32); +#else + csr_write(CSR_STIMECMP, deadline); +#endif + + return 0; +} + +int (* __ro_after_init set_xen_timer)(uint64_t deadline); + s_time_t get_s_time(void) { uint64_t ticks =3D get_cycles() - boot_clock_cycles; @@ -61,20 +75,7 @@ int reprogram_timer(s_time_t timeout) if ( deadline <=3D now ) return 0; =20 - /* - * TODO: When the SSTC extension is supported, it would be preferable = to - * use the supervisor timer registers directly here for better - * performance, since an SBI call and mode switch would no longer - * be required. - * - * This would also reduce reliance on a specific SBI implementat= ion. - * For example, it is not ideal to panic() if sbi_set_timer() re= turns - * a non-zero value. Currently it can return 0 or -ENOSUPP, and - * without SSTC we still need an implementation because only the - * M-mode timer is available, and it can only be programmed in - * M-mode. - */ - if ( (rc =3D sbi_set_timer(deadline)) ) + if ( (rc =3D set_xen_timer(deadline)) ) panic("%s: timer wasn't set because: %d\n", __func__, rc); =20 /* Enable timer interrupt */ @@ -85,10 +86,17 @@ int reprogram_timer(s_time_t timeout) =20 void __init preinit_xen_time(void) { + unsigned long tmp; + if ( acpi_disabled ) preinit_dt_xen_time(); else panic("%s: ACPI isn't supported\n", __func__); =20 boot_clock_cycles =3D get_cycles(); + + if ( csr_allowed_read(CSR_STIMECMP, &tmp) ) + set_xen_timer =3D sstc_set_xen_timer; + else + set_xen_timer =3D sbi_set_timer; } diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index afd8a53a7387..c065052afeb7 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -4,6 +4,7 @@ #include #include =20 +#include #include =20 static void vtimer_expired(void *data) @@ -75,12 +76,16 @@ void vtimer_ctxt_switch_from(struct vcpu *p) { ASSERT(!is_idle_vcpu(p)); =20 - /* Nothing to do at the moment as SSTC isn't supported now. */ + BUG_ON(riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc)); + + /* Nothing to do at the moment as SSTC for guests isn't supported now = */ } =20 void vtimer_ctxt_switch_to(struct vcpu *n) { ASSERT(!is_idle_vcpu(n)); =20 + BUG_ON(riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc)); + migrate_timer(&n->arch.vtimer.timer, n->processor); } --=20 2.53.0 From nobody Mon Mar 23 19:50:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773420318; cv=none; d=zohomail.com; s=zohoarc; b=PcZmOxfpJX+GwKuYq+wJYrjwtOxSHzjHl0TUP3r72i8ztM9KFZh2lkzit+dA/awC7h7Zuw+jsIU3MAhezGfnIs8NzasRL96ivmA+W5I5o8qTdju9MPN7C+2cfe8NtmAoj2hB2l/0JtSjI5QA90RjJmmn79HUK2q+c3LX29PE+O0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773420318; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WC9Q7UDifDEqfqwQFhunvL4KaBDnJAUUS0hjUL4t6mI=; b=SAuz3ew8cYM3lSko7eF8Lq4OWxNZZFIWw4RMmpZMxCGIS9MlW1vaD3YhbIPZfTZfsbUpxd5U5s1bhZVUxlIqqI+hkhBpU7RDgJOojKdZcMlmuQPlaCZHG/ueoKLXhjlLofQkZ9Tts6nEGwVWVJwyfyVqWuHS5ywI/MM28nu/JA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773420318099455.70081478342536; Fri, 13 Mar 2026 09:45:18 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1254120.1550126 (Exim 4.92) (envelope-from ) id 1w15dC-000579-86; Fri, 13 Mar 2026 16:44:58 +0000 Received: by outflank-mailman (output) from mailman id 1254120.1550126; Fri, 13 Mar 2026 16:44:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w15dC-000570-3y; Fri, 13 Mar 2026 16:44:58 +0000 Received: by outflank-mailman (input) for mailman id 1254120; Fri, 13 Mar 2026 16:44:57 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w15dB-0004GG-4W for xen-devel@lists.xenproject.org; Fri, 13 Mar 2026 16:44:57 +0000 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [2a00:1450:4864:20::536]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id f5170cf2-1efb-11f1-9ccf-f158ae23cfc8; Fri, 13 Mar 2026 17:44:52 +0100 (CET) Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-66391baf250so2038238a12.1 for ; Fri, 13 Mar 2026 09:44:52 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-66350b86008sm1394733a12.28.2026.03.13.09.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:50 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f5170cf2-1efb-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773420292; x=1774025092; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WC9Q7UDifDEqfqwQFhunvL4KaBDnJAUUS0hjUL4t6mI=; b=ZP0kBdpNmwu+l6bfZZVSXm8+/xwfs5sdGlQZuz7GNKQGcT1FGN98IVpCFDn4h6IXLe NL2tcUsknjW8bv32fm/RvWD1N0ZEVFaTmcz+a4Wca/xHFVeAZpNldW/VNoQsVdLAahYH YIHWNuA3ddBNb04Jmn/IpeIjDp0TIYVZD3HP69ZypXotLmOtIyCUAhyauLVJIbTGtats S/NqkyhW/bijXWpCOiUzJpCUNPR8OMngEj2fasTCzAL5VGrecMhzn9SwBhgJfrTocIFZ 3EB0XWyR33QgLPuldGIb2gEsgLRQ+ZLwYsIHal1hYBGytv5gfTNXD1AO/l+Jc8OrMXyG h3Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773420292; x=1774025092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=WC9Q7UDifDEqfqwQFhunvL4KaBDnJAUUS0hjUL4t6mI=; b=iYYO95Imr3qq6V+Wp4AKKYUhYQ/Am/JPH6FoQ9Ig8CkjIM89Zc9t9PgwXaQf48BEUW 2O8V9s6LFpG1+d5i7D9KPOi9jfS5KD1g74JUbcWP7l1heoRg/6OGVDl+buTtsiyPcuaq ev8QI8QNE2H1YCd5Kpz4wbxwAYW5AxBf40uS9jjPk23GBo7X+Bp3OXaVY15ZDV66muim UD+QYaa28sadRl7iUpj4xNBl4efVAcSs35Elhgpl666Qku+htwLKczqV/2Dbb7PS1az6 Bj8InvYumc0kqneNzR6IjQYjejkMOa0Ejw/AoEisRq/6VtVcKKFx3KfgZMPz6IdIKFhJ zKMg== X-Gm-Message-State: AOJu0Yw1XS7ovVLrROzkamAH/WwtbHW4XZUDBudLXdoJ2vZ4/zUt2CDs gQ7VCACm/75tuq5x1fXg2HppIpCmkYoTGk+VPg5PdbVV/9eF74SNHNXbBYQEeg== X-Gm-Gg: ATEYQzzTtXyXTWq/x7BS497pHq/j/oUxx8BPE75RstKFy+Qc5HV/Y8tSh4ILFOmd/9V Q157VX7q/Wn35CpD+Pub0g78vBIhVvAcfIWx/7A62mF8z2fuODA/5bTywPtOl+OfbMps7yH+mEX 5fKkuzJJg9Qty881my4fZ86cZkPuvsi43VE0bpg/mGCc7ecPwTF2cyYQABBn9YfAVFupn21FT36 s/JCgAkyO1aEwvOuPzeW7vP989W8HhqCa2cIKcid0dU+72YVieqWOjPoaIE2Wv7PTxYXS2GHyzB LOUX9wW1O/1YsJhW93H5HHDYa7L+0Bdt+t4j9DYIhaNpwA27ms+NYUVv91ArlZ0dVNLC5qBvsOL TchZ+4KNsrYapoVmAzRbdTwHL87H9JgexGx89voGpdc2WjwS4/RQJwlIW9W3r4yk7hbtRR4z0Fo GnQlixKqAJbQDkF6WNwwHDrdoBvepAfkwEM6QxVvvmFtkYJPYn00tAzhJ+729pMAL5jg== X-Received: by 2002:a05:6402:254f:b0:661:d0a4:ad45 with SMTP id 4fb4d7f45d1cf-663babb8965mr2319469a12.10.1773420291271; Fri, 13 Mar 2026 09:44:51 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 4/4] xen/riscv: init_csr_masks()-related improvements Date: Fri, 13 Mar 2026 17:44:38 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773420319371158500 Content-Type: text/plain; charset="utf-8" There is no reason to use _UL() in define-s sitting in C file hence use UL prefix instead. Drop 3d argument of INIT_CSR_MASK() and INIT_RO_ONE_MASK() to reduce risk of incomplete editing after copy-and-paste, or other typo-ing. Suggested-by: Jan Beulich Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/domain.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 5f15dda88c8e..70d0e55ed1bc 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -42,10 +42,10 @@ struct csr_masks { =20 static struct csr_masks __ro_after_init csr_masks; =20 -#define HEDELEG_AVAIL_MASK ULONG_MAX -#define HIDELEG_AVAIL_MASK ULONG_MAX -#define HENVCFG_AVAIL_MASK _UL(0xE0000003000000FF) -#define HSTATEEN0_AVAIL_MASK _UL(0xDE00000000000007) +#define HEDELEG_VALID_MASK ULONG_MAX +#define HIDELEG_VALID_MASK ULONG_MAX +#define HENVCFG_VALID_MASK (0xE0000003000000FFUL) +#define HSTATEEN0_VALID_MASK (0xDE00000000000007UL) =20 void __init init_csr_masks(void) { @@ -57,25 +57,26 @@ void __init init_csr_masks(void) * fields that must be preserved. Any write to the full register must * therefore retain the original values of those fields. */ -#define INIT_CSR_MASK(csr, field, mask) do { \ - register_t old =3D csr_read_set(CSR_ ## csr, mask); \ +#define INIT_CSR_MASK(csr, field) do { \ + register_t old =3D csr_read_set(CSR_ ## csr, csr ## _VALID_MASK); \ csr_masks.field =3D csr_swap(CSR_ ## csr, old); \ } while (0) =20 -#define INIT_RO_ONE_MASK(csr, field, mask) do { \ - register_t old =3D csr_read_clear(CSR_ ## csr, mask); \ - csr_masks.ro_one.field =3D csr_swap(CSR_ ## csr, old) & mask; \ +#define INIT_RO_ONE_MASK(csr, field) do { \ + register_t old =3D csr_read_clear(CSR_ ## csr, csr ## _VALID_MASK)= ; \ + csr_masks.ro_one.field =3D csr_swap(CSR_ ## csr, old) & \ + csr ## _VALID_MASK; \ } while (0) =20 - INIT_CSR_MASK(HEDELEG, hedeleg, HEDELEG_AVAIL_MASK); - INIT_CSR_MASK(HIDELEG, hideleg, HIDELEG_AVAIL_MASK); + INIT_CSR_MASK(HEDELEG, hedeleg); + INIT_CSR_MASK(HIDELEG, hideleg); =20 - INIT_CSR_MASK(HENVCFG, henvcfg, HENVCFG_AVAIL_MASK); + INIT_CSR_MASK(HENVCFG, henvcfg); =20 if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) { - INIT_CSR_MASK(HSTATEEN0, hstateen0, HSTATEEN0_AVAIL_MASK); - INIT_RO_ONE_MASK(HSTATEEN0, hstateen0, HSTATEEN0_AVAIL_MASK); + INIT_CSR_MASK(HSTATEEN0, hstateen0); + INIT_RO_ONE_MASK(HSTATEEN0, hstateen0); } =20 #undef INIT_CSR_MASK --=20 2.53.0