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charset="utf-8" Most (if not all) Intel CPUs starting from Sandy Bridge have up to 8 event selectors per core, which could be halved per hyperthread. However, current PV emulation logic doesn't support up to 8 event selector, leading to errors when trying to access them, hence, preventing Linux from driving the vPMU correctly. Make sure up to MSR_P6_EVNTSEL(7) is usable, which is the same upper bound = as used in VMX code. The check if the event selector actually exist for the hardware is done in core2_vpmu_do_{rdmsr,wrmsr}, hence we're not allowing to access non-existent MSRs. Fixes: 27c554198666 ("x86/VPMU: add support for PMU register handling on PV= guests") Signed-off-by: Teddy Astie Reviewed-by: Jan Beulich --- xen/arch/x86/pv/emul-priv-op.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 64d47ab677..b2556f9213 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -990,7 +990,7 @@ static int cf_check read_msr( return X86EMUL_OKAY; =20 case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7): - case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3): + case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(7): case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL ) @@ -1167,7 +1167,7 @@ static int cf_check write_msr( break; =20 case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7): - case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3): + case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(7): case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL ) --=20 2.53.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Wed Apr 8 02:48:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass header.i=teddy.astie@vates.tech; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1773161131; cv=none; d=zohomail.com; s=zohoarc; b=TBz5/MXH5A+u6dKVMbCTBVM4p+4Pn3hsPJqE6ia1vNpDMpY9TkyKKBUrUeYevseRZ53cZzJjgipuQiIykAMnZHLPnur9NQYLwBJjIPO+m9APqxYK5DlPvopSYejA1OnXE6Nf0PI7hKsuy0scU9/ivoFRTpy+gshfVv8cCjtymqU= ARC-Message-Signature: i=1; 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charset="utf-8" I don't see any reason for them for not be available, especially since core2_vpmu_do_wrmsr has PV specific logic for MSR_IA32_DS_AREA. Fixes: 27c554198666 ("x86/VPMU: add support for PMU register handling on PV= guests") Signed-off-by: Teddy Astie --- xen/arch/x86/pv/emul-priv-op.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index b2556f9213..0d93218030 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -993,6 +993,8 @@ static int cf_check read_msr( case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(7): case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: + case MSR_IA32_PEBS_ENABLE: + case MSR_IA32_DS_AREA: if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL ) { vpmu_msr =3D true; @@ -1170,6 +1172,8 @@ static int cf_check write_msr( case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(7): case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... 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charset="utf-8" Signed-off-by: Teddy Astie --- xen/arch/x86/cpu/vpmu_intel.c | 4 ++-- xen/arch/x86/domain.c | 2 +- xen/include/xen/lib/x86/cpu-policy.h | 10 +++++++++- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 1e3b06ef8e..f43faf9567 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -818,8 +818,8 @@ static int cf_check core2_vpmu_initialise(struct vcpu *= v) u64 msr_content; static bool ds_warned; =20 - if ( v->domain->arch.cpuid->basic.pmu_version <=3D 1 || - v->domain->arch.cpuid->basic.pmu_version >=3D 6 ) + if ( v->domain->arch.cpuid->basic.pmu.version <=3D 1 || + v->domain->arch.cpuid->basic.pmu.version >=3D 6 ) return -EINVAL; =20 if ( (arch_pmc_cnt + fixed_pmc_cnt) =3D=3D 0 ) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index e658c2d647..5762b38fce 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -458,7 +458,7 @@ void domain_cpu_policy_changed(struct domain *d) =20 /* If PMU version is zero then the guest doesn't have VPMU */ if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && - p->basic.pmu_version =3D=3D 0 ) + p->basic.pmu.version =3D=3D 0 ) vpmu_destroy(v); } } diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86= /cpu-policy.h index d29e380359..9161e2ad8d 100644 --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -162,7 +162,15 @@ struct cpu_policy uint64_t :64, :64; /* Leaf 0x9 - DCA */ =20 /* Leaf 0xa - Intel PMU. */ - uint8_t pmu_version, _pmu[15]; + struct { + uint8_t /* a */ version, num_gp_ctrs, gp_ctr_width, + event_enum_length; + uint32_t /* b */:32; + uint32_t /* c */ fixed_ctr_mask; + uint32_t /* d */ num_fixed_ctr:5, fixed_ctr_width:8, :1, + anythread_depreciation:1, slots_per_cyc:4, + :13; + } pmu; =20 uint64_t :64, :64; /* Leaf 0xb - Topology. */ uint64_t :64, :64; /* Leaf 0xc - rsvd */ --=20 2.53.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Wed Apr 8 02:48:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Currently, Xen exposes the host CPUID as-is, which is not correct on hardwa= re that implements PMU features that are not supported by Xen (e.g AnyThread b= it of PMU version 3, IA32_PERF_GLOBAL_INUSE of PMU version 4, and many other things). As we're actually virtualizing PMU version 2 (as version 3 is the same as version 2 with the addition to AnyThread bit, which is we don't support sin= ce [1]), adjust the messages related to PMU emulation to account that. [1] 9f5390441a6e ("x86/vpmu_intel: handle SMT consistently for programmable= and fixed counters") Signed-off-by: Teddy Astie --- It could sound weird that we're now exposing version 2, while we were previ= ously (wrongly) exposing version 3. Version 3 mostly works because the guest is n= ot aware of hyperthreads, hence is not expected to try using AnyThread bit (wh= ich currently faults due to consistency checks). But we were still actually vir= tualizing PMU version 2. xen/arch/x86/cpu-policy.c | 33 ++++++++++++++++++++++++++++++++- xen/arch/x86/cpu/vpmu_intel.c | 4 ++-- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 5273fe0ae4..7f4456d5a2 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -253,6 +253,33 @@ static void recalculate_xstate(struct cpu_policy *p) } } =20 +static void sanitise_vpmu(struct cpu_policy *p) +{ +switch ( p->x86_vendor ) + { + case X86_VENDOR_INTEL: + if ( !p->basic.pmu.version ) + return; + + /* + * Expose up to PMU version 2=20 + * + * PMU version 3 introduced the AnyThread bit we don't want + * to support (see "AnyThread Counting and Software Evolution" + * regarding notes with virtualization). This is the only known + * feature introduced in PMU version 3. + * + * PMU version 5 deprecated AnyThread, and introduced a CPUID + * bit (ANYTHREAD_DEPRECATION) to indicate that this bit isn't sup= ported. + * That CPUID bit should be set for PMU version 5. + */ + if ( p->basic.pmu.version > 2 ) + p->basic.pmu.version =3D 2; + + break; + } +} + /* * Misc adjustments to the policy. Mostly clobbering reserved fields and * duplicating shared fields. Intentionally hidden fields are annotated. @@ -391,6 +418,8 @@ static void __init calculate_host_policy(void) /* When vPMU is disabled, drop it from the host policy. */ if ( vpmu_mode =3D=3D XENPMU_MODE_OFF ) p->basic.raw[0xa] =3D EMPTY_LEAF; + else + sanitise_vpmu(p); =20 /* 0x000000ce MSR_INTEL_PLATFORM_INFO */ /* probe_cpuid_faulting() sanity checks presence of MISC_FEATURES_ENAB= LES */ @@ -841,7 +870,7 @@ static void __init calculate_hvm_max_policy(void) /* Enable features which are always emulated. */ p->extd.raw[0xa].d |=3D (1u << SVM_FEATURE_VMCBCLEAN); } - =20 + guest_common_max_feature_adjustments(fs); guest_common_feature_adjustments(fs); =20 @@ -1054,6 +1083,8 @@ void recalculate_cpuid_policy(struct domain *d) if ( vpmu_mode =3D=3D XENPMU_MODE_OFF || ((vpmu_mode & XENPMU_MODE_ALL) && !is_hardware_domain(d)) ) p->basic.raw[0xa] =3D EMPTY_LEAF; + else + sanitise_vpmu(p); =20 if ( !p->extd.svm ) p->extd.raw[0xa] =3D EMPTY_LEAF; diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index f43faf9567..85539ce6c5 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -901,14 +901,14 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(vo= id) =20 switch ( version ) { + case 3: case 4: case 5: printk(XENLOG_INFO "VPMU: PMU version %u is not fully supported. " - "Emulating version 3\n", version); + "Emulating version 2\n", version); /* FALLTHROUGH */ =20 case 2: - case 3: break; =20 default: --=20 2.53.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Wed Apr 8 02:48:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass header.i=teddy.astie@vates.tech; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1773161123; cv=none; d=zohomail.com; s=zohoarc; b=SaPzXa4ZQPTlEqumqRkmfml7ES9BSE9dtxUpOV2/8weQqmoUkwGSprujyCcuCnxIFxAGiKfhCxrPxpWuE8yFT8FQnady8SbKLl3RlrrKog4lqK3edwSJy152nwGxVL2vzK5/FYGgqJly6xqoWK4kMGqqyA6uTdGY7BUTehusQmc= ARC-Message-Signature: i=1; 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charset="utf-8" Hardware can support more than 8 general or 3 fixed counters, which could l= ead to inconsistent access to MSRs (thus failure to initialize vPMU in guest) a= s we don't support accessing more than these limits. Signed-off-by: Teddy Astie --- I'm not aware of a processor that have more than that, but the specification tells that this is possible. xen/arch/x86/cpu-policy.c | 6 ++++++ xen/arch/x86/cpu/vpmu_intel.c | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 7f4456d5a2..46db7f0726 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -276,6 +276,12 @@ switch ( p->x86_vendor ) if ( p->basic.pmu.version > 2 ) p->basic.pmu.version =3D 2; =20 + /* Truncate control register count to what we support */ + if ( p->basic.pmu.num_gp_ctrs > 8 ) + p->basic.pmu.num_gp_ctrs =3D 8; + + if ( p->basic.pmu.num_fixed_ctr > 3 ) + p->basic.pmu.num_fixed_ctr =3D 3; break; } } diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 85539ce6c5..0871795218 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -924,7 +924,22 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(voi= d) } =20 arch_pmc_cnt =3D core2_get_arch_pmc_count(); + if ( arch_pmc_cnt > 8 ) + { + printk(XENLOG_INFO + "VPMU: Too many general counters (%u), emulating 8 register= s\n", + arch_pmc_cnt); + arch_pmc_cnt =3D 8; + } + fixed_pmc_cnt =3D core2_get_fixed_pmc_count(); + if ( fixed_pmc_cnt > 3 ) + { + printk(XENLOG_INFO + "VPMU: Too many fixed counters (%u), emulating 3 registers\= n", + arch_pmc_cnt); + fixed_pmc_cnt =3D 3; + } =20 if ( cpu_has_pdcm ) { --=20 2.53.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Wed Apr 8 02:48:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass header.i=teddy.astie@vates.tech; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" PMU version 6 (notably implemented in Intel Core Ultra) is backward compati= ble with older versions, as we're exposing version 2 to the guest, it is not expected not try using PMU version 6 features. Signed-off-by: Teddy Astie --- I don't have the hardware to test vPMU on Intel Core Ultra, but I guess it's supposed to work, as it only introduces new features and doesn't disable existing ones. That could want a changelog entry regarding vPMU support on Intel Core Ultr= a=20 and alike ? xen/arch/x86/cpu/vpmu_intel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 0871795218..9c8802b285 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -819,7 +819,7 @@ static int cf_check core2_vpmu_initialise(struct vcpu *= v) static bool ds_warned; =20 if ( v->domain->arch.cpuid->basic.pmu.version <=3D 1 || - v->domain->arch.cpuid->basic.pmu.version >=3D 6 ) + v->domain->arch.cpuid->basic.pmu.version >=3D 7 ) return -EINVAL; =20 if ( (arch_pmc_cnt + fixed_pmc_cnt) =3D=3D 0 ) @@ -904,6 +904,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) case 3: case 4: case 5: + case 6: printk(XENLOG_INFO "VPMU: PMU version %u is not fully supported. " "Emulating version 2\n", version); /* FALLTHROUGH */ --=20 2.53.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech