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This function is invoked in construct_domU() within the common Dom0less code, and providing an implementation of domain_p2m_set_allocation() when CONFIG_ARCH_PAGING_MEMPOOL=3Dy is appropriate for RISC-V. Additionally, implement arch_{set,get}_paging_mempool_size(). They are not used directly for now, but are required to support the XEN_DOMCTL_{get,set}_paging_mempool_size() hypercalls. Remove 'struct paging_domain' from RISC-V's 'struct arch_domain' when the field is not required. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/Makefile | 2 +- xen/arch/riscv/include/asm/domain.h | 2 ++ xen/arch/riscv/p2m.c | 31 +++++++++++++++++++++++++++++ 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 12b337365f1f..091510380949 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -1,5 +1,6 @@ config RISCV def_bool y + select ARCH_PAGING_MEMPOOL select DOMAIN_BUILD_HELPERS select FUNCTION_ALIGNMENT_16B select GENERIC_BUG_FRAME diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 48957104e0b5..b1514f1514a2 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -10,7 +10,7 @@ obj-y +=3D irq.o obj-y +=3D kernel.o obj-y +=3D mm.o obj-y +=3D p2m.o -obj-y +=3D paging.o +obj-$(CONFIG_ARCH_PAGING_MEMPOOL) +=3D paging.o obj-y +=3D pt.o obj-$(CONFIG_RISCV_64) +=3D riscv64/ obj-y +=3D sbi.o diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 6c48bf13111d..0caacf92b5a2 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -92,7 +92,9 @@ struct arch_domain { /* Virtual MMU */ struct p2m_domain p2m; =20 +#ifdef CONFIG_ARCH_PAGING_MEMPOOL struct paging_domain paging; +#endif }; =20 #include diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index fba93bce24d9..886e06196ba2 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -1568,3 +1568,34 @@ struct page_info *get_page_from_gfn(struct domain *d= , unsigned long gfn, =20 return page; } + +#ifdef CONFIG_ARCH_PAGING_MEMPOOL + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + unsigned long pages =3D PFN_DOWN(size); + bool preempted =3D false; + int rc; + + if ( (size & ~PAGE_MASK) || /* Non page-sized request? */ + pages !=3D PFN_DOWN(size) ) /* 32-bit overflow? */ + return -EINVAL; + + spin_lock(&d->arch.paging.lock); + rc =3D p2m_set_allocation(d, pages, &preempted); + spin_unlock(&d->arch.paging.lock); + + ASSERT(preempted =3D=3D (rc =3D=3D -ERESTART)); + + return rc; +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + *size =3D (uint64_t)ACCESS_ONCE(d->arch.paging.total_pages) << PAGE_SH= IFT; + + return 0; +} + +#endif /* CONFIG_ARCH_PAGING_MEMPOOL */ --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773162577; cv=none; d=zohomail.com; s=zohoarc; b=BM6Mxb55TRA9XA+9NFDRBK8vZOYCxKAmu6fXikmqRXtH9RUHvbOmo7Ew1ifHEH0TnqDf1oK2WJuAPvwjCStNzAqPBU2P9+un/jqcb882J5fAXDB4SsGjwekXdmbt8GfxL5jN7QP/N5iXrli4osOVm0XTztfWEMsZAivKcCGFi7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773162577; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dQTAxI2vfkx2VNhH7t+uCNbpYCzRGkHrgeV3afpytNg=; b=Nzvyp2iPsg98d0LRBsErkv2ruTWiE7364b7QR1FSsgm66dhYpZ4Xb6rTPNbW1D1q1ItIQ4L0iFC/XB74x82Imm2oF5T8UENvZIR84JRp33JrzBsnidPRG8WJyUZtDwd15+Kc95IHw9cCmGP7fM6i94YGMwygznS/P1tYuU/hn7Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773162577586461.0161650108787; Tue, 10 Mar 2026 10:09:37 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250385.1547858 (Exim 4.92) (envelope-from ) id 1w00a4-0001fg-5R; Tue, 10 Mar 2026 17:09:16 +0000 Received: by outflank-mailman (output) from mailman id 1250385.1547858; Tue, 10 Mar 2026 17:09:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00a4-0001ee-0r; Tue, 10 Mar 2026 17:09:16 +0000 Received: by outflank-mailman (input) for mailman id 1250385; Tue, 10 Mar 2026 17:09:14 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00a2-0001QA-8G for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:14 +0000 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [2a00:1450:4864:20::330]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id dbfb5bb6-1ca3-11f1-9ccf-f158ae23cfc8; Tue, 10 Mar 2026 18:09:12 +0100 (CET) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-485445e80bdso8157385e9.0 for ; Tue, 10 Mar 2026 10:09:12 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:11 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: dbfb5bb6-1ca3-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162551; x=1773767351; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dQTAxI2vfkx2VNhH7t+uCNbpYCzRGkHrgeV3afpytNg=; b=kIjMY2TcOtVm0g3FH3qXIIVTveg8pfwxQiN1UaWiKLI1fZEE8HG/LKLIhsdl0rAsh0 aq/FFZcQtk17wFCtGONbgOBUZZOnrKVqbftQ2dmEwfetAuEss+9wvpJBkjm+IwCecz2o VYhBe7tYXanN0Ty6qFlPuxfjBRzUNAkBPNLxnDiTXxp+kdKoHGrdpwWeBZZy4VvFnprc mlT9NKMjz2LlewR5T90QVcGTGyApkbsK2sdAPBehqrif06Zxl40wZ0pILSZOG7GTkijz 62ZrQXWyHa9ltAck5tcpUTV0T9wVouuOpoQbxBscADJ+CL/JI2YYr0Gg3PEUDSy+QxOh DWEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162551; x=1773767351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dQTAxI2vfkx2VNhH7t+uCNbpYCzRGkHrgeV3afpytNg=; b=OpqSUlkLAp5FiFhB3WgTZ62cqOqCiFrSJgdjMowzjBgjw1QZ+yPPFf257MXOmNhXow M+XVDU+6NRyJzqkXxB7Dj62plnc7bzzir4jIRFORGYbA9tXTUVeywR6KpDaJuS/QP5tt 1E9rP7t+cO8dFNJ8NYG5fac8ZLztGPFtWGVSz1oy1vX3t4skoi/3AkxmtNSwo6zTdHGk 8t6Amvk8r8dLscuHQ1KedLFt6rwzrAsD28i0eVJ0OHyWH9FNcjm03E8S+nPuCr4RroPA wyF9ki6YRuI0bBepqN0moTIp/Dr5VmMlaHyH4hx2b6xLXlA0ivHT/aHww33BtiG6wiFR rpEw== X-Gm-Message-State: AOJu0Yz9IObBU1SDPmzipXcRqWwaUXBqSBPm9K6cs90ipWcVQfB17JrQ mzk1AUyZ+9Q89eMK4LsnGAoy1sgYyjtnG0Bzyf5Jkzau2l4fFosBkQI8KZLigJo7 X-Gm-Gg: ATEYQzxT76sa6bVxEiqIc8mFvyMGd4kKUJtTPeiD1/ZqBUdvKlvEaiINWl12AM6rd7M /wWvqmFfT/yrsELfQhN/LWLjqwprkomjoDYKIB0Gee39Tch+VgSs+5B6S4tO3mctHgS4oBRGnbx lNpckjTO1QAcMSs6oHNpTNuJHjdodotpzsnPh2JeE/StQI7mpkiVTwwVCJTPbXhm6nqRGR8/Alj 6Otulw6vb4H0byMUKNBRepDoivlroMTQZOM6Xaqlk1Lv8OHdD/MN1VJnDgmLAZl/4grOCUpH+J7 fOIJ+WAdZ/Hg9UcaW4mKUOwvK+I11zyszQ/8M0bCcoGzlrx+gwiKnRsVyEihTjtKNDvjksvvCO5 /yImGnLXE4QYRkcJQGeCVNdX5b9AJy6CBBQpC81U06/Hy+NJcFYY2q/GKEddyQWnmpu+Zm+3ThG sBg2VhW0saqCJcn07ekZQ0xMMZl04z2wcXyS+0SDE7MqlsssSsntkAH0hOoWhGNdf/lBf7sg== X-Received: by 2002:a05:600c:6995:b0:485:3a27:a961 with SMTP id 5b1f17b1804b1-4853a27a9eamr154877525e9.0.1773162551415; Tue, 10 Mar 2026 10:09:11 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 02/27] xen/riscv: Implement construct_domain() Date: Tue, 10 Mar 2026 18:08:35 +0100 Message-ID: <3a86599284108e6f2a27488a03145f8dd1b71def.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162589601158500 Content-Type: text/plain; charset="utf-8" Implement construct_domain() function for RISC-V, which performs initial se= tup for the domain's first vCPU, loads the kernel, initrd, and device tree, and sets up guest CPU registers for boot. It also creates additional vCPUs up to max_vcpus and assigns the device tree address and boot cpuid in registers. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/domain-build.c | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 xen/arch/riscv/domain-build.c diff --git a/xen/arch/riscv/domain-build.c b/xen/arch/riscv/domain-build.c new file mode 100644 index 000000000000..0ce903a911ae --- /dev/null +++ b/xen/arch/riscv/domain-build.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +#include +#include + +int __init construct_domain(struct domain *d, struct kernel_info *kinfo) +{ + struct vcpu *v =3D d->vcpu[0]; + struct cpu_user_regs *regs =3D vcpu_guest_cpu_user_regs(v); + + BUG_ON(d->vcpu[0] =3D=3D NULL); + BUG_ON(v->is_initialised); + + kernel_load(kinfo); + initrd_load(kinfo, copy_to_guest_phys); + dtb_load(kinfo, copy_to_guest_phys); + + regs->sepc =3D kinfo->entry; + + /* Guest boot cpuid =3D 0 */ + regs->a0 =3D 0; + regs->a1 =3D kinfo->dtb_paddr; + + for ( unsigned int i =3D 1; i < d->max_vcpus; i++ ) + { + if ( vcpu_create(d, i) =3D=3D NULL ) + { + printk("Failed to allocate %pd v%d\n", d, i); + break; + } + + printk("Created vcpu %d for %pd\n", i, d); + } + + domain_update_node_affinity(d); + + v->is_initialised =3D 1; + clear_bit(_VPF_down, &v->pause_flags); + + return 0; +} --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773162579; cv=none; d=zohomail.com; s=zohoarc; b=RL6Nl28u9dkPZY2NgOWy/8d5LIYuSGkzFwaqLzkOG+lKSkKr1yx79wFicSm1XEOjXVuIcYKrc5RNMd/xncvmSRsbg9A7BZTfilg52PLZYjK36A73JEp4jUydFYYul9gydVb0IxifkSAqrnLFjjmlW7ZIQjDb58hcoNu7eowtgbI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773162579; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZTdWdjcrO6LbYgQhxDIWi1k5AvTcDOv59FKJtZgzw4Y=; b=eRdtMtRFm/c3vmwnBtb1N0+9ZtoeaOADQHWXmO42IixWG3VLASZU9IcKA20lHXt6/9x7dftM3eMRSC6ufhElpn65u5xsQqHLPFcHN8ZPblZG6SixT6D30B/ULQKQHkzodnMpn3Ps/VM13qC+YtDdzK4mFoP15+S7S0dWBbhxlhI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773162579426241.2121123512503; Tue, 10 Mar 2026 10:09:39 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250386.1547864 (Exim 4.92) (envelope-from ) id 1w00a4-0001mV-FF; Tue, 10 Mar 2026 17:09:16 +0000 Received: by outflank-mailman (output) from mailman id 1250386.1547864; Tue, 10 Mar 2026 17:09:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00a4-0001lY-AG; Tue, 10 Mar 2026 17:09:16 +0000 Received: by outflank-mailman (input) for mailman id 1250386; Tue, 10 Mar 2026 17:09:14 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00a2-0001Q4-Hp for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:14 +0000 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [2a00:1450:4864:20::331]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id dcbe1f1b-1ca3-11f1-b164-2bf370ae4941; Tue, 10 Mar 2026 18:09:13 +0100 (CET) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4852a9c6309so37120805e9.0 for ; Tue, 10 Mar 2026 10:09:13 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:12 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: dcbe1f1b-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162553; x=1773767353; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZTdWdjcrO6LbYgQhxDIWi1k5AvTcDOv59FKJtZgzw4Y=; b=Pq+32YmSwW69cDEgpXSzatnouzEHbw6wKVbf0WjLKqmyXj1S97/e+R66ZR7/lfA9uF /gqm5n26AS7l9jrWRXCFCMjebCvDBa+s+yzHDh72tmVkwf+BVWH5vejURnXP2rf8DEw8 HdMUvVwCcFbQxzNJu2piHTqjWgsK9oI3RLgkM04vTUxfPUFfpp5+CUFFOuu4r73TYHAd JTuBIgnDHxWgaVMuUovHwHgocV8duEJS6vvU4kXfFj6zOE3pvqAGh955mjVDqg+GyrTz J3sVEWROd2oodR0vM0dLOGE3wnrJo/58ctoZbWSGe+pydI48W2W9c7gaHlmmLk89CjbE OEDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162553; x=1773767353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ZTdWdjcrO6LbYgQhxDIWi1k5AvTcDOv59FKJtZgzw4Y=; b=YXaNUCxWo5igCJ1u1SqSz37yOJDzZf6hZfbXqZuzHExJiTqZhVNnvqQlIxbVMbaYZw YyM/MDuaVEik9FDlCU3iHr33XyoSIMEHy8t+YANM5shnB2ZUoP2AO53DZRtFSuMAkt6M gZHMgrv3cuOZDrDGNyh6g6Z+F0w2DogQ+3YwXhYOMlyjEa8a0StB6G8x6cqFHwgDeRhX wKY/ISNk/Y5dvaPP7grZmJOrHVTr63xnlZbiA1CEFD/Rx7bT7HrZFGPjaY2ryLaBTj0k LrVqC8oNn3r9NgkSBJ8g8m+bBVO+4q6cRInWVP/VUiY5V3qy6EBQOLdptyJJvf0gmMFg BDLA== X-Gm-Message-State: AOJu0Yx0tPC21I/FSMRWVkxTKDKq0Nyn+LlkGLzJTDCqVfgJ66uZy5eu 9tq0bX69KeByqpVwDmB+bNcKd7cM4tfrnAxyOpIXFefrp62xReo+72oJvRP/FZC7 X-Gm-Gg: ATEYQzwlU/BvtplZp3dBlRD9Cq1D1iSOZ0rE1ghQDjKTxorm+0yhpiM6/J9H+UsjjIV 0hKmI0HGe5KjNjsrV2QFSIB9gJakkg8wcPsFhNxqZdKkBmnWx5ErhxRDCSSet1TiGtOL/jASqa7 eVVEShUMSu+eKAwWeNyqSneuzRtn32clD3Ozde/H9lzguiYDt8OMIxy9DnzhXNTRf7UFIRFC7oS +z1QUNmb9YqeUbzPJF048wNREyApszLKq0K6K3//DIYMrGHr8yo58pLqn/US1P1iWvjYcxRg7xS Lg1J7iTT+x7YhdQg6tKiEbIZMZj7YqT/VbACBLaG2DbvnLvVDDoYDLczDe61I8YF5lY9OaIS2io 6x+pnXaExokpXWju+C3A+XP1LJfk4NFs/1SiU1mR7XO38CChfC4At5Tb7GkfC0BnwQjzcliuEeY of+SKD4z/RvNyjkvb8cLer67OWp+ETQCQpRT39dpX5Ctx3RoL4MVfOBH8aW4rXklNP2A== X-Received: by 2002:a05:600c:8b01:b0:477:561f:6fc8 with SMTP id 5b1f17b1804b1-485269195afmr262309165e9.5.1773162552633; Tue, 10 Mar 2026 10:09:12 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 03/27] xen/riscv: implement prerequisites for domain_create() Date: Tue, 10 Mar 2026 18:08:36 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162580560158500 Content-Type: text/plain; charset="utf-8" arch_domain_create() and arch_sanitise_domain_config() are prerequisites for domain_create(). arch_sanitise_domain_config() currently returns 0, as there is no specific work required at this stage. arch_domain_create() performs basic initialization, such as setting up the = P2M and initializing the domain's virtual timer. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/domain.c | 27 +++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 3 +++ xen/arch/riscv/stubs.c | 9 +-------- xen/include/public/device_tree_defs.h | 1 + 4 files changed, 32 insertions(+), 8 deletions(-) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 7e3070101714..515735b32e30 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -288,6 +288,33 @@ void sync_vcpu_execstate(struct vcpu *v) /* Nothing to do -- no lazy switching */ } =20 +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + return 0; +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + int rc =3D 0; + + if ( is_idle_domain(d) ) + return 0; + + if ( (rc =3D p2m_init(d)) !=3D 0) + goto fail; + + d->arch.next_phandle =3D GUEST_PHANDLE_LAST + 1; + + return rc; + + fail: + d->is_dying =3D DOMDYING_dead; + arch_domain_destroy(d); + return rc; +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 0caacf92b5a2..506365f199c7 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -95,6 +95,9 @@ struct arch_domain { #ifdef CONFIG_ARCH_PAGING_MEMPOOL struct paging_domain paging; #endif + + /* Next unused device tree phandle number */ + uint32_t next_phandle; }; =20 #include diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index acbb5b9123ea..d139f8786cb5 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -101,14 +101,7 @@ void dump_pageframe_info(struct domain *d) BUG_ON("unimplemented"); } =20 -int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) -{ - BUG_ON("unimplemented"); -} - -int arch_domain_create(struct domain *d, - struct xen_domctl_createdomain *config, - unsigned int flags) +void vcpu_switch_to_aarch64_mode(struct vcpu *v) { BUG_ON("unimplemented"); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:13 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: dd807af5-1ca3-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162554; x=1773767354; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y2l9GSTVdHf37ct2dJEvx0io7ScAIs5lEweSLfZGouo=; b=iIuPKO4b+qUhMQwTITvT3pvAvG6IJR50piZmXbxla5v5v6ZUcQx+0PAERuup0F1qlo g+FE2eOCLD8mjE0gXjHmdmxpAgiwWuZdOaWlO3IefvaqRIQtkhnHWmOiYGIkKNtXYLew c2TrlXp0JEhUZGoOBTJoT1jiqDQ4t2nLhvhT/16OSaxAflo58U8L5NMDJPbRgwvkkOrw fWej3C0xAQ5hvmvPh4hOgQ64RBzdavG4B9uU4sVCEA6lkpInrhHeTedkBC8wQvIQ5Ofa iCbzDRUgAoHILRIEB6kt9FMU1QXS3xOrp1Bu1cVxBuM5K6SlH3YZaNZXNmzLEps2tA10 RDMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162554; x=1773767354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=y2l9GSTVdHf37ct2dJEvx0io7ScAIs5lEweSLfZGouo=; b=MusXI6CI1bXU+TVEazp83y9f5vrpZoeWQygPJLTYc8pkPDwi0kXNrN6j/DJBMvFdkR TfyBMUtgZT+42ctFQ7YzI/yO6Pl3O8JM99nXBq+W92s3loFIDBeYZzEfgZqIlz3PPxy+ w79mR6Oy4biyVBq/xCutI9F4GcMnd0zHru5fKLyuZB7OBM3BUoaK4rZHI5u40VYAzqJw SFR585z/HuBYnUiM3sWrnsMIc/dNVh9txRv7v19/A6GuY+ATM1cDC+5CeF4EcihlB7R3 3SZjUzSZ2LBCKmnKzq5MEJHcWtq852JTkTTQCIEvwhe/KwIu0fN7HMHf3tDIp6ny1DVS e8ew== X-Gm-Message-State: AOJu0YyN9sxMqexhh67wh+yTR/Rvo6e2m3q+QyI5dufTLdKT+48mvyfE Y8eXMJN3hqQYwYwpWsaGAmz33zKA7++ouWIAss0mid7kiihgBM0Ny3wQ3xBJcKMt X-Gm-Gg: ATEYQzzbuSk7Qv9YN0xCaZhJA+xrSIbwJQSnzkdGONzi20jpYAa5jeJ+qlhKXz7dIGX Hju9abVBhIt/V0A88CeIKgGv+uuP5OXVAwMO37rxr6JcgLyCuLn9r2UpCTV7Q9Ei5QQ0j/Ve6G/ rPSNoTWaHaG5/oAp1zjMslUuoM5PsHsybKG0YvtgQWe0PzVTr1BrRfVmsn9YP+fJOZcRnAzEbn6 BeuwwNAmbOhBJfdptYXPhmSObybJO2HBbOyd6zM2A6H11omDItrO34DIJMkBNi1qdgwy1aSfXaG CUmVfRvLB5SuKDHBX6a8W23LoKSu40yI0HgOv0wOJr6h/T9a241pz19HwngaC7I7qkBWkjVZwGC xoXqB+OH41NMjRPPx+560g4IrgMlBssqezdvb5JCk38T5oD+qGu6o1rTc/vhtopr4xrrFC0JFRA XZ849b55hPNphvrboaCMIU1PzBysaAr0Rf2rL0lLGUyl3kv4sXeGMcn1rrTBAvguicJg== X-Received: by 2002:a05:600c:a12:b0:483:badb:618f with SMTP id 5b1f17b1804b1-48526966b07mr244053275e9.25.1773162553878; Tue, 10 Mar 2026 10:09:13 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 04/27] xen/riscv: rework G-stage mode handling Date: Tue, 10 Mar 2026 18:08:37 +0100 Message-ID: <2c8f1ea25b8d3ec78b00510fbe604a87e759e194.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162584491158500 Content-Type: text/plain; charset="utf-8" Rework G-stage mode handling to make the selected mode descriptor reusable outside of p2m initialization. As max_gstage_mode is going to be reused by code that creates CPU nodes for guest domains, not only max_gstage_mode->mode but also max_gstage_mode->name is required. To support this, make max_gstage_mode a global pointer to one = of the entries in a global modes[] array, and remove get_max_supported_mode(). Update struct p2m_domain to store a pointer to a mode descriptor instead of embedding the structure directly. Refactor the modes[] array so that mode->name contains only the MMU scheme name (without the "x4" suffix), as this value is reused when filling the maximum MMU type passed to the guest. According to DT bindings [1], the MMU type must not include the "x4" suffix. Use "none" for the Bare mode to match the DT binding requirements. Adjust modes[]->paging_levels to represent the maximum paging level rather than the total number of levels. This ensures that P2M_ROOT_LEVEL() and its users behave correctly without relying on hardcoded p2m mode values. Finally, drop __initconst from the modes[] declaration, as the array is referenced via p2m->mode and max_gstage_mode beyond the init stage. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /Documentation/devicetree/bindings/riscv/cpus.yaml?h=3Dv6.19-rc3#n82 Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/p2m.h | 7 ++-- xen/arch/riscv/p2m.c | 60 +++++++++++++------------------- xen/arch/riscv/vmid.c | 2 +- 3 files changed, 30 insertions(+), 39 deletions(-) diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/= p2m.h index c6d846b96fb4..4441c0400b83 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -13,7 +13,7 @@ =20 #define P2M_ROOT_ORDER (ilog2(GSTAGE_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT) #define P2M_ROOT_PAGES BIT(P2M_ROOT_ORDER, U) -#define P2M_ROOT_LEVEL(p2m) ((p2m)->mode.paging_levels) +#define P2M_ROOT_LEVEL(p2m) ((p2m)->mode->paging_levels) =20 /* * According to the RISC-V spec: @@ -58,6 +58,8 @@ struct gstage_mode_desc { char name[8]; }; =20 +extern const struct gstage_mode_desc *max_gstage_mode; + /* Per-p2m-table state */ struct p2m_domain { /* @@ -71,7 +73,7 @@ struct p2m_domain { /* The root of the p2m tree. May be concatenated */ struct page_info *root; =20 - struct gstage_mode_desc mode; + const struct gstage_mode_desc *mode; =20 /* Back pointer to domain */ struct domain *domain; @@ -218,7 +220,6 @@ static inline bool arch_acquire_resource_check(struct d= omain *d) } =20 void guest_mm_init(void); -unsigned char get_max_supported_mode(void); =20 int p2m_init(struct domain *d); =20 diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 886e06196ba2..dce1eb205ec9 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -45,18 +45,32 @@ struct p2m_pte_ctx { unsigned int level; /* Paging level at which the PTE resides.= */ }; =20 -static struct gstage_mode_desc __ro_after_init max_gstage_mode =3D { - .mode =3D HGATP_MODE_OFF, - .paging_levels =3D 0, - .name =3D "Bare", -}; - /* * Set to the maximum configured support for IPA bits, so the number of IP= A bits can be * restricted by external entity (e.g. IOMMU). */ unsigned int __read_mostly p2m_ipa_bits =3D PADDR_BITS; =20 +static const struct gstage_mode_desc modes[] =3D { + /* + * Based on the RISC-V spec: + * Bare mode is always supported, regardless of SXLEN. + * When SXLEN=3D32, the only other valid setting for MODE is Sv32. + * When SXLEN=3D64, three paged virtual-memory schemes are defined: + * Sv39, Sv48, and Sv57. + */ + [0] =3D { HGATP_MODE_OFF, 0, "none" }, +#ifdef CONFIG_RISCV_32 + [1] =3D { HGATP_MODE_SV32X4, 1, "sv32" } +#else + [2] =3D { HGATP_MODE_SV39X4, 2, "sv39" }, + [3] =3D { HGATP_MODE_SV48X4, 3, "sv48" }, + [4] =3D { HGATP_MODE_SV57X4, 4, "sv57" }, +#endif +}; + +const struct gstage_mode_desc * __ro_after_init max_gstage_mode =3D &modes= [0]; + static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg); =20 static inline void p2m_free_metadata_page(struct p2m_domain *p2m, @@ -69,11 +83,6 @@ static inline void p2m_free_metadata_page(struct p2m_dom= ain *p2m, } } =20 -unsigned char get_max_supported_mode(void) -{ - return max_gstage_mode.mode; -} - /* * If anything is changed here, it may also require updates to * p2m_{get,set}_type(). @@ -154,23 +163,6 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *= p2m, gfn_t gfn) =20 static void __init gstage_mode_detect(void) { - static const struct gstage_mode_desc modes[] __initconst =3D { - /* - * Based on the RISC-V spec: - * Bare mode is always supported, regardless of SXLEN. - * When SXLEN=3D32, the only other valid setting for MODE is Sv3= 2. - * When SXLEN=3D64, three paged virtual-memory schemes are defin= ed: - * Sv39, Sv48, and Sv57. - */ -#ifdef CONFIG_RISCV_32 - { HGATP_MODE_SV32X4, 2, "Sv32x4" } -#else - { HGATP_MODE_SV39X4, 3, "Sv39x4" }, - { HGATP_MODE_SV48X4, 4, "Sv48x4" }, - { HGATP_MODE_SV57X4, 5, "Sv57x4" }, -#endif - }; - for ( unsigned int mode_idx =3D ARRAY_SIZE(modes); mode_idx-- > 0; ) { unsigned long mode =3D modes[mode_idx].mode; @@ -179,16 +171,16 @@ static void __init gstage_mode_detect(void) =20 if ( MASK_EXTR(csr_read(CSR_HGATP), HGATP_MODE_MASK) =3D=3D mode ) { - max_gstage_mode =3D modes[mode_idx]; + max_gstage_mode =3D &modes[mode_idx]; =20 break; } } =20 - if ( max_gstage_mode.mode =3D=3D HGATP_MODE_OFF ) + if ( max_gstage_mode->mode =3D=3D HGATP_MODE_OFF ) panic("Xen expects that G-stage won't be Bare mode\n"); =20 - printk("Max supported G-stage mode is %s\n", max_gstage_mode.name); + printk("Max supported G-stage mode is %sx4\n", max_gstage_mode->name); =20 csr_write(CSR_HGATP, 0); =20 @@ -289,7 +281,7 @@ static void clear_and_clean_page(struct page_info *page= , bool clean_dcache) unsigned long construct_hgatp(const struct p2m_domain *p2m, uint16_t vmid) { return MASK_INSR(mfn_x(page_to_mfn(p2m->root)), HGATP_PPN_MASK) | - MASK_INSR(p2m->mode.mode, HGATP_MODE_MASK) | + MASK_INSR(p2m->mode->mode, HGATP_MODE_MASK) | MASK_INSR(vmid, HGATP_VMID_MASK); } =20 @@ -369,9 +361,7 @@ int p2m_init(struct domain *d) #endif =20 /* TODO: don't hardcode used for a domain g-stage mode. */ - p2m->mode.mode =3D HGATP_MODE_SV39X4; - p2m->mode.paging_levels =3D 2; - safe_strcpy(p2m->mode.name, "Sv39x4"); + p2m->mode =3D &modes[2]; =20 return 0; } diff --git a/xen/arch/riscv/vmid.c b/xen/arch/riscv/vmid.c index 8fbcd500f24d..11c7e9d6d6c8 100644 --- a/xen/arch/riscv/vmid.c +++ b/xen/arch/riscv/vmid.c @@ -52,7 +52,7 @@ static DEFINE_PER_CPU(struct vmid_data, vmid_data); static unsigned int vmidlen_detect(void) { unsigned int vmid_bits; - unsigned char gstage_mode =3D get_max_supported_mode(); + unsigned char gstage_mode =3D max_gstage_mode->mode; =20 /* * According to the RISC-V Privileged Architecture Spec: --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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The following changes are introduced: - According to the RISC-V privileged specification, M-mode software controls the XLEN value used by S-mode and U-mode. For RV64 harts, the SXL and UXL fields of the mstatus register are WARL fields that define the XLEN for S-mode and U-mode. The XLEN value is provided by M-mode software (OpenSBI in the case of Xen) via the riscv,isa DT property. Introduce and initialize an xlen variable when parsing the host riscv,isa string in riscv_isa_parse_string(). - Introduce the guest_isa_str variable to store the riscv,isa string generated for a guest domain during riscv,isa property parsing. Update match_isa_ext() to populate guest_isa_str accordingly. - Introduce guest_unsupp_bmp and guest_unsupp_exts[] to filter out ISA extensions that should not be exposed to guests. For example, FPU-related extensions are currently not supported for guests (at the moment) and are therefore removed from the guest riscv,isa string. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/cpufeature.c | 33 +++++++++++++++++++++++++ xen/arch/riscv/include/asm/cpufeature.h | 2 ++ 2 files changed, 35 insertions(+) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 987d36dc7eee..d7e483603dbe 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -38,6 +38,8 @@ struct riscv_isa_ext_data { /* Host ISA bitmap */ static __ro_after_init DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX); =20 +static __ro_after_init unsigned int xlen; + static int __init dt_get_cpuid_from_node(const struct dt_device_node *cpu, unsigned long *dt_cpuid) { @@ -160,6 +162,19 @@ static const struct riscv_isa_ext_data __initconst req= uired_extensions[] =3D { RISCV_ISA_EXT_DATA(svpbmt), }; =20 +static const unsigned int __initconst guest_unsupp_exts[] =3D { + RISCV_ISA_EXT_f, + RISCV_ISA_EXT_d, + RISCV_ISA_EXT_h, + RISCV_ISA_EXT_q, + RISCV_ISA_EXT_v, +}; + +static __ro_after_init DECLARE_BITMAP(guest_unsupp_bmp, RISCV_ISA_EXT_MAX); + +#define MAX_GUEST_ISA_STR_LEN 256 +char guest_isa_str[MAX_GUEST_ISA_STR_LEN]; + static bool __init is_lowercase_extension_name(const char *str) { /* @@ -193,6 +208,15 @@ static void __init match_isa_ext(const char *name, con= st char *name_end, !memcmp(name, ext->name, name_end - name) ) { __set_bit(ext->id, bitmap); + + if ( riscv_isa_extension_available(guest_unsupp_bmp, ext->id) ) + break; + + if ( ext->id >=3D RISCV_ISA_EXT_BASE ) + safe_strcat(guest_isa_str, "_"); + + safe_strcat(guest_isa_str, ext->name); + break; } } @@ -207,13 +231,17 @@ static int __init riscv_isa_parse_string(const char *= isa, #if defined(CONFIG_RISCV_32) if ( isa[2] !=3D '3' && isa[3] !=3D '2' ) return -EINVAL; + xlen =3D 32; #elif defined(CONFIG_RISCV_64) if ( isa[2] !=3D '6' && isa[3] !=3D '4' ) return -EINVAL; + xlen =3D 64; #else # error "unsupported RISC-V bitness" #endif =20 + snprintf(guest_isa_str, sizeof(guest_isa_str), "rv%d", xlen); + /* * In unpriv. specification (*_20240411) is mentioned the following: * (1) A RISC-V ISA is defined as a base integer ISA, which must be @@ -487,6 +515,11 @@ void __init riscv_fill_hwcap(void) bool all_extns_available =3D true; struct trap_info trap; =20 + for ( i =3D 0; i < ARRAY_SIZE(guest_unsupp_exts); i++ ) + { + __set_bit(guest_unsupp_exts[i], guest_unsupp_bmp); + } + riscv_fill_hwcap_from_isa_string(); =20 if ( bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX) ) diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index ef02a3e26d2c..aabbbf0c2cc3 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -43,6 +43,8 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_MAX }; =20 +extern char guest_isa_str[]; + void riscv_fill_hwcap(void); =20 bool riscv_isa_extension_available(const unsigned long *isa_bitmap, --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:15 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: df095baa-1ca3-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162556; x=1773767356; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B5Dqi7QE0P+NZcaNQ4Uuko5WRqJ3CVy0ngqKC6es19A=; b=nD53nNjwmA/lbqg4xCHcfXQrbVYhV5OqWNbt6K5tiI1lciiMxxVNBrIkCP5Qhq86PQ xz4tMjoen8Fch0yA33lS3NPN65kRYnV9yg3clqoaLAbFFqPIlmVGiQQqcDbvqhT7Istd k0BhuEdjc1LU86Mrk8wbxG2o/T7Pv9lQ/JxrOWEhAkUpriL4FUeHBvb4hIiy/7UTSr/e lPaknNQlGwefi3kCGFLNCmxex7eNv9JjD0WfLoSqdTcdaV8QgCWFwt8td8hDpdWOnpzq aOw0BpE63w7nGdb6HgzMli3QhOBPlgEZ8Vv11KWDW4oUUSX+2uWINTQXZa072E6HvqTY bakA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162556; x=1773767356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=B5Dqi7QE0P+NZcaNQ4Uuko5WRqJ3CVy0ngqKC6es19A=; b=Qn53DSGpIPvAvjCejPB1+Jv3XqYdNUvDRHpRjGKzYMEZlcQJ/d6e1rh4XH7s+bf6jZ hbJWiXkBIb2cPyarJCFIh8eGkHq0sKx720vhgZHehRgSkI5CCtBHAaL50qSneNq/tpol XS/fxJmjuzqK0gCeecQvVL7KbLmDVfT1b/H2BEfAY1qLVuhXUD8Zg3h1Nnplrrk2nkAW cFsPBHg8rh9cvIxPNeLw3DIVAPq2kgYf4egY01OGiZWvfA/9to1L++X+2qGxiGvifF+z l1AYbK/SC9gZgdb/jPgYOhJvPtwU05ht+ar9HY2a9c/cooZCfSuKoP/UVlWX6TbuBU/+ LL8w== X-Gm-Message-State: AOJu0Yz4Wwi508SJb20q5EBZmfyziBBrYGZqgFDeWXTsMtfxIT7yY1Xg 9lg8i5NNTx52qjorVXHm4nMpW785edZivoFKZxnywjHHTMaoUK7Rk5XDFfwH+WOc X-Gm-Gg: ATEYQzztahiCkTpZWpKbUqqmkRVRxPJLPGQKl9LHil858Ki5j0MCFZ0QB0yE2gPFB61 WiM4pqRCDoTSdOgfP6VH/z+i6cbF78tBe2bRiO9WykGVHVM2vQt+cU/3hLX0aYdpRHr5vzoYpED ibcG6E37ROOwzTMxQDpiF6siJbbEwY+zlt9Nab/oL8NK2j6MOhJhWrYcCoq4hEPjhtwJtY/zLlm Y4ajGR1bm6Cu50+yPbDQTNini2LpsRxz9WC3EW442lX2XvGYe+jZlYrapOMe/kqbauIbPF6+FEJ Om/89IFMRK4W2P4ecmwGlXLb1loAzqS/M+vvfT/eRNu1IltQdrl1CEK+tUlZX4+CVFd1mLezETt axs3TCPL4DDSqMX+2A+TVMhQQj3vPGXAUJctB7TNtqsCkxcxj2esdcawoLXd3dQeer6IRP5Jhh3 +RdJ3WyTJIb7Gf3T3iT7R5JOnfJ5WobxMPVg8FxaQu+Uz2yn7sz6Duhrhq3YSyemsoXA== X-Received: by 2002:a05:600c:3f0b:b0:485:3bb5:92c5 with SMTP id 5b1f17b1804b1-4853bb598e8mr120108175e9.14.1773162556236; Tue, 10 Mar 2026 10:09:16 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 06/27] xen/riscv: implement make_cpus_node() Date: Tue, 10 Mar 2026 18:08:39 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162586432158500 Content-Type: text/plain; charset="utf-8" Implement make_cpus_node() to create cpus node for a guest domain. This function is going to be use by common dom0less code during construction domain. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain-build.c | 108 ++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index b1514f1514a2..6c6c58ed1ac0 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,6 +1,7 @@ obj-y +=3D aplic.o obj-y +=3D cpufeature.o obj-y +=3D domain.o +obj-y +=3D domain-build.o obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o obj-y +=3D entry.o obj-y +=3D guestcopy.o diff --git a/xen/arch/riscv/domain-build.c b/xen/arch/riscv/domain-build.c index 0ce903a911ae..633f02e42c5e 100644 --- a/xen/arch/riscv/domain-build.c +++ b/xen/arch/riscv/domain-build.c @@ -3,8 +3,10 @@ #include #include #include +#include #include =20 +#include #include #include =20 @@ -44,3 +46,109 @@ int __init construct_domain(struct domain *d, struct ke= rnel_info *kinfo) =20 return 0; } + +int __init make_cpus_node(const struct domain *d, void *fdt) +{ + int res; + const struct dt_device_node *cpus =3D dt_find_node_by_path("/cpus"); + unsigned int cpu; + u32 timebase_frequency; + bool frequency_valid; + uint32_t *next_phandle =3D &((struct domain *)d)->arch.next_phandle; + + dt_dprintk("Create cpus node\n"); + + if ( !cpus ) + { + dprintk(XENLOG_ERR, "Missing /cpus node in the device tree?\n"); + return -ENOENT; + } + + frequency_valid =3D dt_property_read_u32(cpus, "timebase-frequency", + &timebase_frequency); + + res =3D fdt_begin_node(fdt, "cpus"); + if ( res ) + return res; + + res =3D fdt_property_cell(fdt, "#address-cells", 1); + if ( res ) + return res; + + res =3D fdt_property_cell(fdt, "#size-cells", 0); + if ( res ) + return res; + + if ( frequency_valid ) + res =3D fdt_property_cell(fdt, "timebase-frequency", timebase_freq= uency); + + for ( cpu =3D 0; cpu < d->max_vcpus; cpu++ ) + { + char buf[64]; + uint32_t reg =3D cpu_to_fdt32(cpu); + + snprintf(buf, sizeof(buf), "cpu@%u", cpu); + res =3D fdt_begin_node(fdt, buf); + if ( res ) + return res; + + res =3D fdt_property(fdt, "reg", ®, sizeof(reg)); + if ( res ) + return res; + + res =3D fdt_property_string(fdt, "status", "okay"); + if ( res ) + return res; + + res =3D fdt_property_string(fdt, "compatible", "riscv"); + if ( res ) + return res; + + BUILD_BUG_ON((sizeof("riscv,") + sizeof_field(struct gstage_mode_d= esc, name) + 1) >=3D sizeof(buf)); + snprintf(buf, sizeof(buf), "riscv,%s", max_gstage_mode->name); + res =3D fdt_property_string(fdt, "mmu-type", buf); + if ( res ) + return res; + + res =3D fdt_property_string(fdt, "riscv,isa", guest_isa_str); + if ( res ) + return res; + + res =3D fdt_property_string(fdt, "device_type", "cpu"); + if ( res ) + return res; + + res =3D fdt_begin_node(fdt, "interrupt-controller"); + if ( res ) + return res; + + res =3D fdt_property_string(fdt, "compatible", "riscv,cpu-intc"); + if ( res ) + return res; + + res =3D fdt_property_cell(fdt, "#interrupt-cells", 1); + if ( res ) + return res; + + res =3D fdt_property(fdt, "interrupt-controller", NULL, 0); + if ( res ) + return res; + + res =3D fdt_property_u32(fdt, "phandle", (*next_phandle)++); + if ( res ) + return res; + + /* end of interrupt-controller */ + res =3D fdt_end_node(fdt); + if ( res ) + return res; + + res =3D fdt_end_node(fdt); + if ( res ) + return res; + } + + res =3D fdt_end_node(fdt); + + return res; +} --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773162587; cv=none; d=zohomail.com; s=zohoarc; b=nx4OUuuyJtCD55ity4theE46cOxNExm2G73tDPQggabjV0Uv+RKXygf7I7GbgG71TvEW4srskg85IBU/7MBEf5SX2rfNJB4ZSydn5tnK7yac2y9PmX39vbhUjeG6iWaNPQVRdZih1/VwVmWnuPDAw2bc/9lmGZXfTvnLu2N/xOY= ARC-Message-Signature: i=1; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:17 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: df90eba6-1ca3-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162557; x=1773767357; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WI2GmymuZn5ZjF6sh0Pndyef5xHCptAQOPGu6/MNHsM=; b=bZDa2dD6Q+j7MrXH/ZZyIvTY0Nnz7lWJ9KKfC4nl98XtkpGVoRyqi5c1knYFbNhUdk wMIDA0aruN5LBiTmanT8k24o7lLTdRdjLb362aVbt/IaJt3yFYvqLjBhaHw5o6qLKsoD sdckNLKjOCV+vQLf9UIqsC0KYRGzY2Sy8UY/6L6XKyDRyj6d/yzVb9dC/aV97OLX8enT go6lRkUqokO7gkWQmLYlXSTEGAljMDCzYXGCrogaPokidV5SOHNBWGWgwT5yU8Pg97/t 9fFjvU5IePrf6hDvFVcbtk+xrYy4/jl13QzrNxmO/6IwqOSfN8LkcD8pH/vtAu/7R7Xd R75A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162557; x=1773767357; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=WI2GmymuZn5ZjF6sh0Pndyef5xHCptAQOPGu6/MNHsM=; b=XqqG+LAPwWLReFRUWv0hZ91Vy3TnYzCtYMAmLDEIUqlEiEEp1xAOYXPDpQGdlqtCDb epJOYwEQ5Kg7+rPk+t0oCaV6mlhDtY6IaOjftEQmcn0RXhtevr32Fqx/77vo2D7P8ruB ebbdfp5koFDBV9TZkVKTWXrC7tUkp/0gQ1XYzcL4mzjr2Mhy23z4kOlJexUvEvWFNYRM nSYZNS/Fwn+ft0vkx9D/QwEprTUKjyoKwi19RsC0dv0Uh+lVEQhxNXxLXfIs5/PL+uiv DPYwVag7lOZjLu9eE68XnBxRhAboqRdo1KZBglbwHzMXCOw/Q2CHUcwlvKqrcT82NbYR CN7w== X-Gm-Message-State: AOJu0YwkZwVuisl22YCF+slQdADHQ3RUx3UfBqsC0+Cgy+dZJWLaNs3N L+p2TraKga5q5JR54xefxtrboSE+mZrtahNeAKcTEzKdC9HbJ9jKNnv03nlxLpxk X-Gm-Gg: ATEYQzwkJnMYF+6qhbSzJODuEM6p/TxoBlrso8hmuNNGRy7upSYqvURl6Pc2DwrL1Ru IiaBqAGHr0KdSOEJ9Gk4ij2H6UJQyE1ygt55FM4GWiiTMMFgYhSzuH/FtYfLf0H5Xq2Af7Nvdtz +nMSP/c4Ac/kWD0D2TT3ElNvcp8PbKQ6asBYzks/M7JVxZu9VJHpV3Eh13L2LOanxuhXDcfnpxU l4PJHWPZhAtHVj+fSYcDWvbFYJfw0ctdqFvXHR58EQJ2oSTjdyWObdEOUH1+q6VrUwaRs0YyJVp 4Bcsb84SDGlpg8jwh8TI+71c2MUMcwMbNaukO711KYHRWGY4hbRusHjsqdQkZGrCaBtnkCUuBWb hTZjA+wrTZlR4MjUGH1uBPnBkaffC+CLGxcHgTuTkRzOZoscrc1JRRzCoKvg+4SdDmsKex2pSMQ 2zTsDsmC8hCmG/CJjxxIfH/8YeWR5W8r/d/prLfvpwrmFF4LE2AX+G/ckvhJxEA7UP1g== X-Received: by 2002:a05:600d:f:b0:485:345b:ccb1 with SMTP id 5b1f17b1804b1-485345bce86mr165965485e9.27.1773162557447; Tue, 10 Mar 2026 10:09:17 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 07/27] xen/riscv: implement make_timer_node() Date: Tue, 10 Mar 2026 18:08:40 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162589128154101 Content-Type: text/plain; charset="utf-8" The make_timer_node() function is implemented to return 0, as RISC-V does not require the creation of a timer node. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- xen/arch/riscv/domain-build.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/riscv/domain-build.c b/xen/arch/riscv/domain-build.c index 633f02e42c5e..ae26faed09ed 100644 --- a/xen/arch/riscv/domain-build.c +++ b/xen/arch/riscv/domain-build.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include =20 @@ -152,3 +153,10 @@ int __init make_cpus_node(const struct domain *d, void= *fdt) =20 return res; } + +int __init make_timer_node(const struct kernel_info *kinfo) +{ + /* There is no need for timer node for RISC-V. */ + + return 0; +} --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773162585; cv=none; d=zohomail.com; s=zohoarc; b=mhbHApD12WreJHf2fm28PbpTgzRY2QnFybY67WLJdyFKsuN+1CngYXATdETNrNGm7h58fUJKq63MI1LjM0rNQAoGjES93fRIue8V1ooTC4QOZkL9F+N8P6HWVNvd5FBJ5wQpXEhkh+8/m5c17BcWdMiKceBffjhGBXUu/E+3kZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773162585; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nhr/YFfUk73fJbCvGKZFP0P0mCzExALFTOhZRjG1AeU=; b=fPQN87jxJZmW/lKLO0G/hegbsbG26I3oqQvTcWun79/WjvmMpbSSgj5RaqCkYUNWh75aSlmzQ9oIO+PHNO5CG5u5f2rO8rtazs4zAcZMNM4QnHWRCt2WeB5VooZ6n/dmuxar17qG30iaTxbxLR6hnKLcxMC44cKEX3Xqy8rFm+k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773162585804151.6127796784433; Tue, 10 Mar 2026 10:09:45 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250391.1547910 (Exim 4.92) (envelope-from ) id 1w00aA-00032U-7x; Tue, 10 Mar 2026 17:09:22 +0000 Received: by outflank-mailman (output) from mailman id 1250391.1547910; Tue, 10 Mar 2026 17:09:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00aA-000300-2G; Tue, 10 Mar 2026 17:09:22 +0000 Received: by outflank-mailman (input) for mailman id 1250391; Tue, 10 Mar 2026 17:09:20 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00a8-0001Q4-Af for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:20 +0000 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [2a00:1450:4864:20::331]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e0890da2-1ca3-11f1-b164-2bf370ae4941; Tue, 10 Mar 2026 18:09:19 +0100 (CET) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4853510b4f3so41185485e9.0 for ; Tue, 10 Mar 2026 10:09:19 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:18 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e0890da2-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162559; x=1773767359; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nhr/YFfUk73fJbCvGKZFP0P0mCzExALFTOhZRjG1AeU=; b=ZFB8LKD577w5idg3ca7RIHLuzqpe2Fu47tUN54QV/8l+a3/zswFtxLLB+X9pw7D70S 4kPdDAGUl6qYCf5lOijzS+sXCPjMYio140HCkdMOVoKkyqJEcw1RMxCMITOvpG2e1gzs cwUNyOq5UYaRnjNHZ3WoQObixO/L4pezOHHPrDwAXPid03gO07yqG2xbH9T0O4ILYRpi PQP8E0dPXzQWRKGnHlW4h5ZpE8Z1aCSCQZ7q8X/3k0DRioJ999zuS6GEnWT3K31Xy6Ou 4qPG+l80rJj3hTxPuNkINB0e4FcAX6KiimVdnHlRaAtWgjAYu/eaWV3OQD+phCoEH+Qq /qEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162559; x=1773767359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=nhr/YFfUk73fJbCvGKZFP0P0mCzExALFTOhZRjG1AeU=; b=SRtqobsqq4ggtMGsYnwTFEI2sP8OFabO9IMc6UiJo6/jFQRdVU55dXNL/7MB7c/uGt 7+d0rwV9JmL2DzOKvSIDomaTX4TXH6YKYJ8g+j2C6+Z3Ic9Q491spU1LKJun6BgcW7tr FsObgh5fr3ICfXBnLISHrZqsKWw9Kq5Mb7ce+5xb9VXO3MhawB4PzHrE0wIfdrGa6ng2 qu1JM52ea+B2LWbd8iKGw+zWZ+QcwTBcylMW2LKIJcawKssnSPPP0qBFvNKvIsK/oRWt tlwSzdl7DI4LndijfgqwmVgH/UPqfvoaqSWm3PpZSNf3WTk3VST8WJLxWHihATjLsBOi oyzQ== X-Gm-Message-State: AOJu0YwMN1IR8Rx3cs4SkliJPpq5z794UqsCOn0s8gWNaDYCJq1+n/Jx oSavh44WKPWBsJz3b/q5/etEdXNTz5CRk2KsC80GPXIh8XY/hk0slgElaioABJhJ X-Gm-Gg: ATEYQzwTJdFqqZUyxY1CpAZP+OOj2DXV3O1qXW2Ot8qr+T9ZNgk0UK19WrhkMMspw7g cNn+99Ilp5ax1cJFrtG8CHw+0a3JPSCKutyMv9ZUT/A1ab1oEVZ6aQZpQCLhvhErSWepTX4U1xF hlr2MpxddjImo0IcjjXok0agmijOJt14lOtwwZw8dFXED/5Fsm6B7AuKe7c8j7lsyLfkZnrk19G xwUj8exfS6GHzzZxSaBp99rIbsu9fiT1aS+ff8yYrBbwE9fqB/j+hE+WCNUGYizp9lJWnkg+gCg uLdlaOjLLAh+C/KQfT6NoIdFl/AgZIyFytAH2aXwQxqKjEG/eIc/WzUGaJA3NZ+NE9LfhNlfK5c QizKS9i4BxSGIOOfcOhlOYa7zXzh1K/WZyiT6rUotXzNv6CwBhzdR4zAiB440MUkWO9MzeEot5Z VEiLUzp+/8vQzw2TWLkZI9q9U8EmgXqx5MzlcakbESidRD3OmKxJOYp60ubdWDA+UU7w== X-Received: by 2002:a05:600c:1e2a:b0:47e:e57d:404 with SMTP id 5b1f17b1804b1-485269582efmr253670135e9.16.1773162558685; Tue, 10 Mar 2026 10:09:18 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 08/27] xen/riscv: implement make_arch_nodes() Date: Tue, 10 Mar 2026 18:08:41 +0100 Message-ID: <9c97b4bc6fb8a5e556c38cfe7e34de0eb3cbbbb0.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162586381158500 Content-Type: text/plain; charset="utf-8" No RISC-V-specific nodes need to be created at the moment, so make_arch_nodes() is implemented to simply return 0. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/dom0less-build.c | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 xen/arch/riscv/dom0less-build.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 6c6c58ed1ac0..fb04cc5a56b2 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,5 +1,6 @@ obj-y +=3D aplic.o obj-y +=3D cpufeature.o +obj-y +=3D dom0less-build.o obj-y +=3D domain.o obj-y +=3D domain-build.o obj-$(CONFIG_EARLY_PRINTK) +=3D early_printk.o diff --git a/xen/arch/riscv/dom0less-build.c b/xen/arch/riscv/dom0less-buil= d.c new file mode 100644 index 000000000000..10863cffc96b --- /dev/null +++ b/xen/arch/riscv/dom0less-build.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +int __init make_arch_nodes(struct kernel_info *kinfo) +{ + /* No RISC-V specific nodes need to be made, at the moment. */ + + return 0; +} --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773162589; cv=none; d=zohomail.com; s=zohoarc; b=j7Ss1yYdrnJ/ZIkBVzrXElS3zlq/9szLO6zX+3mvBKBs3UxE9ECTiwLt/pQrjJgeBfon0kECvlZKGbMT+3mhW+E4o5X00+EHVSbIJKf8whwN4JZCS8PkWLKUMfpng1zAPOJ9qdOW1RGhhtIwXKvFnlWg98Ef6GkdZOcr7REamIU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773162589; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/l+2sfUlHi+3W7tldQuhyj7te+foi9fBjieEM15WHyQ=; b=oF34Rt78r0uUXfYM4DjQllTynLpJhNL01HdzC8xACZKYx4cgYM01Ga3msYo5ZToYkySIUXy7s3MRw3mlQR8S7QXkC9af1Qz7JITu3aSNJFgIRrVIcKmqiLpqcxf2fsTV5kF3VlxktFFaV/Pirgt7vo0L0k42kspx+R99z32uLdk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773162589677704.5998466160605; Tue, 10 Mar 2026 10:09:49 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250392.1547915 (Exim 4.92) (envelope-from ) id 1w00aA-00039u-Qn; Tue, 10 Mar 2026 17:09:22 +0000 Received: by outflank-mailman (output) from mailman id 1250392.1547915; Tue, 10 Mar 2026 17:09:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00aA-00038q-J7; Tue, 10 Mar 2026 17:09:22 +0000 Received: by outflank-mailman (input) for mailman id 1250392; Tue, 10 Mar 2026 17:09:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00a9-0001Q4-Gb for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:21 +0000 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [2a00:1450:4864:20::32d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e11448e7-1ca3-11f1-b164-2bf370ae4941; Tue, 10 Mar 2026 18:09:20 +0100 (CET) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-485392de558so15013885e9.1 for ; Tue, 10 Mar 2026 10:09:20 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:19 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e11448e7-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162560; x=1773767360; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/l+2sfUlHi+3W7tldQuhyj7te+foi9fBjieEM15WHyQ=; b=ZAK36sIlsfOk4hW9Bb7BChtrCIV28Sid3O9vbFB3gC2iVx0qWb4/GSNl2bKt0eRBAq WT47fAnrqMH3QdgU3oMD9LVUPDJAx39Z4nV2R5xe2HqbLW6+2g5Gl4fWGHtxYIAmYtFG grN3QsJ3opTlj7q36I+/NVNyF/vaR95dpMoIbgF/tmc3QsQ47hM5KSAwB0MJVUC+tTWm bbOmaevwCoZQD+RT95OzP8Ccqk4KHVbgQO4PCbfXHZfRPCPWZTJnPCVDiPZPGLfg4pqU XXKzS1tPIhHN6anLHFRhd/HMhsyH3w590akpfFIWeBomVc9FJ3gKGN/L5h9AyjyGRXN+ SUWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162560; x=1773767360; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/l+2sfUlHi+3W7tldQuhyj7te+foi9fBjieEM15WHyQ=; b=XKrojN2ypzF0CG/eTPhVLlAMXbivQV0F8uKHcVzHTvZgUT0nbkuG1Y0gQ/G8t3+t0E VT+LaVGSgnGxNLW01iABuo7CIKD3bFkWSOm1y1PRv9uohe+rn8qQ8MXcvcChQSU0UaWS depDiXgqqc86H0o8RpCLWy/ADwvQ0CKyz8Z6hdxkS4b2gZ2uBPNCyTdrp/Swd60lAexv uVuvf1pz1k6cGbXalTSZyAAjfsKrbrd4M0QQTMqP98i1WtV5GGmORyfoMq2z2uR4XiZ/ LiHRTR75m0FSfXB6k1ehiZvvRAoZY1n54H8KUmowczoF9rIONma2+uZvgtmj0f6ckBZh wBbA== X-Gm-Message-State: AOJu0YzTnMQDZVUdZWLK0ma9ROSNvBFt6tDjsrulScKtgDepbuwjllfm cQjNrg6m52mWXMmlv8axx/tJoXUY3o97aB5e/sDcz9KsEYrOcjFGVtnMxQbtxkUP X-Gm-Gg: ATEYQzyJ/l2cTlL3dlpl/2BuKkuDIU0UUrG8TA0Gkx7cV0CoAWAxra9UqROpoa6NbnY kk5WeRG5UOsxULuEjJfULUzyVD1RMoSe0bj0mkbvVsWQjZ7Q3j2yR2nDamdYkRRCNfziyUe+uNm IjqZRp0vkddZXdszNG90SBPt3Ns7BfajrTaBbgq13+pzPdw6dkHQh6y14xEqDPQocleaIPfF0sL k9kGf/cm9nmcPsgaPMT+1ZP/VVb5hHg7DaOVwjCp1h0x4fO4aN2v5HpRQJqgtTx1BqwN4A6oSlN ioKESIzbXEcyOrJpjgLPUrXE1bWmILUtqu3a561diqKpzWqKtFj06q7jFoaZZ4i2fkh96QGa7cy QERmB+gZrPGILQ71/IEc2D6zBAXzBGfvdm34U9Fzsd4pBbOyfO48zpoN0NYLdBjXZS8uGo7p3Ug C1cNCxbxeaR2GEcDE2mImWFphpEpjF7qpJpFUT4t78UiGKayoM1tPGB4z3gpHWpT7K2ac7OA== X-Received: by 2002:a05:600c:1f0f:b0:483:703e:4ad5 with SMTP id 5b1f17b1804b1-48526967cd9mr255015965e9.22.1773162559897; Tue, 10 Mar 2026 10:09:19 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 09/27] xen/riscv: implement make_intc_domU_node() Date: Tue, 10 Mar 2026 18:08:42 +0100 Message-ID: <7a7f1430090eaf50cc3bff25e894c13404bffad5.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162590464158500 Content-Type: text/plain; charset="utf-8" Introduce a RISC-V specific function to create an interrupt controller Device Tree node for DomU domains during dom0less build. Add make_intc_domU_node() to the dom0less build path and wire it to a new generic helper, intc_make_domu_dt_node(), which delegates DT node creation to the active interrupt controller implementation via intc_hw_ops. Extend struct intc_hw_operations with a make_dom_dt_node callback and expose the required interfaces in the interrupt controller header, allowing individual interrupt controller drivers to populate DomU DT nodes as needed. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/dom0less-build.c | 9 +++++++++ xen/arch/riscv/include/asm/intc.h | 10 ++++++++-- xen/arch/riscv/intc.c | 8 ++++++++ 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/xen/arch/riscv/dom0less-build.c b/xen/arch/riscv/dom0less-buil= d.c index 10863cffc96b..312c5d7d4979 100644 --- a/xen/arch/riscv/dom0less-build.c +++ b/xen/arch/riscv/dom0less-build.c @@ -3,6 +3,15 @@ #include #include =20 +#include + +int __init make_intc_domU_node(struct kernel_info *kinfo) +{ + intc_make_domu_dt_node(kinfo); + + return 0; +} + int __init make_arch_nodes(struct kernel_info *kinfo) { /* No RISC-V specific nodes need to be made, at the moment. */ diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index ecdc8a5e6577..8300d71d472f 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -8,14 +8,14 @@ #ifndef ASM__RISCV__INTERRUPT_CONTOLLER_H #define ASM__RISCV__INTERRUPT_CONTOLLER_H =20 -struct dt_device_node; - enum intc_version { INTC_APLIC, }; =20 struct cpu_user_regs; +struct dt_device_node; struct irq_desc; +struct kernel_info; =20 struct intc_info { enum intc_version hw_version; @@ -41,6 +41,10 @@ struct intc_hw_operations { =20 /* handle external interrupt */ void (*handle_interrupt)(struct cpu_user_regs *regs); + + /* Create interrupt controller node for domain */ + int (*make_dom_dt_node)(const struct kernel_info *kinfo, + const struct dt_device_node *intc); }; =20 void intc_preinit(void); @@ -53,4 +57,6 @@ void intc_route_irq_to_xen(struct irq_desc *desc, unsigne= d int priority); =20 void intc_handle_external_irqs(struct cpu_user_regs *regs); =20 +int intc_make_domu_dt_node(const struct kernel_info *kinfo); + #endif /* ASM__RISCV__INTERRUPT_CONTOLLER_H */ diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c index ea317aea5ad8..a6f8c30f4771 100644 --- a/xen/arch/riscv/intc.c +++ b/xen/arch/riscv/intc.c @@ -67,3 +67,11 @@ void intc_route_irq_to_xen(struct irq_desc *desc, unsign= ed int priority) intc_set_irq_type(desc, desc->arch.type); intc_set_irq_priority(desc, priority); } + +int __init intc_make_domu_dt_node(const struct kernel_info *kinfo) +{ + if ( intc_hw_ops && intc_hw_ops->make_dom_dt_node ) + return intc_hw_ops->make_dom_dt_node(kinfo, intc_hw_ops->info->nod= e); + + return -ENOSYS; +} --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773162583; cv=none; d=zohomail.com; s=zohoarc; b=RQGbL6wAJ5dgUWM5Kve8Jhc3gLih5ojwfIDWvA5Vd32AIQGqo/DSKRhwaDAflU11zHDf9SsCYHI2pvRMhkU7i1tp+LyKsbPVgnIleP/leGVb/NURjzNcx9z9ny+vk59OOSCgcq4FwEYXMuke3DjzFXDeeYov6+La5xdTyLhwCI0= ARC-Message-Signature: i=1; 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Add support for generating an IMSIC node when building the guest DT. Keep a reference to the host IMSIC DT node and reuse its compatible property while constructing the guest-visible node. The generated node contains guest-specific information such as the MMIO region sized for the number of vCPUs and the interrupts-extended property referencing per-vCPU interrupt controllers. This allows guests to discover and use the IMSIC interrupt controller. Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/imsic.c | 113 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/imsic.h | 7 ++ 2 files changed, 120 insertions(+) diff --git a/xen/arch/riscv/imsic.c b/xen/arch/riscv/imsic.c index a4460576f620..0956b187705f 100644 --- a/xen/arch/riscv/imsic.c +++ b/xen/arch/riscv/imsic.c @@ -13,8 +13,11 @@ #include #include #include +#include #include +#include #include +#include #include #include #include @@ -329,6 +332,8 @@ int __init imsic_init(const struct dt_device_node *node) struct imsic_mmios *mmios; struct imsic_msi *msi =3D NULL; =20 + imsic_cfg.host_node =3D node; + /* Parse IMSIC node */ rc =3D imsic_parse_node(node, &nr_parent_irqs, &nr_mmios); /* @@ -487,3 +492,111 @@ int __init imsic_init(const struct dt_device_node *no= de) =20 return rc; } + +static int __init imsic_make_reg_property(struct domain *d, void *fdt) +{ + __be32 regs[4]; + + regs[0] =3D cpu_to_be32(imsic_cfg.base_addr >> 32); + regs[1] =3D cpu_to_be32(imsic_cfg.base_addr); + regs[2] =3D cpu_to_be32((IMSIC_MMIO_PAGE_SZ * d->max_vcpus) >> 32); + regs[3] =3D cpu_to_be32(IMSIC_MMIO_PAGE_SZ * d->max_vcpus); + + return fdt_property(fdt, "reg", regs, sizeof(regs)); +} + +static int __init imsic_set_interrupt_extended_prop(struct domain *d, + void *fdt) +{ + uint32_t len =3D 0, pos =3D 0, cpu, phandle; + uint32_t *irq_ext; + char buf[64]; + int res; + + irq_ext =3D xvzalloc_array(uint32_t, d->max_vcpus * 2); + if ( !irq_ext ) + return -ENOMEM; + + for ( cpu =3D 0; cpu < d->max_vcpus; cpu++ ) + { + snprintf(buf, sizeof(buf), "/cpus/cpu@%u/interrupt-controller", cp= u); + phandle =3D fdt_get_phandle(fdt, fdt_path_offset(fdt, buf)); + + if ( phandle <=3D 0 ) + return phandle; + + irq_ext[pos++] =3D cpu_to_be32(phandle); + len +=3D sizeof(uint32_t); + irq_ext[pos++] =3D cpu_to_be32(IRQ_S_EXT); + len +=3D sizeof(uint32_t); + } + + res =3D fdt_property(fdt, "interrupts-extended", irq_ext, len); + + XVFREE(irq_ext); + + return res; +} + +int __init imsic_make_dt_node(const struct kernel_info *kinfo) +{ + uint32_t len; + const void *data =3D NULL; + int res =3D 0; + void *fdt =3D kinfo->fdt; + const struct dt_device_node *host_imsic_node =3D imsic_cfg.host_node; + uint32_t *next_phandle =3D &kinfo->bd.d->arch.next_phandle; + + res =3D fdt_begin_node(fdt, host_imsic_node->full_name); + if ( res ) + return res; + + data =3D dt_get_property(host_imsic_node, "compatible", &len); + if ( !data ) + { + printk(XENLOG_ERR "%s: Can't find 'compatible' property\n", + host_imsic_node->full_name); + + return -ENOENT; + } + + res =3D fdt_property(fdt, "compatible", data, len); + if ( res ) + return res; + + res =3D imsic_make_reg_property(kinfo->bd.d, fdt); + if ( res ) + return res; + + res =3D imsic_set_interrupt_extended_prop(kinfo->bd.d, fdt); + if ( res ) + return res; + + res =3D fdt_property_u32(fdt, "riscv,num-ids", imsic_cfg.nr_ids); + if ( res ) + return res; + + res =3D fdt_property(fdt, "msi-controller", NULL, 0); + if ( res ) + return res; + + res =3D fdt_property_u32(fdt, "#msi-cells", 0); + if ( res ) + return res; + + res =3D fdt_property(fdt, "interrupt-controller", NULL, 0); + if ( res ) + return res; + + res =3D fdt_property_u32(fdt, "#interrupt-cells", 0); + if ( res ) + return res; + + imsic_cfg.phandle =3D (*next_phandle)++; + + res =3D fdt_property_cell(fdt, "phandle", imsic_cfg.phandle); + if ( res ) + return res; + + return fdt_end_node(fdt); +} diff --git a/xen/arch/riscv/include/asm/imsic.h b/xen/arch/riscv/include/as= m/imsic.h index c6c59215df20..a63d56fbd5d9 100644 --- a/xen/arch/riscv/include/asm/imsic.h +++ b/xen/arch/riscv/include/asm/imsic.h @@ -57,11 +57,16 @@ struct imsic_config { /* MSI */ const struct imsic_msi *msi; =20 + /* DT node of IMSIC */ + const struct dt_device_node *host_node; + /* Lock to protect access to IMSIC's stuff */ spinlock_t lock; }; =20 struct dt_device_node; +struct kernel_info; + int imsic_init(const struct dt_device_node *node); =20 const struct imsic_config *imsic_get_config(void); @@ -71,4 +76,6 @@ void imsic_irq_disable(unsigned int hwirq); =20 void imsic_ids_local_delivery(bool enable); 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Add support for creating an APLIC node when building the guest DT. The node is derived from the host DT and linked to the guest IMSIC via the msi-parent property, allowing guests to discover and use the APLIC interrupt controller. Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/aplic.c | 82 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/xen/arch/riscv/aplic.c b/xen/arch/riscv/aplic.c index 739e8dab3498..e139946a05a0 100644 --- a/xen/arch/riscv/aplic.c +++ b/xen/arch/riscv/aplic.c @@ -12,8 +12,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -295,6 +297,85 @@ static void cf_check aplic_set_irq_type(struct irq_des= c *desc, spin_unlock(&aplic.lock); } =20 +static int __init cf_check aplic_make_dom_dt_node( + const struct kernel_info *kinfo, + const struct dt_device_node *aplic_nod= e) +{ + uint32_t len; + const __be32 *regs; + const void *data =3D NULL; + int res =3D 0; + void *fdt =3D kinfo->fdt; + + res =3D imsic_make_dt_node(kinfo); + if ( res ) + return res; + + res =3D fdt_begin_node(fdt, aplic_node->full_name); + if (res) + return res; + + data =3D dt_get_property(aplic_node, "#interrupt-cells", &len); + if ( !data ) + { + printk("%s: Can't find '#interrupt-cells' property\n", + aplic_node->full_name); + return -FDT_ERR_XEN(ENOENT); + } + + res =3D fdt_property(fdt, "#interrupt-cells", data, len); + if ( res ) + return res; + + regs =3D dt_get_property(aplic_node, "reg", &len); + if ( !regs ) + { + printk("%s: Can't find 'reg' property\n", aplic_node->full_name); + return -FDT_ERR_XEN(ENOENT); + } + + res =3D fdt_property(fdt, "reg", regs, len); + if ( res ) + return res; + + data =3D dt_get_property(aplic_node, "riscv,num-sources", &len); + if ( !data ) + { + printk("%s: Can't find 'riscv,num-sources' property\n", + aplic_node->full_name); + return -FDT_ERR_XEN(ENOENT); + } + + res =3D fdt_property(fdt, "riscv,num-sources", data, len); + if ( res ) + return res; + + res =3D fdt_property(fdt, "interrupt-controller", NULL, 0); + if ( res ) + return res; + + data =3D dt_get_property(aplic_node, "compatible", &len); + if ( !data ) + { + printk("%s: Can't find 'compatible' property\n", aplic_node->full_= name); + return -FDT_ERR_XEN(ENOENT); + } + + res =3D fdt_property(fdt, "compatible", data, len); + if ( res ) + return res; + + res =3D fdt_property_cell(fdt, "msi-parent", aplic.imsic_cfg->phandle); + if ( res ) + return res; + + res =3D fdt_property_cell(fdt, "phandle", kinfo->phandle_intc); + if ( res ) + return res; + + return fdt_end_node(fdt); +} + static const hw_irq_controller aplic_xen_irq_type =3D { .typename =3D "aplic", .startup =3D aplic_irq_startup, @@ -310,6 +391,7 @@ static const struct intc_hw_operations aplic_ops =3D { .host_irq_type =3D &aplic_xen_irq_type, .handle_interrupt =3D aplic_handle_interrupt, .set_irq_type =3D aplic_set_irq_type, + .make_dom_dt_node =3D aplic_make_dom_dt_node, }; =20 static int cf_check aplic_irq_xlate(const uint32_t *intspec, --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:23 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e34d6159-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162564; x=1773767364; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wxAqjKoB8nUBBhDPx/zv6ewxjJzbCrTIbqMHHIHK+cg=; b=Ehou3/FICijR4b2STcMbbQHoyIuCgt5IClHYUlmXUtuc9ZWkk89Vi1gHiNRVMHACRF UPuNFuy3xWozX6NR7JRspEGGh2YTrLHRpVvwiKJKclNN4nJrcdkMrND6dq5PyuILsmBu 6clqBW7+ZiETMV4HM22coVwOM5OcwuJWGZTbXgg2/D4aZM702KuvEV1gdcOvJS6KyGqk SdpSECJz7g45Ck8GRaBruPjkMTr4zeWt9MnE6lh/MO9Q73Xx3c2PJl9S1ZiUWDwr9IA7 x3d+NFy9QTwEWBcNZsPECFkTVO5pNQDMHrMowvq8i2PT2WHW/8z0Lnyos1Fbp4SGy1Et WZuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162564; x=1773767364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wxAqjKoB8nUBBhDPx/zv6ewxjJzbCrTIbqMHHIHK+cg=; b=P+IJwQT7h+GDoAwzZwXtUtLRuqpp2Dvnyd0NC7pcJCysPskiG/OUvHQQoeoWrz6jwf swzXtPSTPAo/5ZBsAechG+Ib10c8QbABYVTuGOsi8IYyhFrpDwmOcMv/yjdzWLCMZ4DW iSo5Xjy2AQFrJHMiTLVNkG6GN5gte3lirVp1lgUDlCvdqKGVN3aPFqHm9S+9Epe2mZYG scR/6qcDb7xeV+jXPxvY55PmxLHfIdE4ZldgqDdm+GGgxvMC40EvZ98WGbbnokHjYkcD iQmq7Y19DN9mV//6NvQ0+GJPNn2oLCP27/X7/nexalP9wTmiF4v+ADQtHr7XpWIV8rX5 cBfA== X-Gm-Message-State: AOJu0Yz9QAfMqrm3EvGSHHg1Wvoz31yBcokwTGf4LYAD9OiTcnJ6fqK6 sQpHRRAYCVFGqOSyAfXQRrAKbPusrp5Lf3fptuYaMxwuP6gs6B8lB4HBZSEpRaLf X-Gm-Gg: ATEYQzytiRDAs2892gWiPFygQzTVqkEm4aWuxcSScA44nKakzJyeK2l7N5LDayETNHg 79sKKdUH9oytk/+RvZTELIv8md1o/eV+c3t3usDE1Bw68pj9/rnZa8C39sFB2B08cNMXYQ1GE6d j8uJkFjPl+z6cH6bjiZyE0em80O+rekQxLSkUB9G6PIweeCPDD+C8pn5KMZT5dRBj6Xo2PralwW wG2DHkRLygk7LuTj4OK0NHOy1v74FUGyPK2lRhrgIs9Vt5UjgxcvhOR5Vy01B8p+TFGxPEf6kxs 7ILSdpVUOXBXkMEFUChPrcJxp1N/JIipuXTNWBBY6CxwECUwp48thNmhF//5Wv3T4sRcF669aN8 oIzByQRhGNDpaHmSKPU5Y7K+30t/T3eKJoFBcFhf7YFD34/zoBvEEAblVArBhxaCJnhHDAAwnlK xxTGdcNQure+zEqTFMSNNFjO4GM64P9rnPdBeVkVXJh5SZAhjNRjpE7vWIjAr2nIIw24hWpQ== X-Received: by 2002:a05:600c:4fc3:b0:485:3692:e906 with SMTP id 5b1f17b1804b1-4853692eacemr162644025e9.13.1773162563586; Tue, 10 Mar 2026 10:09:23 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 12/27] xen/riscv: introduce aia_init() and aia_available() Date: Tue, 10 Mar 2026 18:08:45 +0100 Message-ID: <74f15b1db86139b36b721ef9d12b998fe4f0f348.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162588414158500 Content-Type: text/plain; charset="utf-8" aia_init() is going to contain all the stuff related to AIA initialization. At the moment, it is just Check if SSAIA extension is available and if yes set is_aia_available to true. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/aia.c | 25 +++++++++++++++++++++++++ xen/arch/riscv/include/asm/aia.h | 10 ++++++++++ xen/arch/riscv/intc.c | 3 +++ 4 files changed, 39 insertions(+) create mode 100644 xen/arch/riscv/aia.c create mode 100644 xen/arch/riscv/include/asm/aia.h diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index fb04cc5a56b2..d772b42386c0 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,3 +1,4 @@ +obj-y +=3D aia.o obj-y +=3D aplic.o obj-y +=3D cpufeature.o obj-y +=3D dom0less-build.o diff --git a/xen/arch/riscv/aia.c b/xen/arch/riscv/aia.c new file mode 100644 index 000000000000..5e3f190e8e2c --- /dev/null +++ b/xen/arch/riscv/aia.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include + +static bool __ro_after_init is_aia_available; + +bool aia_available(void) +{ + return is_aia_available; +} + +int __init aia_init(void) +{ + if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) + return -ENODEV; + + is_aia_available =3D true; + + return 0; +} diff --git a/xen/arch/riscv/include/asm/aia.h b/xen/arch/riscv/include/asm/= aia.h new file mode 100644 index 000000000000..039607faf685 --- /dev/null +++ b/xen/arch/riscv/include/asm/aia.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ASM__RISCV__AIA_H +#define ASM__RISCV__AIA_H + +bool aia_available(void); + +int aia_init(void); + +#endif /* ASM__RISCV__ACPI_H */ diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c index a6f8c30f4771..c9f12651fda1 100644 --- a/xen/arch/riscv/intc.c +++ b/xen/arch/riscv/intc.c @@ -8,6 +8,7 @@ #include #include =20 +#include #include =20 static const struct intc_hw_operations *__ro_after_init intc_hw_ops; @@ -27,6 +28,8 @@ void __init intc_preinit(void) =20 void __init intc_init(void) { + aia_init(); + if ( intc_hw_ops->init() ) panic("Failed to initialize the interrupt controller drivers\n"); } --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:24 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e415608c-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162565; x=1773767365; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0nBjOwOkgmV3ao9VaFguk8mStyy/ASZb20xOrZJU8TM=; b=QvpJqg/cMsyPNKSuJbij6IINo/Kl94JU5kX2IhQPKpO7cshbYtN5OdAQO4lmMn+OXf GaBaD9zT+46iZ8gQxAJ2MUeeE3+GcAqyRY50ZK1HauL2jCPIuZnsBbm+CHCKIJCRwgVs I+7WygMG+89wXoEC02keUhO9DuzpvA3+7VSsHUDFUQVoQKF9rz0A9ETPTP/QYudI/4JZ tRqIJtxIfDxhwYbF5r1x5soRo0Y96sBr3roACC/XmBAA0gXw7fj/lpQbC+VW8+9+V7Dq 8kX0tKl7za/w8HqGHwKuSFtOHvcCMLxbRt4ydPAkrZ45ImS0n639yIoIfoXs+4v4XwYe 0hcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162565; x=1773767365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0nBjOwOkgmV3ao9VaFguk8mStyy/ASZb20xOrZJU8TM=; b=JQzc6+NZU4eU2Tdmgdo668Os1n9nhJ8H2IW2YG6G2+q/rQNcEc9PkgvX98ZB/9HAbU G9crJsRS6/BuHCQyrr+T0135QuPwxstmzcw5vHg6f/5RpdZYAN34dTfo5O6ZgPaLXBPH B2vwSRxjzuXJ3pENAruZAN5rNj02RDuBE3XxCsYjjx1TLAzdpoUQ+7MumTw4rpqlzDV8 e4VdeFUM4ec1db6W2ejQ33F46krlJUHYH4V4NgFkfk7tbpJVQldr/ao+pUPFSL9NG3Kx TwRzswFQJ15HdwRfUF5SjAoedImNsfE+W/LQj1/TH7gjP39yGo4zXzlr7lpaQ0Odx5Pq rNOw== X-Gm-Message-State: AOJu0YwVwg1PrEcoll3jkzhlXYh5w5DfP2Wcm/5hKpQvQX2FtmyPBhWI RFyzD7h8c7mhI8XbmMIsN6nyDNurx/95QI5AxAU2yi24rLHtyTAE54eDwf2ddFrA X-Gm-Gg: ATEYQzx3RWRxtzB2wofTcjnq0zqD3TcB9O6kKIE/ZTcGScoduZnQA1dBZf+PO07U1oN Egrs9QcAuHxF3pfufIejb6PDWyF3xCuJyEKWxXSz/YPyFo7HMUSHtsnrcACj05VEFQNRTc4Lk5k HJhP+UKGZmXSFkDbFcknyHZgCyS/y1t342l4A0PexlVpJWO1Ubpe5Hfv6Y/QqJ9LE29M8No+uXW Zwsw61M8fX116cxxLG/dovb/XqKmplZfxJEK188TcoXGOhN157cajq5/9g/sekgeVCwjo35c3eP TLjLQPmDozrFGnLRkxb89LcJPBjqZ0iu6esDXlDHMRk6aM90kMUGsAzhaSV66+bbvxEEIjad3DO iq+ZxLeKHbcMhD07mhpPlzuL7Oc2KlP3w/yEcLHunkUR9NRHMKTBXW5dscyCanDQSOklFIPJD3N 224pcQ/GEK01tiv4sYHxuy7MHNdLxRNKBzGeaI2VEAN+hxnqkaK9hLCXX9WcSvMczAX28Z+pSbA Xtb X-Received: by 2002:a05:600c:4ed1:b0:485:3a03:ced1 with SMTP id 5b1f17b1804b1-4853a03d7eamr152562415e9.28.1773162564912; Tue, 10 Mar 2026 10:09:24 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 13/27] xen/riscv: add basic VGEIN management for AIA guests Date: Tue, 10 Mar 2026 18:08:46 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162594537158500 Content-Type: text/plain; charset="utf-8" AIA provides a hardware-accelerated mechanism for delivering external interrupts to domains via "guest interrupt files" located in IMSIC. A single physical hart can implement multiple such files (up to GEILEN), allowing several virtual harts to receive interrupts directly from hardware Introduce per-CPU tracking of guest interrupt file identifiers (VGEIN) for systems implementing AIA specification. Each CPU maintains a bitmap describing which guest interrupt files are currently in use. Add helpers to initialize the bitmap based on the number of available guest interrupt files (GEILEN), assign a VGEIN to a vCPU, and release it when no longer needed. When assigning a VGEIN, the corresponding value is written to the VGEIN field of the guest hstatus register so that VS-level external interrupts are delivered from the selected interrupt file. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/aia.c | 112 ++++++++++++++++++++++++++++++- xen/arch/riscv/include/asm/aia.h | 18 +++++ 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/aia.c b/xen/arch/riscv/aia.c index 5e3f190e8e2c..7bd66d1e37c6 100644 --- a/xen/arch/riscv/aia.c +++ b/xen/arch/riscv/aia.c @@ -1,11 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include +#include +#include #include +#include =20 +#include #include +#include +#include + +/* + * Bitmap for each physical cpus to detect which VS (guest) + * interrupt file id was used. + */ +DEFINE_PER_CPU(struct vgein_bmp, vgein_bmp); =20 static bool __ro_after_init is_aia_available; =20 @@ -14,12 +27,109 @@ bool aia_available(void) return is_aia_available; } =20 +int __init vgein_init(unsigned int cpu) +{ + struct vgein_bmp *vgein =3D &per_cpu(vgein_bmp, cpu); + + csr_write(CSR_HGEIE, -1UL); + vgein->geilen =3D flsl(csr_read(CSR_HGEIE)); + csr_write(CSR_HGEIE, 0); + if ( vgein->geilen ) + vgein->geilen--; + + BUG_ON(!vgein->geilen); + + printk("cpu%d.geilen=3D%d\n", cpu, vgein->geilen); + + if ( !vgein->bmp ) + { + vgein->bmp =3D xvzalloc_array(unsigned long, BITS_TO_LONGS(vgein->= geilen)); + if ( !vgein->bmp ) + return -ENOMEM; + } + + spin_lock_init(&vgein->lock); + + return 0; +} + int __init aia_init(void) { + int rc =3D 0; + if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) return -ENODEV; =20 + if ( (rc =3D vgein_init(0)) ) + return rc; + is_aia_available =3D true; =20 - return 0; + return rc; +} + +unsigned int vgein_assign(struct vcpu *v) +{ + unsigned int vgein_id; + + struct vgein_bmp *vgein_bmp =3D &per_cpu(vgein_bmp, v->processor); + unsigned long *bmp =3D vgein_bmp->bmp; + unsigned long flags; + + spin_lock_irqsave(&vgein_bmp->lock, flags); + vgein_id =3D bitmap_weight(bmp, vgein_bmp->geilen); + + /* + * All vCPU guest interrupt files are used and we don't support a case + * when number of vCPU on 1 pCPU is bigger then geilen. + */ + ASSERT(vgein_id < vgein_bmp->geilen); + + bitmap_set(bmp, vgein_id, 1); + spin_unlock_irqrestore(&vgein_bmp->lock, flags); + + /* + * The vgein_id shouldn't be zero, as it will indicate that no guest + * external interrupt source is selected for VS-level external interru= pts + * according to RISC-V priviliged spec: + * 8.2.1 Hypervisor Status Register (hstatus) in RISC-V priviliged s= pec: + * + * The VGEIN (Virtual Guest External Interrupt Number) field selects + * a guest external interrupt source for VS-level external interrupt= s. + * VGEIN is a WLRL field that must be able to hold values between ze= ro + * and the maximum guest external interrupt number (known as GEILEN), + * inclusive. + * When VGEIN=3D0, no guest external interrupt source is selected for + * VS-level external interrupts. + */ + vgein_id++; + +#ifdef VGEIN_DEBUG + printk("%s: %pv: vgein_id(%u), xen_cpu%d_bmp=3D%#lx\n", + __func__, v, vgein_id, v->processor, *bmp); +#endif + + vcpu_guest_cpu_user_regs(v)->hstatus &=3D ~HSTATUS_VGEIN; + vcpu_guest_cpu_user_regs(v)->hstatus |=3D + MASK_INSR(vgein_id, HSTATUS_VGEIN); + + return vgein_id; +} + +void vgein_release(struct vcpu *v, unsigned int vgen_id) +{ + unsigned long flags; + + struct vgein_bmp *vgein_bmp =3D &per_cpu(vgein_bmp, v->processor); + + spin_lock_irqsave(&vgein_bmp->lock, flags); + bitmap_clear(vgein_bmp->bmp, vgen_id - 1, 1); + spin_unlock_irqrestore(&vgein_bmp->lock, flags); + +#ifdef VGEIN_DEBUG + printk("%s: vgein_id(%u), xen_cpu%d_bmp=3D%#lx\n", + __func__, vgen_id, v->processor, *vgein_bmp->bmp); +#endif + + vcpu_guest_cpu_user_regs(v)->hstatus &=3D ~HSTATUS_VGEIN; } diff --git a/xen/arch/riscv/include/asm/aia.h b/xen/arch/riscv/include/asm/= aia.h index 039607faf685..c2717504cbea 100644 --- a/xen/arch/riscv/include/asm/aia.h +++ b/xen/arch/riscv/include/asm/aia.h @@ -3,8 +3,26 @@ #ifndef ASM__RISCV__AIA_H #define ASM__RISCV__AIA_H =20 +#include +#include + +struct vcpu; + +struct vgein_bmp { + unsigned long *bmp; + spinlock_t lock; + struct vcpu *owners[BITS_PER_LONG]; + unsigned int geilen; +}; + +DECLARE_PER_CPU(struct vgein_bmp, vgein_bmp); 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Introduce a per-vCPU structure to hold IMSIC-related state, including the guest interrupt file identifier and the CPU providing the backing VS-file. Access to the guest file identifier is protected by a lock. Initialize this structure during vCPU setup and store it in arch_vcpu. The initial state marks the VS-file as software-backed until it becomes associated with a physical CPU. Add helpers to retrieve and update the guest interrupt file identifier. Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/imsic.c | 42 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 2 ++ xen/arch/riscv/include/asm/imsic.h | 17 ++++++++++++ 3 files changed, 61 insertions(+) diff --git a/xen/arch/riscv/imsic.c b/xen/arch/riscv/imsic.c index 0956b187705f..bbadbdf352a1 100644 --- a/xen/arch/riscv/imsic.c +++ b/xen/arch/riscv/imsic.c @@ -59,6 +59,29 @@ do { \ csr_clear(CSR_SIREG, v); \ } while (0) =20 +unsigned int vcpu_guest_file_id(const struct vcpu *v) +{ + struct imsic_state *imsic_state =3D v->arch.imsic_state; + unsigned long flags; + unsigned int vsfile_id; + + read_lock_irqsave(&imsic_state->vsfile_lock, flags); + vsfile_id =3D imsic_state->guest_file_id; + read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); + + return vsfile_id; +} + +void imsic_set_guest_file_id(const struct vcpu *v, unsigned int guest_file= _id) +{ + struct imsic_state *imsic_state =3D v->arch.imsic_state; + unsigned long flags; + + write_lock_irqsave(&imsic_state->vsfile_lock, flags); + imsic_state->guest_file_id =3D guest_file_id; + write_unlock_irqrestore(&imsic_state->vsfile_lock, flags); +} + void __init imsic_ids_local_delivery(bool enable) { if ( enable ) @@ -315,6 +338,25 @@ static int imsic_parse_node(const struct dt_device_nod= e *node, return 0; } =20 +int __init vcpu_imsic_init(struct vcpu *v) +{ + struct imsic_state *imsic_state; + + /* Allocate IMSIC context */ + imsic_state =3D xvzalloc(struct imsic_state); + if ( !imsic_state ) + return -ENOMEM; + + v->arch.imsic_state =3D imsic_state; + + /* Setup IMSIC context */ + rwlock_init(&imsic_state->vsfile_lock); + + imsic_state->guest_file_id =3D imsic_state->vsfile_pcpu =3D NR_CPUS; + + return 0; +} + /* * Initialize the imsic_cfg structure based on the IMSIC DT node. * diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 506365f199c7..bdb1ffd748c9 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -52,6 +52,8 @@ struct arch_vcpu { =20 struct vtimer vtimer; =20 + struct imsic_state *imsic_state; + register_t hcounteren; register_t hedeleg; register_t hideleg; diff --git a/xen/arch/riscv/include/asm/imsic.h b/xen/arch/riscv/include/as= m/imsic.h index a63d56fbd5d9..13a563dce066 100644 --- a/xen/arch/riscv/include/asm/imsic.h +++ b/xen/arch/riscv/include/asm/imsic.h @@ -11,6 +11,7 @@ #ifndef ASM_RISCV_IMSIC_H #define ASM_RISCV_IMSIC_H =20 +#include #include #include #include @@ -64,8 +65,20 @@ struct imsic_config { spinlock_t lock; }; =20 +struct imsic_state { + /* IMSIC VS-file */ + rwlock_t vsfile_lock; + unsigned int guest_file_id; + /* + * (vsfile_pcpu >=3D 0) =3D> h/w IMSIC VS-file + * (vsfile_pcpu =3D=3D NR_CPUS) =3D> s/w IMSIC SW-file + */ + unsigned long vsfile_pcpu; +}; + struct dt_device_node; struct kernel_info; +struct vcpu; =20 int imsic_init(const struct dt_device_node *node); =20 @@ -78,4 +91,8 @@ void imsic_ids_local_delivery(bool enable); =20 int imsic_make_dt_node(const struct kernel_info *kinfo); =20 +int vcpu_imsic_init(struct vcpu *v); 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Initialize vAPLIC's domaincfg to with the interrupt-enable bit set and MSI delivery mode selected as the current solution is exepcted to have always IMSIC, and initialize vintc->ops. Other operations such as emulate_load(), emulate_store(), and is_access() will be needed once guests are running and MMIO accesses to APLIC MMIO range must be handled. These will be introduced separately later. Introduce a structure to describe a virtual interrupt controller (vINTC) and a vintc_ops structure, which provides operations to emulate load and store accesses to interrupt controller MMIOs and to check whether a given address falls within the MMIO range of a specific virtual interrupt controller. The vAPLIC implementation of these operations will be provided later once guests can be run and these operations are actually needed. Introduce these structures here as they are required for the implementation of domain_vaplic_init() and domain_vaplic_alloc(). Also, introduce vcpu_vaplic_init() and init vintc_ops->vcpu_init() with it. Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 11 ++--- xen/arch/riscv/include/asm/domain.h | 2 + xen/arch/riscv/include/asm/intc.h | 14 ++++++ xen/arch/riscv/include/asm/vaplic.h | 36 ++++++++++++++ xen/arch/riscv/intc.c | 1 + xen/arch/riscv/vaplic.c | 74 +++++++++++++++++++++++++++++ 7 files changed, 131 insertions(+), 8 deletions(-) create mode 100644 xen/arch/riscv/include/asm/vaplic.h create mode 100644 xen/arch/riscv/vaplic.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index d772b42386c0..b9941a230e03 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -24,6 +24,7 @@ obj-y +=3D smpboot.o obj-y +=3D stubs.o obj-y +=3D time.o obj-y +=3D traps.o +obj-y +=3D vaplic.o obj-y +=3D vmid.o obj-y +=3D vm_event.o obj-y +=3D vsbi/ diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 515735b32e30..560b21b16ffb 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include =20 @@ -154,14 +155,8 @@ int arch_vcpu_create(struct vcpu *v) if ( (rc =3D vcpu_vtimer_init(v)) ) goto fail; =20 - /* - * As interrupt controller (IC) is not yet implemented, - * return an error. - * - * TODO: Drop this once IC is implemented. - */ - rc =3D -EOPNOTSUPP; - goto fail; + if ( (rc =3D v->domain->arch.vintc->ops->vcpu_init(v)) ) + goto fail; =20 return rc; =20 diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index bdb1ffd748c9..21a3e6876f36 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -98,6 +98,8 @@ struct arch_domain { struct paging_domain paging; #endif =20 + struct vintc *vintc; + /* Next unused device tree phandle number */ uint32_t next_phandle; }; diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index 8300d71d472f..c5a869db8bc5 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -16,6 +16,7 @@ struct cpu_user_regs; struct dt_device_node; struct irq_desc; struct kernel_info; +struct vcpu; =20 struct intc_info { enum intc_version hw_version; @@ -47,6 +48,19 @@ struct intc_hw_operations { const struct dt_device_node *intc); }; =20 +struct vintc_ops { + /* Initialize some vINTC-related stuff for a vCPU */ + int (*vcpu_init)(struct vcpu *vcpu); + + /* Check if a register is virtual interrupt controller MMIO */ + int (*is_access)(const struct vcpu *vcpu, const unsigned long addr); +}; + +struct vintc { + const struct intc_info *info; + const struct vintc_ops *ops; +}; + void intc_preinit(void); =20 void register_intc_ops(const struct intc_hw_operations *ops); diff --git a/xen/arch/riscv/include/asm/vaplic.h b/xen/arch/riscv/include/a= sm/vaplic.h new file mode 100644 index 000000000000..7684f3490829 --- /dev/null +++ b/xen/arch/riscv/include/asm/vaplic.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * xen/arch/riscv/vaplic.c + * + * Virtual RISC-V Advanced Platform-Level Interrupt Controller support + * + * Copyright (c) Microchip. + */ + +#ifndef ASM__RISCV__VAPLIC_H +#define ASM__RISCV__VAPLIC_H + +#include +#include + +#include + +struct domain; + +#define to_vaplic(v) container_of(v, struct vaplic, base) + +struct vaplic_regs { + uint32_t domaincfg; + uint32_t smsiaddrcfg; + uint32_t smsiaddrcfgh; +}; + +struct vaplic { + struct vintc base; + struct vaplic_regs regs; +}; + +int domain_vaplic_init(struct domain *d); +void domain_vaplic_deinit(struct domain *d); + +#endif /* ASM__RISCV__VAPLIC_H */ diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c index c9f12651fda1..ff7a76accaca 100644 --- a/xen/arch/riscv/intc.c +++ b/xen/arch/riscv/intc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include =20 #include diff --git a/xen/arch/riscv/vaplic.c b/xen/arch/riscv/vaplic.c new file mode 100644 index 000000000000..9b105de7ed7d --- /dev/null +++ b/xen/arch/riscv/vaplic.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: MIT */ +/* + * xen/arch/riscv/vaplic.c + * + * Virtual RISC-V Advanced Platform-Level Interrupt Controller support + * + * Copyright (c) Microchip. + * Copyright (c) Vates + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include "aplic-priv.h" + +static int __init cf_check vcpu_vaplic_init(struct vcpu *v) +{ + int rc =3D 0; + + rc =3D vcpu_imsic_init(v); + if ( rc ) + return rc; + + imsic_set_guest_file_id(v, vgein_assign(v)); + + return rc; +} + +static const struct vintc_ops vaplic_ops =3D { + .vcpu_init =3D vcpu_vaplic_init, +}; + +static struct vintc * __init vaplic_alloc(void) +{ + struct vaplic *v =3D NULL; + + v =3D xvzalloc(struct vaplic); + if ( !v ) + return NULL; + + return &v->base; +} + +int __init domain_vaplic_init(struct domain *d) +{ + int ret =3D 0; + + d->arch.vintc =3D vaplic_alloc(); + if ( !d->arch.vintc ) + { + ret =3D -ENOMEM; + goto fail; + } + + d->arch.vintc->ops =3D &vaplic_ops; + to_vaplic(d->arch.vintc)->regs.domaincfg =3D + APLIC_DOMAINCFG_IE | APLIC_DOMAINCFG_DM; + + fail: + return ret; +} + +void __init domain_vaplic_deinit(struct domain *d) +{ + struct vaplic *vaplic =3D to_vaplic(d->arch.vintc); + + XVFREE(vaplic); +} --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:28 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e635720d-1ca3-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162569; x=1773767369; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1QzhisNeEOl5GG/axHTaY1VrOGJ87S7KPahT63K4FL0=; b=QRnE/YbuQxS5aJsCV1+VHm3IC/UsB81S8opwqaYiMnl3i672gr5xq3uwdlCOzBOaHR HzEAe7scP69C2TpkeCRcpAwSZkj2qlea0fdUReJARKMwivOnu1QPubvlHIws9SBO7A6m ll1TAX5d7wHh7VA+ihPtpsJOoO7ud3BQmaBlobhUeC41cKAYhltGByFIqS0kanz0VDTM vW9Dbwg5JO3mhYWWenjb1bbRdCy4euHUot+8tzidopxZ0388Q9GwK0i0Hw6qhcRiKUTN yvp/9CK063/uTOaxKU4+FA550XTu7mHht1eVgRN552Ck+k45H+jx3WNOLEy1CzagNCdr kyTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162569; x=1773767369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=1QzhisNeEOl5GG/axHTaY1VrOGJ87S7KPahT63K4FL0=; b=uHhY1BSJcVMoHtrsi6XEY0VoUuRNenbTaAz593RRwsg+H3Znb8gj8Qlw1uGQJV5yU6 mPvpcA1DWm0OamktGw99yTDsWtx5yyk6HUyfLBJtNlZZONmyAmD29hEktzpXJIBrsERi ARAoxDF24ZvQBVBrhd6ofWQ+NA5Qz087di6RS/QuFJhVg8frSkk9W2F/0Mq0PJo0Sm1f K5BnYBie7IofBFf6BlEliWGhAwfQeujqss7KmgeGr0vye6ebT5Y5d9xSKCFcR7jI54Vh OOOJyCTUaYbEOmSZGsS3dLqnmS3MJrXd59g+gsk+K/BUYqhytwNs+/H5Vh1JNdORSkTc r6kQ== X-Gm-Message-State: AOJu0YwUjtVCh53HhmnBe9NzB1H9p2gVx2NwP+o51D3ElOjTAINqB1c5 IpAInqJZFqLx2WdPOaDTqEgBEXotpNTs81gxm8t1Z3WbgIYXh/atgEVKv2nOOgou X-Gm-Gg: ATEYQzybt1JojwHVHE5NESSNSDv6kr2dKw59Ge+Lq6sbMAIzu4k5URkk1oNlt/TZ+gs D1Bl4RW/qAEs4d+sb1PHA7rnh4NC9rRRhmYafay0oYuUrNZlQ+7pBB9VATgUSM5N5EOkN9Yy9J8 VWwVzH4EnbDexnUj8gvkhlA2GNw0L3kfSgIoZET5VDPnmCIx0EAIpp4JozMClpXdmk6IRK89abc 3FpiJppI5shIkgUpwW+KcJ/SFa1Ci60UJS+lcv9GeWCHtT2LIkD/hdzgKZ752qYUr74xgTrPsaq JLYHVNuF+7PuDoRpaidzhj00mqEyM0o8/KsZZ76+KxnpMVPz9hlzHrPWWNYXRGxs5HzDazY+YbJ 7ZbHdfpGRu7aBJN8zfzPEMKZ05JwmSf3NtVKTiS1cGSvZ79n2o4RRXaPF0zUhRnm4qXiJf+FP6r xg/0E8AmWEBX8oSYH/HeprzQwBKVJsZ+KGCuzz/LcgteOiZIstg6sfEEEsgf5EcSmSPA== X-Received: by 2002:a05:600c:8719:b0:485:39d1:b4ca with SMTP id 5b1f17b1804b1-48539d1bb25mr151543855e9.9.1773162568498; Tue, 10 Mar 2026 10:09:28 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 16/27] xen/riscv: implement IRQ mapping for device passthrough Date: Tue, 10 Mar 2026 18:08:49 +0100 Message-ID: <10654a6c38fa929b5fdf6f214badfe4f60fe78d4.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163069526158500 Content-Type: text/plain; charset="utf-8" Add initial support for assigning device interrupts to domains in dom0less configurations. IRQs described in the device tree are retrieved and authorized for the target domain. Interrupts that are not connected to the primary interrupt controller (at the momemnt, I haven't seen the platform with secondary interrupt controller) are ignored, and IRQs already assigned to another domain are rejected to prevent sharing. Signed-off-by: Oleksii Kurochko --- For better undesrstanding how auth_irq_bmp[] is going to be used it is also introduced two extra patches which are going after this. They aren't really needed now as this code will be used when guest will be ran, but it improves understanding and it in general can go with this patch series. --- --- xen/arch/riscv/include/asm/aplic.h | 2 + xen/arch/riscv/include/asm/intc.h | 12 +++ xen/arch/riscv/include/asm/setup.h | 17 ++++ xen/arch/riscv/intc.c | 8 ++ xen/arch/riscv/vaplic.c | 124 ++++++++++++++++++++++++++++- 5 files changed, 162 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/aplic.h b/xen/arch/riscv/include/as= m/aplic.h index b0724fe6f360..55cd4a128de7 100644 --- a/xen/arch/riscv/include/asm/aplic.h +++ b/xen/arch/riscv/include/asm/aplic.h @@ -15,6 +15,8 @@ =20 #include =20 +#define APLIC_NUM_REGS 32 + #define APLIC_DOMAINCFG_IE BIT(8, U) #define APLIC_DOMAINCFG_DM BIT(2, U) =20 diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index c5a869db8bc5..76d2fd09cb8b 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -16,6 +16,7 @@ struct cpu_user_regs; struct dt_device_node; struct irq_desc; struct kernel_info; +struct rangeset; struct vcpu; =20 struct intc_info { @@ -54,11 +55,22 @@ struct vintc_ops { =20 /* Check if a register is virtual interrupt controller MMIO */ int (*is_access)(const struct vcpu *vcpu, const unsigned long addr); + + /* + * Retrieves the interrupts configuration from a device tree node and = maps + * those interrupts to the target domain. + */ + int (*map_device_irqs_to_domain)(struct domain *d, + struct dt_device_node *dev, + bool need_mapping, + struct rangeset *irq_ranges); }; =20 struct vintc { const struct intc_info *info; const struct vintc_ops *ops; + + void *private; }; =20 void intc_preinit(void); diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h index 2215894cfbb1..1c23043f409f 100644 --- a/xen/arch/riscv/include/asm/setup.h +++ b/xen/arch/riscv/include/asm/setup.h @@ -5,6 +5,10 @@ =20 #include =20 +struct domain; +struct dt_device_node; +struct rangeset; + #define max_init_domid (0) =20 void setup_mm(void); @@ -13,6 +17,19 @@ void copy_from_paddr(void *dst, paddr_t paddr, unsigned = long len); =20 void init_csr_masks(void); =20 +/* TODO: move somewhere to common header? */ +/* + * Retrieves the interrupts configuration from a device tree node and maps + * those interrupts to the target domain. + * + * Returns: + * < 0 error + * 0 success + */ +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, + bool need_mapping, + struct rangeset *irq_ranges); + #endif /* ASM__RISCV__SETUP_H */ =20 /* diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c index ff7a76accaca..a91dbc5e997c 100644 --- a/xen/arch/riscv/intc.c +++ b/xen/arch/riscv/intc.c @@ -79,3 +79,11 @@ int __init intc_make_domu_dt_node(const struct kernel_in= fo *kinfo) =20 return -ENOSYS; } + +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, + bool need_mapping, + struct rangeset *irq_ranges) +{ + return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapp= ing, + irq_ranges); +} diff --git a/xen/arch/riscv/vaplic.c b/xen/arch/riscv/vaplic.c index 9b105de7ed7d..0c69f087cf4d 100644 --- a/xen/arch/riscv/vaplic.c +++ b/xen/arch/riscv/vaplic.c @@ -9,6 +9,7 @@ */ =20 #include +#include #include #include =20 @@ -19,6 +20,113 @@ =20 #include "aplic-priv.h" =20 +struct vaplic_priv { + /* Contains a legal interrupts for a domain */ + uint32_t auth_irq_bmp[APLIC_NUM_REGS]; +}; + +static bool is_irq_shared_among_domains(const struct domain *d, + const unsigned int irq_num) +{ + struct domain *tmp; + unsigned int reg_num =3D irq_num / APLIC_NUM_REGS; + unsigned int bit_pos =3D irq_num % APLIC_NUM_REGS; + + for_each_domain ( tmp ) + { + uint32_t *auth_irq_bmp; + + if ( tmp =3D=3D d ) + continue; + + auth_irq_bmp =3D tmp->arch.vintc->private; + + if ( auth_irq_bmp[reg_num] & BIT(bit_pos, U) ) + { + printk("%s: irq%d is shared between %pd and %pd\n", __func__, + irq_num, tmp, d); + + return true; + } + } + + return false; +} + +int vaplic_map_device_irqs_to_domain(struct domain *d, + struct dt_device_node *dev, + bool need_mapping, + struct rangeset *irq_ranges) +{ + unsigned int i, nirq; + int res, irq; + struct dt_raw_irq rirq; + uint32_t *auth_irq_bmp =3D d->arch.vintc->private; + unsigned int reg_num; + + nirq =3D dt_number_of_irq(dev); + + /* Give permission and map IRQs */ + for ( i =3D 0; i < nirq; i++ ) + { + res =3D dt_device_get_raw_irq(dev, i, &rirq); + if ( res ) + { + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", + i, dt_node_full_name(dev)); + return res; + } + + /* + * Don't map IRQ that have no physical meaning + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. + */ + if ( rirq.controller !=3D dt_interrupt_controller ) + { + dt_dprintk("irq %u not connected to primary controller." + "Connected to %s\n", i, + dt_node_full_name(rirq.controller)); + continue; + } + + irq =3D platform_get_irq(dev, i); + if ( irq < 0 ) + { + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(d= ev)); + return irq; + } + + res =3D irq_permit_access(d, irq); + if ( res ) + { + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n"= , d, + irq); + return res; + } + + reg_num =3D irq / APLIC_NUM_REGS; + + if ( is_irq_shared_among_domains(d, irq) ) + { + printk("%s: Shared IRQ isn't supported\n", __func__); + return -EINVAL; + } + + auth_irq_bmp[reg_num] |=3D BIT(irq % APLIC_NUM_REGS, U); + + dt_dprintk(" - IRQ: %u\n", irq); + + if ( irq_ranges ) + { + res =3D rangeset_add_singleton(irq_ranges, irq); + if ( res ) + return res; + } + } + + return 0; +} + static int __init cf_check vcpu_vaplic_init(struct vcpu *v) { int rc =3D 0; @@ -34,6 +142,7 @@ static int __init cf_check vcpu_vaplic_init(struct vcpu = *v) =20 static const struct vintc_ops vaplic_ops =3D { .vcpu_init =3D vcpu_vaplic_init, + .map_device_irqs_to_domain =3D vaplic_map_device_irqs_to_domain, }; =20 static struct vintc * __init vaplic_alloc(void) @@ -62,13 +171,26 @@ int __init domain_vaplic_init(struct domain *d) to_vaplic(d->arch.vintc)->regs.domaincfg =3D APLIC_DOMAINCFG_IE | APLIC_DOMAINCFG_DM; =20 + d->arch.vintc->private =3D xvzalloc(struct vaplic_priv); + if ( !d->arch.vintc->private ) + { + ret =3D -ENOMEM; + goto fail; + } + + return ret; + fail: + domain_vaplic_deinit(d); + return ret; } =20 void __init domain_vaplic_deinit(struct domain *d) { - struct vaplic *vaplic =3D to_vaplic(d->arch.vintc); + struct vintc *vintc =3D d->arch.vintc; + struct vaplic *vaplic =3D to_vaplic(vintc); =20 + XVFREE(vintc->private); XVFREE(vaplic); } --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773163134; cv=none; d=zohomail.com; s=zohoarc; b=jOtKodktCeGKo9y+D9H19U8OmU4/LYbZJGDD3UCoGpYn6FV0A0C/WxU3+5t+hKDAhTnkJ70XeDpJfnW8BPI2w80OlwhU62ELqtqYXy3I0mh+VKK+GGWwbb4a0zniwW+eO/+kEew8Cfol7eRNVUSTKIee9w3x9zFevcFA70nOFdQ= ARC-Message-Signature: i=1; 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Date: Tue, 10 Mar 2026 18:08:50 +0100 Message-ID: <2097fefb49fca36f641ddd7d7fb31e796a03619e.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163135734158500 Content-Type: text/plain; charset="utf-8" These definitions are required for correct decoding of APLIC MMIO accesses and target configuration, and will be used by both the physical and virtual APLIC implementations. No functional change is intended by this patch; it only centralises hardware definitions that were previously missing. Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/aplic.h | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/xen/arch/riscv/include/asm/aplic.h b/xen/arch/riscv/include/as= m/aplic.h index 55cd4a128de7..7e9161d98ceb 100644 --- a/xen/arch/riscv/include/asm/aplic.h +++ b/xen/arch/riscv/include/asm/aplic.h @@ -17,6 +17,11 @@ =20 #define APLIC_NUM_REGS 32 =20 +#define APLIC_REG_OFFSET_MASK 0x3FFF +#define APLIC_TARGET_IPRIO_MASK 0xFF +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 +#define APLIC_TARGET_EIID_MASK 0x7FF + #define APLIC_DOMAINCFG_IE BIT(8, U) #define APLIC_DOMAINCFG_DM BIT(2, U) =20 @@ -27,6 +32,36 @@ #define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 #define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 =20 +#define APLIC_DOMAINCFG 0x0000 +#define APLIC_SOURCECFG_BASE 0x0004 +#define APLIC_SOURCECFG_LAST 0x0FFC + +#define APLIC_SMSICFGADDR 0x1BC8 +#define APLIC_SMSICFGADDRH 0x1BCC + +#define APLIC_SETIP_BASE 0x1C00 +#define APLIC_SETIP_LAST 0x1C7C +#define APLIC_SETIPNUM 0x1CDC + +#define APLIC_CLRIP_BASE 0x1D00 +#define APLIC_CLRIP_LAST 0x1D7C +#define APLIC_CLRIPNUM 0x1DDC + +#define APLIC_SETIE_BASE 0x1E00 +#define APLIC_SETIE_LAST 0x1E7C +#define APLIC_SETIENUM 0x1EDC + +#define APLIC_CLRIE_BASE 0x1F00 +#define APLIC_CLRIE_LAST 0x1F7C +#define APLIC_CLRIENUM 0x1FDC + +#define APLIC_SETIPNUM_LE 0x2000 + +#define APLIC_GENMSI 0x3000 + +#define APLIC_TARGET_BASE 0x3004 +#define APLIC_TARGET_LAST 0x3FFC + #define APLIC_TARGET_HART_IDX_SHIFT 18 =20 struct aplic_regs { --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773163134; cv=none; d=zohomail.com; s=zohoarc; b=l/1QxRGMran5WcuUkAu8aXb6yWsYw/75PO4AUi39JCOIJH4pmSY6BrEsaU80lQ25m0u+LU+diZ7KA1+bWv5qHgvFTAAcuCsFbwLDB3Jv8UHlnHdCnpfk4+CzTUUBV+OHGtRaXBRtQTBXzMd7XFdiStXpvhgIohUbnuCHFkFGI4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773163134; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hH9znhbJsO7IzrzhoOYnrjac5Z3LLI2ieI1hChueBHI=; b=a59qE4HUZ03Qi/knZZeiviU1MIxKzF6oBkhpDzDz/t8kXINGA8G+Cq5vpvZhsW5KrG/lIaXMBLmiGVqhFtgtJpDZOlFO3oM36FqSJdkT1srg636vb/ohP5I+nPvcXi1P1IDvYnXLsp+I9W3H38RX8QgqIukOQgda8WcGU95uXAU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773163134559348.5721484311895; Tue, 10 Mar 2026 10:18:54 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250569.1548071 (Exim 4.92) (envelope-from ) id 1w00j8-0005ql-9E; Tue, 10 Mar 2026 17:18:38 +0000 Received: by outflank-mailman (output) from mailman id 1250569.1548071; Tue, 10 Mar 2026 17:18:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00j8-0005pe-63; Tue, 10 Mar 2026 17:18:38 +0000 Received: by outflank-mailman (input) for mailman id 1250569; Tue, 10 Mar 2026 17:18:37 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00aL-0001Q4-H7 for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:33 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e7a07e20-1ca3-11f1-b164-2bf370ae4941; Tue, 10 Mar 2026 18:09:31 +0100 (CET) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4852c9b4158so28934155e9.0 for ; Tue, 10 Mar 2026 10:09:31 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:30 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e7a07e20-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162571; x=1773767371; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hH9znhbJsO7IzrzhoOYnrjac5Z3LLI2ieI1hChueBHI=; b=Y4DkD/FJ6idyy/ETSIEB3Lce9eUGQw5qOmA5brIy9bFsihE5ZkKdJivL5KOxB3BaeX SQ0fBpcbDGKb+qltfLu6uqgQMOlYBJr7VfCJ9SCwBET2c7s6k4L9/e2MEtAtvjoKrR4s xXj6GLQGX2pd9W4cPwHj+NNBZUIzP//YY0s6ugNpHuIOVtoQmTAcBdG40mNU8QbAsBr9 tJUV2gKNyw07ofkZy9hc2sNUjKjMJLU7nC7eFh3ZZz+Zu0Jqn3xmd2PgJn3MH8MOxxr+ AFnXIfHCRd0eAm97JNB/vYubKihg7X7tqcXBKxeoDAoRNDa+FKwSQU9s9OIt+b3CobW0 47LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162571; x=1773767371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=hH9znhbJsO7IzrzhoOYnrjac5Z3LLI2ieI1hChueBHI=; b=s5bIpSPsmRDMnARCaWBRrBfgJ7kiKLqVfkgygy+f4vsIql46lN0tUGh85UbxzBkHcM H4GC/RLg4Fiuwb1ctU6iSd245i/sOowycwTjlRQAnIh8WGQ8hvC2hB4EGfZT3W55Yeoq NYsXcqGaMVeyUUyYMSOGgVsCq+98Cs9J6LNWL7oF6vp4DQMKMB1fQGMql95P7QDr7mUt A83abdLLH4xjM9df3QiOTunTrXRqQ2HeH92tlUCgrtBIMcT24ygzSICFV9VksGZ6mSNt c6G0B6Juc+wGFoJ6hzOjFuQ6ri8JW+jBZrLwFPANEPq1+N4GSTVsYrJwLk5Vea5jBV6Z n5hQ== X-Gm-Message-State: AOJu0YzXHUVXdt6ffDH5Zma2zKtV5EEJ+6aCOZ0y4WGDOMN8keEm+6ms 4oExoqL05jtpzH84MVngwK9diCZ8eJIp5RHB0lgHLl/mrMj+XfcFSXX6D06hMZR8 X-Gm-Gg: ATEYQzzzPkY4PTwqAcym4km0sRIM7X4QhNVdyN7qvxKjyVRS0gB9mtyU0PI7SB+DdWa I+/7qmRwQUOye3njOV/DRQRFirWK1QLeGlU62Ywj6Xo8TNm8lT53S77z6zXfP22Wz30I3zfXQdk X3thEGSgoXAsb1PgEcyMYCUYtMqjvpglSTWaebSNuaMwG71uqbu6UoRXmhwzFnGWrawrBeSXqYp OCihTGWPjNjW83gEe4UZNAxkUCh4xhmQePyOINiXwFKuRYgO3xAnbWvBUnXEYwmR7tejQhoEugB q1KghQHiiN/c53sqjEmJvo/NaEluMNn4zf7WsqwwYLe6JfZVLS6UHqJykaeTc8PC4oHbNr2peMw A8TFuqljC57yyZk8AXtgl1W3tXUb2N5uxtspaDDpqLg/z7PYvVGPtDi8aA2+xqrCKsAqAIrWhLz LB+aJTin3SZPZ+XvPbsGBYG4XzGiEVyLOQBmlbv0FXXu4iDrPWR+lzFU1yb0dpK2165zjNlQ== X-Received: by 2002:a05:600c:8707:b0:485:3ff1:d5c3 with SMTP id 5b1f17b1804b1-4853ff1d6a6mr122929915e9.5.1773162570910; Tue, 10 Mar 2026 10:09:30 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 18/27] xen/riscv: add vaplic access check Date: Tue, 10 Mar 2026 18:08:51 +0100 Message-ID: <0fc9adf790d4f981e8117bd9759c7e64bb11e439.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163135980154100 Content-Type: text/plain; charset="utf-8" Provide a mechanism for the virtual APLIC to determine whether a guest access targets the physical APLIC MMIO region. This is required to correctly identify and route guest APLIC accesses. Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/aplic.c | 1 + xen/arch/riscv/include/asm/intc.h | 3 +++ xen/arch/riscv/vaplic.c | 15 +++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/xen/arch/riscv/aplic.c b/xen/arch/riscv/aplic.c index e139946a05a0..754b444a2a13 100644 --- a/xen/arch/riscv/aplic.c +++ b/xen/arch/riscv/aplic.c @@ -38,6 +38,7 @@ static struct aplic_priv aplic =3D { =20 static struct intc_info __ro_after_init aplic_info =3D { .hw_version =3D INTC_APLIC, + .private =3D &aplic, }; =20 static void __init aplic_init_hw_interrupts(void) diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index 76d2fd09cb8b..e6b6c179415a 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -25,6 +25,9 @@ struct intc_info { =20 /* number of irqs */ unsigned int num_irqs; + + /* private data pointer of the interrupt controller */ + void *private; }; =20 struct intc_hw_operations { diff --git a/xen/arch/riscv/vaplic.c b/xen/arch/riscv/vaplic.c index 0c69f087cf4d..82e74a609ee6 100644 --- a/xen/arch/riscv/vaplic.c +++ b/xen/arch/riscv/vaplic.c @@ -127,6 +127,20 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, return 0; } =20 +static int cf_check vaplic_is_access(const struct vcpu *vcpu, + const unsigned long addr) +{ + const struct vaplic *vaplic =3D to_vaplic(vcpu->domain->arch.vintc); + const struct aplic_priv *priv =3D vaplic->base.info->private; + const paddr_t paddr_end =3D priv->paddr_start + priv->size; + + /* check if it is an APLIC access */ + if ( priv->paddr_start <=3D addr && addr < paddr_end ) + return 1; + + return 0; +} + static int __init cf_check vcpu_vaplic_init(struct vcpu *v) { int rc =3D 0; @@ -143,6 +157,7 @@ static int __init cf_check vcpu_vaplic_init(struct vcpu= *v) static const struct vintc_ops vaplic_ops =3D { .vcpu_init =3D vcpu_vaplic_init, .map_device_irqs_to_domain =3D vaplic_map_device_irqs_to_domain, + .is_access =3D vaplic_is_access, }; =20 static struct vintc * __init vaplic_alloc(void) --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:31 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e86f8024-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162572; x=1773767372; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dla2ZfjKuAdtGf39njgNy8xyCVJufRaAAQSeRsdKKdA=; b=RIb/tv4cYnIPfFle98vInh+ohr451UXDC/EyxAOwEMmzdq2mKFZeiAqiXpHz1I7l5A N4T/ncLVrATIdFPF+KY6pzb0aYbWzoe6GaXioto//Ofiv9AP5M/Fk+lpfIZRx46l1OXO /Jb36T0qPXvwryMlZc5z1yb4Ol2uJ+IQZxHdWccwVL5jCaO2INmKkLTJhzBkAJB+ziHF 6w4vWW7qgN4uceQ86Zc5/8CAXWrgXNzmXdXmB7cZgHR/TaAJd8GpozNgbe98GrtyiQOW LQ3+YKnewLEGxXBx2q47yL5AqX16ohdT5T5cGS+AWOw7UhnbNCkmzp0N9gE8vFUOj/rt 1EGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162572; x=1773767372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dla2ZfjKuAdtGf39njgNy8xyCVJufRaAAQSeRsdKKdA=; b=lRN+lRlSQ67kytKB7gVJSz/Tx4zZCawruhHr6LgV0t1uSsMtVKu+OByQRA9FOy+To+ EorKqrA2rbPGTKJ/pqIBoHzSLVxURsjpAvBPkYTpQhLg5JbUqnTRm3SUxRopYMbxo3dz JqlUp01WJEfMqxSzdn+ggsge90JJ2yBnQkP0xenUWHCe2avRpgv/s0PqgZYwoazORlBA YUhqF57NyJHDbkW3Svgw8rpsCyqIDN09yXlYCfeDyMRojGXhoWIWzJEkmKbw7FmstwwM GKwlU37rs1YCZWh8j58npqM6jYGxNgk9u7p1HuW1ETmMaafF+iEcVNNbnmNxNAxJUJkY DzSw== X-Gm-Message-State: AOJu0YxYNN4ctG4lCMHCbzmJp3aEyvA9Ky+iu67+G+qG3+qvR2Ib9zl5 xzVrng4Qf5kVAAvXgyj8+HPM8S/6JaRKlUkr98De8nAKhAcctt6PdPefMRIRNMMh X-Gm-Gg: ATEYQzy2J2cgC/xJ68DXEViZb6l6TESe3/fjBpj/y+JAJ6j2Rjm8ByZ5ux8Gif8KoX+ XtwDb1LOZcnz5agsb87JAJso1CEe13YOCJtWxH48j74sbAQKS39LxGlP9/3uMM27g7eQUW2h6XR lPNBhGgxVdR1R0fRdVy736D0nzDZbVi2yJ7f7a4bxeSm6mj/beHLSr1wSO6V0Mf9xzuIBraJGo+ DbAyrDUoN3mZde4ltqrYaGu2oLK74rim8fRh2hDYSdb2ptjWROUZCqqLcLsbGQeU+X6ghonlSUL XJk9EKGPI5zQkgPlfVFwqj6pCwgyIStoy03ySFguhlyqHVECarzliRS+/g17FNNGXsWmhvZitSs dhHtqXgRzGYamh+GYVjXZGTbosvTieldk3d1Dt29V8mrAoPV4rEx3mEa9gnoQPX6Vvn3qhlhq35 sfR9WHQBPx06QGRuuYTbSEbMiN0AM2mTfH+URL36i6O9LtwNInu8oOchFXqEX0gC1obg== X-Received: by 2002:a05:600c:46c4:b0:485:304a:58cd with SMTP id 5b1f17b1804b1-485304a5a00mr211584565e9.4.1773162571955; Tue, 10 Mar 2026 10:09:31 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 19/27] xen/riscv: emulate guest writes to virtual APLIC MMIO Date: Tue, 10 Mar 2026 18:08:52 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163089316154100 RISC-V guests program interrupt routing by writing to APLIC registers. When APLIC is virtualised, Xen must intercept these MMIO writes and translate them into updates of the virtual interrupt controller state. Introduce vaplic_emulate_store() to validate guest APLIC accesses and apply only those changes that are permitted by the domain=E2=80=99s authori= sed interrupt bitmap. Writes targeting unauthorised interrupts are ignored, ensuring that guests cannot affect interrupts they do not own. APLIC TARGET writes are rewritten to reflect the effective interrupt delivery configuration, depending on whether the domain operates in direct (isn't supported by Xen) or MSI mode. This ensures that guest-visible routing requests are correctly mapped onto the underlying virtual interrupt topology. Unexpected or unsupported register accesses are treated as fatal, as they indicate a emulation bug. Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/intc.h | 4 + xen/arch/riscv/vaplic.c | 169 ++++++++++++++++++++++++++++++ 2 files changed, 173 insertions(+) diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index e6b6c179415a..92a74eede4a0 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -56,6 +56,10 @@ struct vintc_ops { /* Initialize some vINTC-related stuff for a vCPU */ int (*vcpu_init)(struct vcpu *vcpu); =20 + /* Emulate store to virtual interrupt controller MMIOs */ + int (*emulate_store)(const struct vcpu *vcpu, unsigned long addr, + uint32_t in); + /* Check if a register is virtual interrupt controller MMIO */ int (*is_access)(const struct vcpu *vcpu, const unsigned long addr); =20 diff --git a/xen/arch/riscv/vaplic.c b/xen/arch/riscv/vaplic.c index 82e74a609ee6..5540b4884179 100644 --- a/xen/arch/riscv/vaplic.c +++ b/xen/arch/riscv/vaplic.c @@ -20,6 +20,16 @@ =20 #include "aplic-priv.h" =20 +#define APLIC_REG_GET(addr, offset) \ + readl((void *)((vaddr_t)(addr) + offset)) +#define APLIC_REG_SET(addr, offset, value) \ + writel(value, (void *)((vaddr_t)(addr) + offset)) + +#define AUTH_IRQ_BIT(irqnum) (auth_irq_bmp[(irqnum) / APLIC_NUM_REGS] & \ + BIT((irqnum) % APLIC_NUM_REGS, U)) + +#define regval_to_irqn(reg_val) ((reg_val) / sizeof(uint32_t)) + struct vaplic_priv { /* Contains a legal interrupts for a domain */ uint32_t auth_irq_bmp[APLIC_NUM_REGS]; @@ -127,6 +137,164 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, return 0; } =20 +static void vaplic_dm_update_target(const unsigned long hart_id, uint32_t = *iprio) +{ + *iprio &=3D APLIC_TARGET_IPRIO_MASK; + *iprio |=3D (hart_id << APLIC_TARGET_HART_IDX_SHIFT); +} + +static void vaplic_update_target(const struct imsic_config *imsic, + const int guest_id, + const unsigned long hart_id, uint32_t *va= lue) +{ + unsigned long group_index; + unsigned int hhxw =3D imsic->group_index_bits; + unsigned int lhxw =3D imsic->hart_index_bits; + unsigned int hhxs =3D imsic->group_index_shift - IMSIC_MMIO_PAGE_SHIFT= * 2; + unsigned long base_ppn =3D imsic->msi[hart_id].base_addr >> IMSIC_MMIO= _PAGE_SHIFT; + + group_index =3D (base_ppn >> (hhxs + 12)) & (BIT(hhxw, UL) - 1); + + *value &=3D APLIC_TARGET_EIID_MASK; + *value |=3D guest_id << APLIC_TARGET_GUEST_IDX_SHIFT; + *value |=3D hart_id << APLIC_TARGET_HART_IDX_SHIFT; + *value |=3D group_index << (lhxw + APLIC_TARGET_HART_IDX_SHIFT) ; +} + +#define CALC_REG_VALUE(base) \ +{ \ + uint32_t index; \ + uint32_t tmp_val; \ + index =3D regval_to_irqn(offset - base); \ + tmp_val =3D APLIC_REG_GET(priv->regs, aplic_addr) & ~auth_irq_bmp[inde= x]; \ + value &=3D auth_irq_bmp[index]; \ + value |=3D tmp_val; \ +} + +static int cf_check vaplic_emulate_store(const struct vcpu *vcpu, + unsigned long addr, uint32_t valu= e) +{ + struct vaplic *vaplic =3D to_vaplic(vcpu->domain->arch.vintc); + struct aplic_priv *priv =3D vaplic->base.info->private; + uint32_t offset =3D addr & APLIC_REG_OFFSET_MASK; + unsigned long aplic_addr =3D addr - priv->paddr_start; + const uint32_t *auth_irq_bmp =3D vcpu->domain->arch.vintc->private; + + switch ( offset ) + { + case APLIC_SETIP_BASE ... APLIC_SETIP_LAST: + CALC_REG_VALUE(APLIC_SETIP_BASE); + break; + + case APLIC_CLRIP_BASE ... APLIC_CLRIP_LAST: + CALC_REG_VALUE(APLIC_CLRIP_BASE); + break; + + case APLIC_SETIE_BASE ... APLIC_SETIE_LAST: + CALC_REG_VALUE(APLIC_SETIE_BASE); + break; + + case APLIC_CLRIE_BASE ... APLIC_CLRIE_LAST: + CALC_REG_VALUE(APLIC_CLRIE_BASE); + break; + + case APLIC_SOURCECFG_BASE ... APLIC_SOURCECFG_LAST: + /* We don't suppert delagation, so bit10 if sourcecfg should be 0 = */ + ASSERT(!(value & BIT(10, U))); + + /* + * As sourcecfg register starts from 1: + * 0x0000 domaincfg + * 0x0004 sourcecfg[1] + * 0x0008 sourcecfg[2] + * ... + * 0x0FFC sourcecfg[1023] + * It is necessary to calculate an interrupt number by substracting + * of APLIC_DOMAINCFG instead of APLIC_SOURCECFG_BASE. + */ + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_DOMAINCFG)) ) + /* interrupt not enabled, ignore it */ + return 0; + + break; + + case APLIC_TARGET_BASE ... APLIC_TARGET_LAST: + struct vcpu *target_vcpu =3D NULL; + + /* + * Look at vaplic_emulate_load() for explanation why + * APLIC_GENMSI is substracted. + */ + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_GENMSI)) ) + /* interrupt not enabled, ignore it */ + return 0; + + for ( int i =3D 0; i < vcpu->domain->max_vcpus; i++ ) + { + struct vcpu *v =3D vcpu->domain->vcpu[i]; + + if ( v->vcpu_id =3D=3D (value >> APLIC_TARGET_HART_IDX_SHIFT) ) + { + target_vcpu =3D v; + break; + } + } + + ASSERT(target_vcpu); + + if ( !(vaplic->regs.domaincfg & APLIC_DOMAINCFG_DM) ) + { + vaplic_dm_update_target(cpuid_to_hartid(target_vcpu->processor= ), + &value); + } + else + vaplic_update_target(priv->imsic_cfg, + vcpu_guest_file_id(target_vcpu), + cpuid_to_hartid(target_vcpu->processor), + &value); + + break; + + case APLIC_SETIPNUM: + case APLIC_SETIPNUM_LE: + case APLIC_CLRIPNUM: + case APLIC_SETIENUM: + case APLIC_CLRIENUM: + if ( AUTH_IRQ_BIT(value) ) + break; + + return 0; + + case APLIC_DOMAINCFG: + /* + * TODO: + * The domaincfg register has this format: + * bits 31:24 read-only 0x80 + * bit 8 IE + * bit 7 read-only 0 + * bit 2 DM (WARL) + * bit 0 BE (WARL) + * + * The most interesting bit for us is IE(Interrupt Enable) bit. + * At the moment, at least, Linux doesn't use domaincfg.IE bit to + * disable interrupts globally, but if one day someone will use it + * then extra actions should be done. + */ + + printk_once("%s: Nothing to do, domaincfg is set by aplic during " + "initialization in Xen\n", __func__); + + return 0; + + default: + panic("%s: unsupported register offset: %#x\n", __func__, offset); + } + + APLIC_REG_SET(priv->regs, aplic_addr, value); + + return 0; +} + static int cf_check vaplic_is_access(const struct vcpu *vcpu, const unsigned long addr) { @@ -158,6 +326,7 @@ static const struct vintc_ops vaplic_ops =3D { .vcpu_init =3D vcpu_vaplic_init, .map_device_irqs_to_domain =3D vaplic_map_device_irqs_to_domain, .is_access =3D vaplic_is_access, + .emulate_store =3D vaplic_emulate_store, }; =20 static struct vintc * __init vaplic_alloc(void) --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:32 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e916d655-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162573; x=1773767373; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vggNX4iy/s3rYe31fA6JCPRN0nqiyw41a2u9JUGJC2M=; b=A2A7GGJ0CAL4ikMnK2xD81wYIzdXp39h5Zq/4vsUGRd5AAbzcp2wfPNKv4aCeFr04B C4IbuMfaJg+/kwf7iFC7ERmKa2lyb/rL60QRuKtcY+M5bQ0kRLhYbvE82t5yai5yh3rf /avseKkvQXMffFCmcBc/FeMTFbjpP9WW61twM2zGhRBwzJVbBl9DaB5SHGLr+XVJ2J26 uGpNrwjofjMFzPFKjfSnCPe278/WhkG0LOvCONnmF5/7++mAxzgQu/CrYLHjzobcuMXp xeJacLC+YzLuSdchQgjCPfOWsDtUDr0prU6K+szRuJKjE4jxzn0q3asWrKyvDMvK5Tzy HQYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162573; x=1773767373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=vggNX4iy/s3rYe31fA6JCPRN0nqiyw41a2u9JUGJC2M=; b=Ig6dVDQ+LcTI/hW/gNALG5n4zaBY5wgNasgTTkJ4IEcQLvm+1Wq8658V+Q84j7rO14 eXVqsgEVi4uWTXQO68mFpKgebN3sHw+E4sFBiYbyngX6A7x4xC2n8bXfMCYvsuDVqN21 sdCoDBrqOmzzb6Vg/Rpii8HVBfOq4W560EjSnPvAS+nrarQ1LTapvErbtHJm387d43JX Jzx+0HwnfNIJ/fRIBwBa5D7sQGaXmj4eTdEsBsuhPuDH1mUt9efG6fG0xabWX5YbgenC tIuKWGqPoBykdjwjASKL7Df5f8v/Lq5dnWG89zK3Ix2jkzVekOXHdgAT5PTs6RPeGDql CIzA== X-Gm-Message-State: AOJu0YxHYzbxq5VrgemTmpLf7h5FhkmIfrK8Fi9ObWdSLz2wOJuE5pHv FFdfmOHZFv0QrMiXQwwGs51QLEOF+ev2K3HAH9iK6BiHqV+3CRgK9FlwB9lZOYo1 X-Gm-Gg: ATEYQzxt0YRSDIoNzbT7YtZ4xE66nEdsGPuZf1CMrlnU2egtqfIJaukap7FwDAhJVMG Bv3IAXfyZTAorslb5BBZgUumzuIqXiSoI7tYB++k1faqAVA+vsyqKYwGGz3ne2QlTncm8WpleKS rOtAewu+pwtW6TnTBYz6GYH9DDeZAu3B8wapYPhB59y7CrPR6R8EczrceWT3CAuzZyStowGC+5m DiKGicdCJuU/SXmH3aFf23LhCYlN+ca2ecqI8n8BA3vzcwm7GMp6PIFCqDs7j1MZTEEom/4nZNE 9P/EnKbLGT7MyHlDbxye5MhdoFzSjdvQsJj4+YhfpX1Y4Ef95C33LJdgmCDVVAjRlVTi0hiNC3x HWIOKZB0mzZ7jfAqBFcZpIHtDx2Y6yRHNU4EYIYqDi2j61xrRJC/cGY3LT0xFCOHKp6mRiLwZMg 5fu30+Oej0zHO7+t75TBUU2+4yRdP9lfxIcpNHL1GqYp6J/O8Fnf/gN+dWy0z1hylL5g== X-Received: by 2002:a05:600c:a08b:b0:485:42ba:fc8 with SMTP id 5b1f17b1804b1-48542ba105dmr58826615e9.4.1773162573184; Tue, 10 Mar 2026 10:09:33 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 20/27] xen/riscv: emulate guest reads from virtual APLIC MMIO Date: Tue, 10 Mar 2026 18:08:53 +0100 Message-ID: <626d0874c2c7ec858725860bc3857691f0f829ad.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163081535158500 Guests may read back APLIC registers to inspect interrupt state and routing configuration. When virtualising APLIC, Xen must intercept these MMIO reads and present a consistent, restricted view of the virtual interrupt controller state. Note that at the moment only MSI mode is supported. Introduce vaplic_emulate_load() to handle guest loads from virtual APLIC registers. Readback is filtered through the domain=E2=80=99s authoris= ed interrupt bitmap so that guests can observe state only for interrupts they are permitted to control. Registers defined by the AIA specification to read as zero are handled accordingly, while other registers return masked values derived from the underlying virtual APLIC state. Unsupported accesses are treated as fatal, as they indicate a emulation error. Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/intc.h | 4 ++ xen/arch/riscv/vaplic.c | 69 +++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index 92a74eede4a0..45d41e191e30 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -56,6 +56,10 @@ struct vintc_ops { /* Initialize some vINTC-related stuff for a vCPU */ int (*vcpu_init)(struct vcpu *vcpu); =20 + /* Emulate load to virtual interrupt controller MMIOs */ + int (*emulate_load)(const struct vcpu *vcpu, unsigned long addr, + uint32_t *out); + /* Emulate store to virtual interrupt controller MMIOs */ int (*emulate_store)(const struct vcpu *vcpu, unsigned long addr, uint32_t in); diff --git a/xen/arch/riscv/vaplic.c b/xen/arch/riscv/vaplic.c index 5540b4884179..293729ad0ad4 100644 --- a/xen/arch/riscv/vaplic.c +++ b/xen/arch/riscv/vaplic.c @@ -137,6 +137,74 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, return 0; } =20 +static int vaplic_emulate_load(const struct vcpu *vcpu, + const unsigned long addr, uint32_t *out) +{ + const struct vaplic *vaplic =3D to_vaplic(vcpu->domain->arch.vintc); + struct aplic_priv *priv =3D vaplic->base.info->private; + const unsigned long offset =3D addr & APLIC_REG_OFFSET_MASK; + const uint32_t *auth_irq_bmp =3D vcpu->domain->arch.vintc->private; + bool auth_bit; + + switch ( offset ) + { + case APLIC_DOMAINCFG: + *out =3D vaplic->regs.domaincfg; + break; + + case APLIC_SETIPNUM: + case APLIC_SETIPNUM_LE: + case APLIC_CLRIPNUM: + case APLIC_SETIENUM: + /* + * Based on the RISC-V AIA sepc a read of these registers + * always returns zero + */ + *out =3D 0; + break; + + case APLIC_SETIP_BASE ... APLIC_SETIP_LAST: + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_SETIP_BASE= )]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + case APLIC_CLRIP_BASE ... APLIC_CLRIP_LAST: + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_CLRIP_BASE= )]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + case APLIC_SETIE_BASE ... APLIC_SETIE_LAST: + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_CLRIP_BASE= )]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + case APLIC_CLRIE_BASE ... APLIC_CLRIE_LAST: + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_CLRIE_BASE= )]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + case APLIC_TARGET_BASE ... APLIC_TARGET_LAST: + /* + * As target registers start for 1: + * 0x3000 genmsi + * 0x3004 target[1] + * 0x3008 target[2] + * ... + * 0x3FFC target[1023] + * It is necessary to calculate an interrupt number by substracting + * of APLIC_GENMSI instead of APLIC_TARGET_BASE. + */ + auth_bit =3D auth_irq_bmp[regval_to_irqn(offset - APLIC_GENMSI)]; + *out =3D APLIC_REG_GET(priv->regs, addr - priv->paddr_start) & aut= h_bit; + break; + + default: + panic("%s: unsupported register offset: %#lx", __func__, offset); + } + + return 0; +} + static void vaplic_dm_update_target(const unsigned long hart_id, uint32_t = *iprio) { *iprio &=3D APLIC_TARGET_IPRIO_MASK; @@ -327,6 +395,7 @@ static const struct vintc_ops vaplic_ops =3D { .map_device_irqs_to_domain =3D vaplic_map_device_irqs_to_domain, .is_access =3D vaplic_is_access, .emulate_store =3D vaplic_emulate_store, + .emulate_load =3D vaplic_emulate_load, }; =20 static struct vintc * __init vaplic_alloc(void) --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773163148; cv=none; d=zohomail.com; s=zohoarc; b=aGNkZKyZAtvKGNHGd9OGtwvzgRaPwbd0lWJyMjzL6G/Ek2RoBYMMBKa+cdybwwhcGIPDhHuYHbZJGZD1gFMCxIy9TtC4KcvvmEJa2UZEihqfT6Wk9PWHzrOZajyuRhJEGeMq5CB9DAbxEz55JZT/Tvx16OCPpNUh1AzrlsuP0HQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773163148; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eOghi8Ll3/sbazIkniNGMCKDlS8jGFlMwoa4Be1UqI8=; b=ZnnTKafPoY2lIKtOA2X1oSXOxy2YMrvn8R7sCU1woEbU+gE0qfxVxXHTRQq2vsFEWR6f/ifYcq6Phx2IMnJBAdx9/zFCJsP4ONc8JJI5o8Ho9cVV0e4sPDYE6KND+YosnSefcumlhniI98eSFWUaUTh6c3QBa9eYo7umva+hiq8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773163148270737.9864341403161; Tue, 10 Mar 2026 10:19:08 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250580.1548089 (Exim 4.92) (envelope-from ) id 1w00jJ-0006o6-0Q; Tue, 10 Mar 2026 17:18:49 +0000 Received: by outflank-mailman (output) from mailman id 1250580.1548089; Tue, 10 Mar 2026 17:18:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00jI-0006nv-Sf; Tue, 10 Mar 2026 17:18:48 +0000 Received: by outflank-mailman (input) for mailman id 1250580; Tue, 10 Mar 2026 17:18:47 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00aP-0001QA-Ad for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:37 +0000 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [2a00:1450:4864:20::332]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id e9cd1f6e-1ca3-11f1-9ccf-f158ae23cfc8; Tue, 10 Mar 2026 18:09:35 +0100 (CET) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-48534e9076fso20624205e9.0 for ; Tue, 10 Mar 2026 10:09:35 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. 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Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/domain.c | 3 +++ xen/arch/riscv/include/asm/intc.h | 4 ++++ xen/arch/riscv/intc.c | 40 +++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 560b21b16ffb..1c08ba7396ea 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -300,6 +300,9 @@ int arch_domain_create(struct domain *d, if ( (rc =3D p2m_init(d)) !=3D 0) goto fail; =20 + if ( (rc =3D domain_vintc_init(d)) ) + goto fail; + d->arch.next_phandle =3D GUEST_PHANDLE_LAST + 1; =20 return rc; diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm= /intc.h index 45d41e191e30..fb4188b96a75 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -13,6 +13,7 @@ enum intc_version { }; =20 struct cpu_user_regs; +struct domain; struct dt_device_node; struct irq_desc; struct kernel_info; @@ -96,4 +97,7 @@ void intc_handle_external_irqs(struct cpu_user_regs *regs= ); =20 int intc_make_domu_dt_node(const struct kernel_info *kinfo); =20 +int domain_vintc_init(struct domain *d); +void domain_vintc_deinit(struct domain *d); + #endif /* ASM__RISCV__INTERRUPT_CONTOLLER_H */ diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c index a91dbc5e997c..88ce658a4de0 100644 --- a/xen/arch/riscv/intc.c +++ b/xen/arch/riscv/intc.c @@ -11,6 +11,7 @@ =20 #include #include +#include =20 static const struct intc_hw_operations *__ro_after_init intc_hw_ops; =20 @@ -87,3 +88,42 @@ int map_device_irqs_to_domain(struct domain *d, struct d= t_device_node *dev, return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapp= ing, irq_ranges); } + +int __init domain_vintc_init(struct domain *d) +{ + int ret =3D -EOPNOTSUPP; + const enum intc_version ver =3D intc_hw_ops->info->hw_version; + + switch ( ver ) + { + case INTC_APLIC: + ret =3D domain_vaplic_init(d); + break; + + default: + printk("vintc (ver:%d) isn't implemented\n", ver); + break; + } + + if ( !ret ) + d->arch.vintc->info =3D intc_hw_ops->info; + + return ret; +} + +void __init domain_vintc_deinit(struct domain *d) +{ + const enum intc_version ver =3D intc_hw_ops->info->hw_version; + + switch ( ver ) + { + case INTC_APLIC: + domain_vaplic_deinit(d); + break; + + default: + printk("vintc (ver:%d) isn't implemented\n", ver); + break; + } + +} --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773163108; cv=none; d=zohomail.com; s=zohoarc; b=SQY7DKM6f+MA1cT5fz3shwSdpKscfeRXNLNzPAFLD4syOvNqiY6u5i03C7sECINXc/eeFB+mANvJmcJ8G1W7lrmKDouJSoxfyPI5VRZZ6k/UAg9Wv7xlET81gcmNSv7RocXK7iFpRw7Jhwci4pK1Ptq9IB2Am3mWZDc6OLObb9E= ARC-Message-Signature: i=1; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:35 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ea6f992a-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162576; x=1773767376; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yJVP2CNX14UgxmTAWNMtAQ5gdpc3OGAi5Vg/Vni1k8k=; b=gLgGsN8SmUSsWitN/PB72s1+nqVMlU3K4dhUR7Y0ngWHxHby5cakYuynZMNdvMXGYz qoOmFWXtorZE/9IJyvBzNk6vTtyCkRmkjlMPX19A5Jk1UIFeWLBmCGXh6zJ+MKtJJty9 lvmKGn4/ZYKLXDgQwsi7WHmy373b8H9+G4LiuH5PmTdfLSjJNfJKa5o3td7f+B/AVlmq SjMDkOtlR/W40ht91XOjZIEa+lI3E5AKTjUf2Wcfagb1MHoxpryG1lEUMarZTWfTz7r+ hIfUDMuJTxZbHPeTePlegX419LD1lIYHawBTaIvOw7PpD+IPSsSWIZDqgDSO5/b55wlL 9Hqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162576; x=1773767376; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=yJVP2CNX14UgxmTAWNMtAQ5gdpc3OGAi5Vg/Vni1k8k=; b=PI0WoY1KdrYkmC94pZmdh8B4TmZswHwtcDXjGs2tT2BgQdEnp2pLjpi11JikqWdYiT gEaQUjz0OQQwxDHaMGDA2gd3/Frai2v6snROZtOFQ6N7iCXEoAO/sdDOPTPUWZyfIYa5 5aRB/btThnExKpsHseyvBXQxwoWbLK35rolV7SP3gO0nR+cFBZfk8OsN/8wEsotWNCx4 kkMd4ppUigRGE/eGGp2zqlcNYmurZ6yKgVw9aLA+ro+Qfj16OKGsVWA9ezAD4nIAra5/ kFG9TSMiK/954VVi1S4FBTrytLS+By2FPPPQAJ9fXNvcgmC3TSs0W3h3z6A+MkZ/mHeP SoHQ== X-Gm-Message-State: AOJu0Yz8gMkYhuzA5lxjyzLBarABcYRWq+0g2LI+919IzFr1ZSL9VdZo Y82NJUZVyiwtlapKY4p+J+NsnARpbMFg/1cbvxCjF8AlOwbYTNgcLZs72Qmfnmtc X-Gm-Gg: ATEYQzzutfvmvGRD+M8AIosLcyxvDo11ODD2zPcWQfhAQzEF8QNKI4ZgreR9STffxtB r2rcyjedaOqT70a2y7f6tB1L2oo0O5R/GAhJxa0w18QolZEB6mk+3MoRjuhFdFnoT9CBsVjSUNC 7PA6tSxvoofrg7XmbyxXd5ZZ4SpUQm196pbm3hwxfj662me1bweRYmlvzJn/UIDGqg3c5h8wXm1 I9RRRJfclDTOBwkv5QWehrz11PKS47E3bkqlsCBZrfpcLH39EvBoJhR3uMOsefSxwUEc11fTZ1k meP5boI4XwsJa4wRsTpEQBcK7ERmwD4mX41Zf+WntgbYROBk9o6zmbE12oSjek2MsGqZGF9LWqJ ODmd5Ky/5D4VElxQALrHbQp6TqDRyR+fPXwJ2Uyjb2uTUx2R8NIApyKNbYX+ze+AW5wLryVgvkr ar6wRq+h09NKlN2gySZ+t6gJ6hm055yd57YTrm/UfUrdv89coiuFbNi+tcZ4UWFwEyQRP0SrqbK ZHfPqAS X-Received: by 2002:a05:600c:6306:b0:485:40ed:2d1 with SMTP id 5b1f17b1804b1-48540ed03fdmr88457825e9.17.1773162575630; Tue, 10 Mar 2026 10:09:35 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 22/27] xen/riscv: implement init_intc_phandle() Date: Tue, 10 Mar 2026 18:08:55 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163111557154100 Content-Type: text/plain; charset="utf-8" Implement init_intc_phandle() to read phandle of interrupt controller node and save it in kernel->phandle_intc for the future usage during creation of guest interrupt controller node. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- xen/arch/riscv/dom0less-build.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/xen/arch/riscv/dom0less-build.c b/xen/arch/riscv/dom0less-buil= d.c index 312c5d7d4979..180d653e5780 100644 --- a/xen/arch/riscv/dom0less-build.c +++ b/xen/arch/riscv/dom0less-build.c @@ -2,9 +2,26 @@ =20 #include #include +#include =20 #include =20 +int __init init_intc_phandle(struct kernel_info *kinfo, const char *name, + const int node_next, const void *pfdt) +{ + if ( dt_node_cmp(name, "intc") =3D=3D 0 ) + { + uint32_t phandle_intc =3D fdt_get_phandle(pfdt, node_next); + + if ( phandle_intc !=3D 0 ) + kinfo->phandle_intc =3D phandle_intc; + + return 0; + } + + return 1; +} + int __init make_intc_domU_node(struct kernel_info *kinfo) { intc_make_domu_dt_node(kinfo); --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773163130; cv=none; d=zohomail.com; s=zohoarc; b=lYm0u4s17V31sv9pFrWkO1BbDM/2Zmpuav7U+qPkBjMbBuTLuXXucVKdu5gVwwzuwtcheHX06FEbzyDjHEYFueHBBupezoAsdS7f74trU1XB3asGVKM9l0DJVghSAj8D4oLF24UYnt1x8QAAWM0ElMHx5OHquA0FPN1sI/FPrng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773163130; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JBHKAkfBQ+LZpxYmLsiOZkYEb81ClhJSsNte5UEhevw=; b=SbaF1VTh29uGb2AwXBgmFGFN44bCg9FN/Jbe7JvZHGKIt0MidTCtepcrO/YasjmxnuelxDt5CQZJv1D/dWeFexnMASPnbDxmfXGyA6wgS0hWWF0LmWFyhlxiDLnCXiYQ9M1CCc3LCC5cZZb0XEG4K1e7ZIL8LmWwylDjpLM/FgI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 17731631309665.759346870650916; Tue, 10 Mar 2026 10:18:50 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250563.1548043 (Exim 4.92) (envelope-from ) id 1w00j5-00059p-F0; Tue, 10 Mar 2026 17:18:35 +0000 Received: by outflank-mailman (output) from mailman id 1250563.1548043; Tue, 10 Mar 2026 17:18:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00j5-00059a-CJ; Tue, 10 Mar 2026 17:18:35 +0000 Received: by outflank-mailman (input) for mailman id 1250563; Tue, 10 Mar 2026 17:18:34 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00aR-0001Q4-ID for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:39 +0000 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [2a00:1450:4864:20::32a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id eb100563-1ca3-11f1-b164-2bf370ae4941; Tue, 10 Mar 2026 18:09:37 +0100 (CET) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4852f73d0a3so29542695e9.3 for ; Tue, 10 Mar 2026 10:09:37 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:36 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: eb100563-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162577; x=1773767377; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JBHKAkfBQ+LZpxYmLsiOZkYEb81ClhJSsNte5UEhevw=; b=lIVV+sTLdgY+AaZuM0+BqCxg+XStMGIxkMzhdbplTO5zEC8AztNxPsv4chN4AlXDzO DI/PuPQx3dsPZtBrZ42cTlS9G94bjzh4OiyG3FnN9YDMmfWNTpolqClDjwo7TSpdBB+n Q8wymBlu72N5+JOVa1hO7j7HDpuh0h/lI60SbJtwEZGc/2IPwRMotk6EfsLsX6wa3V8v wDUyNpnX+FUCETLIgJY3/jHnAqgEGtuS++ywcPeSo0SQUI6gMAaolv87G8fGMGmAWbZB 93V/1ovnbdPm0vBFFMFM2iRphhdRXGbFQ/sGy4wonxr1fRoRunTG9ZVqNMuujXbltmGA gZpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162577; x=1773767377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=JBHKAkfBQ+LZpxYmLsiOZkYEb81ClhJSsNte5UEhevw=; b=ReV6POYmX6o4Ple0r2H2GKgi5lDMHzUXQoYfT2stxDkwW5mh3q+pIL8ZilUPqL+k3+ if3ss7bQ/3t4PzHWF37JjKi4HuygL32zpqmXpm9X5+XUprXvwOR4yhucsuP/Pzf2krZV kJQCFIwsCEX8+0rSZeOl/grkoBOz8z+j74fGjj3oYdl2RXFMbX4JFeQVavu4+Y3CgxQu iiAIBCnK6wBqSAloQPLDBfPluUA0rU3YhiWQ43p5hD3VIggZMy/KOajZsVrVG61nbclZ R7g1VCjMEAk7xqDwMjSe1cr7UjSD1VqeP6qnUFAhnYPCx5fIyJSOgpnYN6veeAZq78nP XNuQ== X-Gm-Message-State: AOJu0YxfkjqFWGm7XoQc8a78SVswlV0nwqCS9rlrrol+a2J/HQgTqw1s R16jMZmaCNebr126sdyO/7YlbMc3JeeXT9A6J8JbEhjXd8xglhhGvn0nIV8CCG5T X-Gm-Gg: ATEYQzzOAW7304OWTZ3rGPay/e8MQjPBkOWN36j6tAlp4BpF0HIyvgenN0KGQU2C0ZW nYZXx6xmwC80TcJu4edLUdFRzY4o0FqFOX5efzRia3fnLbEoCGBfhehBZDNetg8KhwdGlq4apKc 5GCEwjVJEsNqDBK94qh2KopIJqYUYT/aunOprN1F0lTl4nbOaRQj6pp1zvTPjTvC3MRMR5qubKW HKVFWH77zYwSjUjPNYxzEesSsV9F0xuwTun2CN8amMLIWPLdkiFiPC05f/fUIkqe61VOTn/gtW9 sWqGZKEu3Waj+z7o6PeJcHyV+xd9dp0S/uBuD4ITnkQnqrEAJOx6T9uDNLAg3s9pRI417lDdhHZ Ropirk5h8GM+0l42lwE5m+VSTddBG0ao0Lmq59oXCFpIWVK0dMk0rr6ybW8boIyG5A9uzFyOEXh kV7DhDAXIWGd4swJlFEuXQsKXjHaBOk0QRAipyxyAeNSEYjWTPzJUHuP3UcgglQlrc64O9fo1mz ksF9J6C X-Received: by 2002:a05:600c:c086:b0:485:3f1c:d897 with SMTP id 5b1f17b1804b1-4853f1cd9d1mr91902945e9.9.1773162576726; Tue, 10 Mar 2026 10:09:36 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 23/27] xen/riscv: call do_initcalls() in start_xen() Date: Tue, 10 Mar 2026 18:08:56 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163134002154100 Content-Type: text/plain; charset="utf-8" Execute initcall function. Additionally, before do_initcalls() call scheduler_init() which is needed because of cpupool_create_pool() is called by do_initcalls(); otherwise BUG_ON(IS_ERR(pool)) will occur in inside cpupool_create_pool(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- xen/arch/riscv/setup.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index cae49bb29626..24bad0c606a5 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -159,6 +160,11 @@ void __init noreturn start_xen(unsigned long bootcpu_i= d, =20 guest_mm_init(); =20 + scheduler_init(); + set_current(idle_vcpu[0]); + + do_initcalls(); + printk("All set up\n"); =20 machine_halt(); --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773163144; cv=none; d=zohomail.com; s=zohoarc; b=Mnjgr0Srm8Uui+Ypue7xPeMiAXXIddHauY78WCIgtuzPXigW9hydHLBJGAElba5iZRqTLLgnsqbHrja9caJ7BuREcNw6ZBhvHV2tFzj3VP1n9O0f/tomIr16gs0QIxqUkp4FY19K6kDfZO07ACjJYmQRBB7lKvl5/P4SnqbmM0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773163144; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JkvH963wjORCKzFpDWqD/iOnBC1tRJKt38ThB/X1OSI=; b=nnePOtUTW0Wpd6hw1JZSviMIDUVlj9AcqEnVQtzAf8iUhaZXQrGQfVAOe+QnqZXHWv3uVxAYqpCsEHjmFgCM94Fz55hH+NX+AfxrzvIjk+fpGPYH88srS1HFGFifDWpFS+ffINWxy5wqKheYBmuFornOEkh0OV6gmV0ZgUAgBoo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1773163144034592.0725959646703; Tue, 10 Mar 2026 10:19:04 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250576.1548081 (Exim 4.92) (envelope-from ) id 1w00jG-0006UA-Kc; Tue, 10 Mar 2026 17:18:46 +0000 Received: by outflank-mailman (output) from mailman id 1250576.1548081; Tue, 10 Mar 2026 17:18:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00jG-0006U3-FT; Tue, 10 Mar 2026 17:18:46 +0000 Received: by outflank-mailman (input) for mailman id 1250576; Tue, 10 Mar 2026 17:18:44 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00aS-0001QA-Ay for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:40 +0000 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [2a00:1450:4864:20::333]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id ebbdf6ba-1ca3-11f1-9ccf-f158ae23cfc8; Tue, 10 Mar 2026 18:09:38 +0100 (CET) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4852a9c6309so37126245e9.0 for ; Tue, 10 Mar 2026 10:09:38 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. 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Tue, 10 Mar 2026 10:09:37 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 24/27] xen/riscv: init rcu Date: Tue, 10 Mar 2026 18:08:57 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163145746158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 24bad0c606a5..3e337bf611fb 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -154,6 +155,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 timer_init(); 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Tue, 10 Mar 2026 10:09:38 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 25/27] xen/riscv: setup system domains Date: Tue, 10 Mar 2026 18:08:58 +0100 Message-ID: <4474cdb8e326c486a806e07d65ad6bdb9e7b9541.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163150221154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 3e337bf611fb..5bc34e41fe55 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -157,6 +158,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 rcu_init(); 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For full guesst console support it will better to have something similar to [1], thereby there is nothing specific should be done, at least, for now and init_vuart() is provided to make dom0less code buildable. [1] https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2602041533440.317= 5371@ubuntu-linux-20-04-desktop/ Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- xen/arch/riscv/dom0less-build.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/riscv/dom0less-build.c b/xen/arch/riscv/dom0less-buil= d.c index 180d653e5780..43c8bdc52300 100644 --- a/xen/arch/riscv/dom0less-build.c +++ b/xen/arch/riscv/dom0less-build.c @@ -6,6 +6,14 @@ =20 #include =20 +int __init init_vuart(struct domain *d, struct kernel_info *kinfo, + const struct dt_device_node *node) +{ + /* Nothing to do at the moment */ + + return 0; +} + int __init init_intc_phandle(struct kernel_info *kinfo, const char *name, const int node_next, const void *pfdt) { --=20 2.53.0 From nobody Wed Apr 8 02:48:30 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1773163128; cv=none; d=zohomail.com; s=zohoarc; b=DCEfT8h9JcU9WXlhDW2dKhCAWturhRc6UqLK+QAvwmQsPKJveLW611CJZdkB75bBvZzPrSGqejrwwWlQl0914/0jZAhrVbnEBEtzq0X60K6mUBWDkVo4FqytdDu1bAK6CknWhRn22vi5gEjqeOtSRcghe4Od/iBDnv0npGH5UJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773163128; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eS5sSCMJ+IJ1M5ORzLuoNMwjp7zPxai25z8WoDewGMs=; b=SbDRLd3Pz0OgTYpqrfKjuuG7AFvXLuCzJX6koaNRNaAC0RHWavF9x0CzbE6DGVmNTGLtC4DRfs2pV4VeXwiIyYUFizKEzcS4X5krX9hlepHv8mJlyDoKtUT1ctCfOlczUdh06UfwKUVtrHRZ8JMGG67P2PQceQux3jk9j5LT4WY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 177316312863252.871802893069; Tue, 10 Mar 2026 10:18:48 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1250565.1548053 (Exim 4.92) (envelope-from ) id 1w00j6-0005Nz-Os; Tue, 10 Mar 2026 17:18:36 +0000 Received: by outflank-mailman (output) from mailman id 1250565.1548053; Tue, 10 Mar 2026 17:18:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00j6-0005Nm-M2; Tue, 10 Mar 2026 17:18:36 +0000 Received: by outflank-mailman (input) for mailman id 1250565; Tue, 10 Mar 2026 17:18:34 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w00aW-0001Q4-J5 for xen-devel@lists.xenproject.org; Tue, 10 Mar 2026 17:09:44 +0000 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [2a00:1450:4864:20::330]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ede70159-1ca3-11f1-b164-2bf370ae4941; Tue, 10 Mar 2026 18:09:42 +0100 (CET) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4853510b4f3so41192225e9.0 for ; Tue, 10 Mar 2026 10:09:42 -0700 (PDT) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:41 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ede70159-1ca3-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162581; x=1773767381; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eS5sSCMJ+IJ1M5ORzLuoNMwjp7zPxai25z8WoDewGMs=; b=V6yZRalt6hfTpxVuBCuArsS79iZpCjhdoZ/pdpi3ir4s30PmTg4uVDZIb3Bdz0SKmK zQ0bPZCAb5S0UnZ8riWtkO6Lm9rEB5jzFI5R3L5EJxuvWaEvlUmsBpJmragGPpyKU8WZ m2MXTahbvFKhSeT6OOhkFaJAtz7LYuEmLN+61st8nbeXKI8iItQ/7ndN9EO3q/qf5Ysn jzl9f/jNc0MuRdtaU5NpIvYK8ypE93OIgz0Lg7hAhQn+gPFhO78t2qyzIvfWUFaejzWx sY0/LpZeASF9UO56c3tnMlZFp83qnk7TZlQjz8w0cuwyxjFUYDBx7v15c0MrveGUDRR+ JSiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162581; x=1773767381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=eS5sSCMJ+IJ1M5ORzLuoNMwjp7zPxai25z8WoDewGMs=; b=s6ypZ+rYGTliRaIJQywBJCpnFK1NaBmTpRN3jwRVuTbaO8E2dhJMPOMxA+QDNPljMy 5wiNpISxtQrshket458J3WwBbzqONP7IGIN6i1yTAut+sHL5DkVGwaHqm3nxc59e+ndc zCTlN1OS5PyvTaVuCGjCWDTvjmjeTXJ3C6gRFphjg0QdMOieyr6b2c7+UWNp+ubFHn8r 7du7pu7r7vRFgXyZygmOftWn7Bf5RvQ7SckGeXBCOaBegr85+SwuwxnyzWzKQJb5r54h /B3N/mDavKdPiATAwMAfeYAtkxgVoq4Mo6JrignLvM9YXsSyKBDdSW8MdgAI7amEykM2 DNGw== X-Gm-Message-State: AOJu0YwjVfrb6rnYvzki2Rw1pSfSmYKOoKdGoP6AEg4DpaqFvJPszUfQ WgP+mZ4sdnX3J2r1BkkwNv/wzDfDbSYDVlT3R7EvTwLRzKwdSj08+/u9rStKeqE/ X-Gm-Gg: ATEYQzwMo8kkiGOq1YIoWwv1Qi7XhNmu6sDVSpr8Gb6B32rV56VJu3g590ObJcWkaJ7 QPpDowvUT9eDPdrzP5Yd3G/X0qnQ/F1noZ6dCZ1Zb6BY0gIKdKO0LfHKIXvMhAU11yHmYjZ8y0W HWD4uUf4RMWVwsQG6FljNBqpcJeVnuu4pR0wGXSy5Z/oJ2nBxNroqL37NocBKpp9IR0cz7lwf/T eX5baAMOxQXu+SUHFez9ioEUA1RbCr2JD7HIavV8krBRoM1bCajfSgfPqWFErvl/vM+pFOkuzu2 ToN65cMA1fcnmWMjQgjgGY7TkEzMGQ9L6maBQiD7yjZ32tjPiKcKhGQ+vTuN8KwCl6L4aK9d4KC nrKO+2ct272+G5PMidGPGGRVQDQs1t1F1uGBMwcaHu/eUuqLTVZqXO6UhRihcgi0dI3Q0GlEgHf bmdMm3vB2AeB4tdXS3TSM8w5QuCeAGvLEfRcTrZFT0tlOFL+oFumzgHhFAEVS67ANtwbcvag== X-Received: by 2002:a05:600c:19ca:b0:485:3d43:7c9a with SMTP id 5b1f17b1804b1-4853d437d40mr110653125e9.25.1773162581377; Tue, 10 Mar 2026 10:09:41 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 27/27] xen/riscv: add initial dom0less infrastructure support Date: Tue, 10 Mar 2026 18:09:00 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773163129766158500 Content-Type: text/plain; charset="utf-8" Enable dom0less support for RISC-V by selecting HAS_DOM0LESS and providing the minimal architecture hooks required by the common dom0less infrastructure. Add stub implementations for architecture-specific helpers used when building domains from the device tree. These currently perform no additional work but allow the generic dom0less code to build and run on RISC-V. Introduce max_init_domid as a runtime variable rather than a constant so that it can be updated during dom0less domain creation. Provide missing helpers and definitions required by the domain construction code, including domain bitness helpers and the p2m_set_allocation() prototype. Additionally define the guest magic memory region in the public RISC-V interface. Signed-off-by: Oleksii Kurochko --- Open questions: - Move declaration of p2m_set_allocation() to xen/fdt-domain-build.h or xen/dom0less-build.h as it is used in common code of Dom0less and there is not too much sense in declaration of it for each arch which supports Dom0less. It could be ifdef-ed in common header as, at the momemnt, it is used only for Dom0less. - Shouldn't declaration/defintion of max_init_domid move to common code instead of having it for each architecture separately? If yes, then what would be the best place. --- --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/dom0less-build.c | 18 ++++++++++++++++++ xen/arch/riscv/domain-build.c | 13 +++++++++++++ xen/arch/riscv/include/asm/domain.h | 8 ++++++++ xen/arch/riscv/include/asm/p2m.h | 2 ++ xen/arch/riscv/include/asm/setup.h | 4 +++- xen/arch/riscv/setup.c | 2 ++ xen/include/public/arch-riscv.h | 3 +++ 8 files changed, 50 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 091510380949..abd579aa6a54 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -6,6 +6,7 @@ config RISCV select GENERIC_BUG_FRAME select GENERIC_UART_INIT select HAS_DEVICE_TREE_DISCOVERY + select HAS_DOM0LESS select HAS_PMAP select HAS_UBSAN select HAS_VMAP diff --git a/xen/arch/riscv/dom0less-build.c b/xen/arch/riscv/dom0less-buil= d.c index 43c8bdc52300..865311ec7037 100644 --- a/xen/arch/riscv/dom0less-build.c +++ b/xen/arch/riscv/dom0less-build.c @@ -43,3 +43,21 @@ int __init make_arch_nodes(struct kernel_info *kinfo) =20 return 0; } + +void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) +{ + /* Nothing to do */ +} + +int __init arch_parse_dom0less_node(struct dt_device_node *node, + struct boot_domain *bd) +{ + /* Nothing to do */ + return 0; +} + +int __init arch_handle_passthrough_prop(struct kernel_info *kinfo, + struct dt_device_node *node) +{ + return 0; +} diff --git a/xen/arch/riscv/domain-build.c b/xen/arch/riscv/domain-build.c index ae26faed09ed..20735f41d646 100644 --- a/xen/arch/riscv/domain-build.c +++ b/xen/arch/riscv/domain-build.c @@ -154,9 +154,22 @@ int __init make_cpus_node(const struct domain *d, void= *fdt) return res; } =20 +int __init construct_hwdom(struct kernel_info *kinfo, + const struct dt_device_node *node) +{ + return -EOPNOTSUPP; +} + int __init make_timer_node(const struct kernel_info *kinfo) { /* There is no need for timer node for RISC-V. */ =20 return 0; } + +int __init make_hypervisor_node(struct domain *d, + const struct kernel_info *kinfo, + int addrcells, int sizecells) +{ + return -EOPNOTSUPP; +} diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 21a3e6876f36..a8342ca7c5bf 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -20,6 +20,14 @@ struct hvm_domain uint64_t params[HVM_NR_PARAMS]; }; =20 +#ifdef CONFIG_RISCV_64 +#define is_32bit_domain(d) (0) +#define is_64bit_domain(d) (1) +#else +#define is_32bit_domain(d) (1) +#define is_64bit_domain(d) (0) +#endif + struct arch_vcpu_io { }; =20 diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/= p2m.h index 4441c0400b83..d97c8d13ef6b 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -259,6 +259,8 @@ void p2m_ctxt_switch_from(struct vcpu *p); void p2m_ctxt_switch_to(struct vcpu *n); void p2m_handle_vmenter(void); =20 +int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preemp= ted); + #endif /* ASM__RISCV__P2M_H */ =20 /* diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h index 1c23043f409f..2e3f8931d01b 100644 --- a/xen/arch/riscv/include/asm/setup.h +++ b/xen/arch/riscv/include/asm/setup.h @@ -5,11 +5,13 @@ =20 #include =20 +#include + struct domain; struct dt_device_node; struct rangeset; =20 -#define max_init_domid (0) +extern domid_t max_init_domid; =20 void setup_mm(void); =20 diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 5bc34e41fe55..513f94777f38 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -32,6 +32,8 @@ #include #include =20 +domid_t max_init_domid =3D 0; + /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); diff --git a/xen/include/public/arch-riscv.h b/xen/include/public/arch-risc= v.h index 91cee3096041..3c0c786c57ac 100644 --- a/xen/include/public/arch-riscv.h +++ b/xen/include/public/arch-riscv.h @@ -58,6 +58,9 @@ typedef uint64_t xen_ulong_t; #define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE } #define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE } =20 +#define GUEST_MAGIC_BASE xen_mk_ullong(0x39000000) +#define GUEST_MAGIC_SIZE xen_mk_ullong(0x01000000) + struct vcpu_guest_context { }; typedef struct vcpu_guest_context vcpu_guest_context_t; --=20 2.53.0