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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:40 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3c87ec6e-197a-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814821; x=1773419621; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CmbbmA8PgeTF4OMY1R9mkMVOPj+EWhxjWMhkhMqQixw=; b=mt6XOoSBpqL5RjnQGdAQcigJHrRF2kgeuKl1kMY1nKq2adZ4nI4MHD8DQma9xxve3y Jrs4UVCdZfFBwi275d2Zq2CBhglHblYmDRQxSOMR/9WbkpYitLp1XPk2SVh93AO8btX3 F4uCr77wt67dhNyO5oIPdmgGELQoa5xc7fqnVX9DlwdQpzuF++55gypKVMMm5VKrG8O0 /wot/Dk6AjO8lt6Ous9KxQNuaRA53AuLxyBwsL7t+KOSSlnLgYOCCgX4nKmnnALKOroN rg3XpSi/pMmwnVdarLHhiEkxhRYj0phnqHvLd2H0G7hkjT5xTxEdXLUoWxLDLYhVailz CnNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814821; x=1773419621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=CmbbmA8PgeTF4OMY1R9mkMVOPj+EWhxjWMhkhMqQixw=; b=qv1/AGNTx+r9gmJQYBIkb8u8FYGoC/sSeCr8JCy9zd9AYku3b3Eq1/Ke+dCyxhnU6X jKM8u6j5MqEBcAnnhV8Qki1qGpmGbd7CTBYVIeSF0mgK6RCId1OSnJx3DXSH2Ar9tr23 LN2k/J2qC0+XDglcdCB5RjWT9xjDFTxd9BWRaokeXj90YFADNi/rdPAGHl9wD+ZNyACW QRBzxjyS//L+BHD7uNaO6ezFWeIRYp/qXJZyPOgg+hOL8yukgVuCWm+5EiarlKDfJwtp e0qa416kuLq72jxk8SCsSBpaT0DOAk0EE6BDwr9bS+IGhXHeeBW+kjkeEvejp5581pcC Th8w== X-Gm-Message-State: AOJu0YzoFswGwjb+vOJXKacpXyf0kLcoVC8Gr9gJl3uIfHTCY4ijvhdr laE0N0neh8AKuLhhF2kuj1A6iyC0n01qbe2yNFMBsLRByUaM57g/Ni/OHuiglQ== X-Gm-Gg: ATEYQzxtB0P+cHXbMSF5ksOoiBkK1wU163U21kmRQw34f3MzATz34o9eAqLAqXGLDUG 7dnfoK9M7P1vjhAHbLVCG5Us5sxRKaWHwxcfY+y4nt+4sZrT+zRaSMUVUz7JgPE3u3ZwwCqAIxo 2FkmKonT2WabknwieQoexAwgGPboHlCKcfwnu+jBtG7w55aggSISV/2oDuN7ep1uHd1Iw29v8lx lr8hHA7FbNBcYeqA8HYZlZGMQjQ4Om5vlMkkAv7fNb1RFDxpZEzGmUs07KXl969vyPiMD4RW7Sh JwXW0wh9AnZqCYN8+el5uVjVGetheNBwd/fqpxAXNKpJiZRtjKfjo7ijrRBiXhVyEkQwxy/6MtY scyrWEWkqmTs//0nPuIFdbeyvfv7shbt4Pyy4zZOnoPDnytFN+CYavw5YWDt5HClWjz7aAHUmGD UI0/OaKFBCjYO9fR8pc5fUTX2orwDXkhUdUuHZwxuBLV0BHWBwoSbDmZsVODXwKLRMkgKF8AYrn 6m4 X-Received: by 2002:a05:6000:2313:b0:431:808:2d58 with SMTP id ffacd0b85a97d-439da8a147bmr5202646f8f.51.1772814820844; Fri, 06 Mar 2026 08:33:40 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v7 01/14] xen/riscv: detect and store supported hypervisor CSR bits at boot Date: Fri, 6 Mar 2026 17:33:18 +0100 Message-ID: <3201951150104f17593e16c7ba00ada51ac1e10f.1772814110.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814847571154100 Content-Type: text/plain; charset="utf-8" Some hypervisor CSRs expose optional functionality and may not implement all architectural bits. Writing unsupported bits can either be ignored or raise an exception depending on the platform. Detect the set of writable bits for selected hypervisor CSRs at boot and store the resulting masks for later use. This allows safely programming these CSRs during vCPU context switching and avoids relying on hardcoded architectural assumptions. Use csr_read()&csr_write() instead of csr_swap()+all ones mask as some CSR registers have WPRI fields which should be preserved during write operation. Also, ro_one struct is introduced to cover the cases when a bit in CSR register (at the momemnt, it is only hstateen0) may be r/o-one to have hypervisor view of register seen by guest correct. Masks are calculated at the moment only for hedeleg, henvcfg, hideleg, hstateen0 registers as only them are going to be used in the follow up patch. If the Smstateen extension is not implemented, hstateen0 cannot be read because the register is considered non-existent. Instructions that attempt to access a CSR that is not implemented or not visible in the current mode are reserved and will raise an illegal-instruction exception. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V7: - Use csr_read_set() in INIT_CSR_MASK() instead of csr_read()+csr_write(). - Add undef of INIT_CSR_MASK(). - Move local variable old above INIT_CSR_MASK(). - Introduce INIT_RO_ONE_MASK() to init csr_masks.ro_one.* fields. - Introduce defines for masks intead of constants. - Move old variable inside macros INIT_CSR_MASK() and INIT_RO_ONE_MASK(). --- Changes in V6: - Introduce sub-struct ro_one inside csr_masks to cover the case that hstateen0 could have read-only-one bits. - Refacotr init_csr_masks() to handle hstateen0 case when a bit is r/o-one and handle WPRI fields properly. - Update the commit message. --- Changes in V5: - Move everything related to csr_masks to domain.c and make it static. - Move declaration of old variable in init_csr_masks() inside INIT_CSR_MAS= K. - Use csr_swap() in INIT_CSR_MASK(). --- Changes in V4: - Move csr_masks defintion to domain.c. Make it static as at the moment it is going to be used only in domain.c. - Rename and refactor X macros inside init_csr_masks(). --- Changes in V3: - New patch. --- xen/arch/riscv/domain.c | 57 ++++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/setup.h | 2 ++ xen/arch/riscv/setup.c | 2 ++ 3 files changed, 61 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index b60320b90def..32974cb48929 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -2,9 +2,66 @@ =20 #include #include +#include #include #include =20 +#include +#include + +struct csr_masks { + register_t hedeleg; + register_t henvcfg; + register_t hideleg; + register_t hstateen0; + + struct { + register_t hstateen0; + } ro_one; +}; + +static struct csr_masks __ro_after_init csr_masks; + +#define HEDELEG_AVAIL_MASK ULONG_MAX +#define HIDELEG_AVAIL_MASK ULONG_MAX +#define HENVCFG_AVAIL_MASK _UL(0xE0000003000000FF) +#define HSTATEEN0_AVAIL_MASK _UL(0xDE00000000000007) + +void __init init_csr_masks(void) +{ + /* + * The mask specifies the bits that may be safely modified without + * causing side effects. + * + * For example, registers such as henvcfg or hstateen0 contain WPRI + * fields that must be preserved. Any write to the full register must + * therefore retain the original values of those fields. + */ +#define INIT_CSR_MASK(csr, field, mask) do { \ + register_t old =3D csr_read_set(CSR_##csr, mask); \ + csr_masks.field =3D csr_swap(CSR_##csr, old); \ + } while (0) + +#define INIT_RO_ONE_MASK(csr, field, mask) do { \ + register_t old =3D csr_read_clear(CSR_HSTATEEN0, mask); \ + csr_masks.ro_one.field =3D csr_swap(CSR_##csr, old) & mask; \ + } while (0) + + INIT_CSR_MASK(HEDELEG, hedeleg, HEDELEG_AVAIL_MASK); + INIT_CSR_MASK(HIDELEG, hideleg, HIDELEG_AVAIL_MASK); + + INIT_CSR_MASK(HENVCFG, henvcfg, HENVCFG_AVAIL_MASK); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + INIT_CSR_MASK(HSTATEEN0, hstateen0, HSTATEEN0_AVAIL_MASK); + INIT_RO_ONE_MASK(HSTATEEN0, hstateen0, HSTATEEN0_AVAIL_MASK); + } + +#undef INIT_CSR_MASK +#undef INIT_RO_ONE_MASK +} + static void continue_new_vcpu(struct vcpu *prev) { BUG_ON("unimplemented\n"); diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h index c9d69cdf5166..2215894cfbb1 100644 --- a/xen/arch/riscv/include/asm/setup.h +++ b/xen/arch/riscv/include/asm/setup.h @@ -11,6 +11,8 @@ void setup_mm(void); =20 void copy_from_paddr(void *dst, paddr_t paddr, unsigned long len); =20 +void init_csr_masks(void); + #endif /* ASM__RISCV__SETUP_H */ =20 /* diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 9b4835960d20..bca6ca09eddd 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -137,6 +137,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 riscv_fill_hwcap(); =20 + init_csr_masks(); + preinit_xen_time(); =20 intc_preinit(); --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814852; cv=none; d=zohomail.com; s=zohoarc; b=ftLpJwjiMscSj+wwlaNvIWXoqurBRkPGp2bxsEdPUuGJaKCx8LfIrQEM0DIP7oCC/Juu5N6+gWAtkG5JJDjpvSgD9MtGrDu2/RNsVXH7hoK72MeHdLUIPAoPeF//ozTt3w1Rwun84KNGs9kdPl9xmM8aagvpdFJnNBttkaz67e0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772814852; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CzQC2ov+xYcuBZPHbnymUYPvOXLbca5uUsTK8SmNRMc=; b=H9CAd6G2ZZSfG8SY5cN7F9czYNt98G22uoWez3K42hFqgPmMjtP35gRZ1K2DHFb2IN4ru7dGYd6B6o7V5m9fyetTeAVQ5DnGYjK5Nx3wGstgsiKlyu9tzFOl8Oi7IWu4LOSilJqhGnufOISZxO3mqKX1WluM7br87+/bv2u4ago= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772814852909412.2502674120134; Fri, 6 Mar 2026 08:34:12 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1247973.1546328 (Exim 4.92) (envelope-from ) id 1vyY7W-0003Rt-QB; Fri, 06 Mar 2026 16:33:46 +0000 Received: by outflank-mailman (output) from mailman id 1247973.1546328; Fri, 06 Mar 2026 16:33:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7W-0003Rm-NR; Fri, 06 Mar 2026 16:33:46 +0000 Received: by outflank-mailman (input) for mailman id 1247973; Fri, 06 Mar 2026 16:33:45 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7V-0003HN-BP for xen-devel@lists.xenproject.org; Fri, 06 Mar 2026 16:33:45 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 3d1f88e6-197a-11f1-9ccf-f158ae23cfc8; Fri, 06 Mar 2026 17:33:42 +0100 (CET) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-483703e4b08so92166675e9.1 for ; Fri, 06 Mar 2026 08:33:42 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:41 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3d1f88e6-197a-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814822; x=1773419622; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CzQC2ov+xYcuBZPHbnymUYPvOXLbca5uUsTK8SmNRMc=; b=ZFs5by6RhXhoDd7Xfev6/OC0yC/6Q+DO+L2wRqeSNMljxn9pBcPyWZ3kaJggx/ybUN RGr99E2GvVJJr/IXIwB5SzjvZ2taWxTquPhNcDwgvQPwS7POJOnDF6eNx9PZvexeJMS/ WppRZqcSgWbY08lr5kXh9jkuDYSbnOeRQ4rs3jgUQNHS6MwSS3Ao/oGc1iRLQEEBa9ry IRuuRKXAGLEEeNNX7/XPVAn++LVI7VtaXZjjHokf2xbR/hmdNGXP/kjBepM3Ci3R5F6L lzV6vw0zmYMSriHkH6+rQBWeu4UjfjJFzioHoLktjfD9fXg0ZUVTmYSZ/YBzmHWPxSJl avAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814822; x=1773419622; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=CzQC2ov+xYcuBZPHbnymUYPvOXLbca5uUsTK8SmNRMc=; b=P/OkvASnzkwwRbh5MeMOMZH5NPCw0bE6/WURsrXPAxsyqAy45DMdgRKUJH+Y/jaDt7 Qj8+eiJPNG+yIDfTbiKo98qe67Hm7MccSiNQvNBjoAeSuzEZFHV26rFQBEF+Aucvjxhr KI7Hr7olVCgi2XGDqBGmXVtFSsA4nyDilbY5c4jaRWPba/T0uyxdHEIpkgI6SDk8YKSI sdPTPXjDbS84RZx8N4Ijj65tBuf2il8G40GSA6dtRLYKdnq7JM5Zcwx+U3IypQxAolYW 78L1pN+ooddzdjE3yIBxyQaDq3m0mBTGnjPpR0epf6eEI9UZOfW3PPC4QsN9/ORdV8Gw Hs6w== X-Gm-Message-State: AOJu0YwAh7Uht4yBL1xM2Za9xhnqOPZtg+IWN7XCUTe2vqZFAQB78p4Q IvBoteCLbkaIZFfUzruSt8yYGblSaAKPIOj2putkimAl04cewBYcKUuv3MVTTA== X-Gm-Gg: ATEYQzwFPLwX8YOfeY7onVC4mEVA5s+T1eccOTWry15snnHsDnR7hdrwM3/poLgEwbK euEq0zrSQGZ3hozr/SAWW2VoYjXu4fvLGIuCmOjRPqbshkAJ6x3lsVZgF8qnLx3DfJEO+4mHYxe VSoe8QUvb/nkJu13j+GPnPDjSOctT2hvOE0qeB9HGUu+S43AcZjpMCzSRrlSf4JbRd4rw5Ypwev bbUO87XD3tuWaNmF7D5T8ayjemDaeFalmS47Z5FLbAZuwGqorodfM2DAfX4BYLhMDY/YlkXDbJB lf4SaZpqksgFv6TGJ5klmi4TZp8s7s9Uy5xwk9WwSZeuG/EWupsTK4aoywNY8mCAKuTsLf2xt6O vG+nyv60HfmXNDOjESWJQjXEol/aekRtCtDKk4yyW9QfonAkZ0Y4r5cLguAGowr/3nJQzR4VCoO EVunaf13fhqvbAC7mc6GF7XWrrIvuMMqhs6ZIMd6yKl0BjeWKtkuk7s5JaYsop4S07UpOnyQ== X-Received: by 2002:a05:600c:154b:b0:47d:6c36:a125 with SMTP id 5b1f17b1804b1-4852675edf7mr40929495e9.17.1772814821883; Fri, 06 Mar 2026 08:33:41 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v7 02/14] xen/riscv: implement vcpu_csr_init() Date: Fri, 6 Mar 2026 17:33:19 +0100 Message-ID: <91724a0d6f2d2de3979a1a7d1f92da11ffd06171.1772814110.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814855699154100 Content-Type: text/plain; charset="utf-8" Introduce vcpu_csr_init() to initialise hypervisor CSRs that control vCPU execution and virtualization behaviour before the vCPU is first scheduled. The function configures trap and interrupt delegation to VS-mode by setting the appropriate bits in the hedeleg and hideleg registers, initializes hstatus so that execution enters VS-mode when control is passed to the guest, and restricts guest access to hardware performance counters by initializing hcounteren, as unrestricted access would require additional handling in Xen. When the Smstateen and SSAIA extensions are available, access to AIA CSRs and IMSIC guest interrupt files is enabled by setting the corresponding bits in hstateen0, avoiding unnecessary traps into Xen (note that SVSLCT(Supervisor Virtual Select) name is used intead of CSRIND as OpenSBI uses such name and riscv_encoding.h is mostly based on it). If the Svpbmt extension is supported, the PBMTE bit is set in henvcfg to allow its use for VS-stage address translation. Guest access to the ENVCFG CSR is also enabled by setting ENVCFG bit in hstateen0, as a guest may need to control certain characteristics of the U-mode (VU-mode when V=3D1) execution environment. For CSRs that may contain read-only bits (e.g. hedeleg, hideleg, hstateen0), to the written value a correspondent mask is applied to avoid divergence between the software state and the actual CSR contents. As hstatus is not part of struct arch_vcpu (it already resides in struct cpu_user_regs), introduce vcpu_guest_cpu_user_regs() to provide a uniform way to access hstatus and other guest CPU user registers. This establishes a consistent and well-defined initial CSR state for vCPUs prior to their first context switch. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V7: - Add Acked-by: Jan Beulich . --- Changes in V6: - Apply introduced in prev. patch csr_masks.ro_one.hstaten0 in vcpu_csr_in= it(). --- Changes in v5: - Initialize of hstateen0 with SMSTATEEN0_HSENVCFG when a variable is defined. - Use |=3D for a code inside if (*_ssaia) case. - Put declaration of the registers hedeleg and hideleg together in arch_vc= pu structure as they are typically used together so better chances to be in the same cache line. --- Changes in v4: - Move local variable hstateen0 into narrower scope. - Code style fixes. - Move the call of vcpu_csr_init(v) after if ( is_idle_vcpu() ) check in arcg_vcpu_create(). --- Changes in v3: - Add hypervisor register used to initalize vCPU state. - Apply masks introduced before instead of csr_write()/csr_read() pattern. --- Changes in v2: - As hstatus isn't a part of arch_vcpu structure (as it is already a part = of cpu_user_regs) introduce vcpu_guest_cpu_user_regs() to be able to access hstatus and other CPU user regs. - Sort hideleg bit setting by value. Drop a stray blank. - Drop | when the first initialization of hcounteren and hennvcfg happen. - Introduce HEDELEG_DEFAULT. Sort set bits by value and use BIT() macros instead of open-coding it. - Apply pattern csr_write() -> csr_read() for hedeleg and hideleg instead of direct bit setting in v->arch.h{i,e}deleg as it could be that for some reason some bits of hedeleg and hideleg are r/o. The similar patter is used for hstateen0 as some of the bits could be r/= o. - Add check that SSAIA is avaialable before setting of SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_SVSLCT bits. - Drop local variables hstatus, hideleg and hedeleg as they aren't used anymore. --- xen/arch/riscv/domain.c | 63 +++++++++++++++++++++ xen/arch/riscv/include/asm/current.h | 2 + xen/arch/riscv/include/asm/domain.h | 6 ++ xen/arch/riscv/include/asm/riscv_encoding.h | 2 + 4 files changed, 73 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 32974cb48929..08b990f7b9f6 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 struct csr_masks { register_t hedeleg; @@ -20,6 +21,21 @@ struct csr_masks { } ro_one; }; =20 +#define HEDELEG_DEFAULT (BIT(CAUSE_MISALIGNED_FETCH, U) | \ + BIT(CAUSE_FETCH_ACCESS, U) | \ + BIT(CAUSE_ILLEGAL_INSTRUCTION, U) | \ + BIT(CAUSE_BREAKPOINT, U) | \ + BIT(CAUSE_MISALIGNED_LOAD, U) | \ + BIT(CAUSE_LOAD_ACCESS, U) | \ + BIT(CAUSE_MISALIGNED_STORE, U) | \ + BIT(CAUSE_STORE_ACCESS, U) | \ + BIT(CAUSE_USER_ECALL, U) | \ + BIT(CAUSE_FETCH_PAGE_FAULT, U) | \ + BIT(CAUSE_LOAD_PAGE_FAULT, U) | \ + BIT(CAUSE_STORE_PAGE_FAULT, U)) + +#define HIDELEG_DEFAULT (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) + static struct csr_masks __ro_after_init csr_masks; =20 #define HEDELEG_AVAIL_MASK ULONG_MAX @@ -62,6 +78,51 @@ void __init init_csr_masks(void) #undef INIT_RO_ONE_MASK } =20 +static void vcpu_csr_init(struct vcpu *v) +{ + v->arch.hedeleg =3D HEDELEG_DEFAULT & csr_masks.hedeleg; + + vcpu_guest_cpu_user_regs(v)->hstatus =3D HSTATUS_SPV | HSTATUS_SPVP; + + v->arch.hideleg =3D HIDELEG_DEFAULT & csr_masks.hideleg; + + /* + * VS should access only the time counter directly. + * Everything else should trap. + */ + v->arch.hcounteren =3D HCOUNTEREN_TM; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) ) + v->arch.henvcfg =3D ENVCFG_PBMTE & csr_masks.henvcfg; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + /* Allow guest to access CSR_SENVCFG */ + register_t hstateen0 =3D SMSTATEEN0_HSENVCFG; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) + /* + * If the hypervisor extension is implemented, the same three + * bits are defined also in hypervisor CSR hstateen0 but conce= rn + * only the state potentially accessible to a virtual machine + * executing in privilege modes VS and VU: + * bit 60 CSRs siselect and sireg (really vsiselect and + * vsireg) + * bit 59 CSRs siph and sieh (RV32 only) and stopi (really + * vsiph, vsieh, and vstopi) + * bit 58 all state of IMSIC guest interrupt files, inclu= ding + * CSR stopei (really vstopei) + * If one of these bits is zero in hstateen0, and the same bit= is + * one in mstateen0, then an attempt to access the correspondi= ng + * state from VS or VU-mode raises a virtual instruction excep= tion. + */ + hstateen0 |=3D SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_= SVSLCT; + + v->arch.hstateen0 =3D (hstateen0 & csr_masks.hstateen0) | + csr_masks.ro_one.hstateen0; + } +} + static void continue_new_vcpu(struct vcpu *prev) { BUG_ON("unimplemented\n"); @@ -84,6 +145,8 @@ int arch_vcpu_create(struct vcpu *v) if ( is_idle_vcpu(v) ) return 0; =20 + vcpu_csr_init(v); + /* * As the vtimer and interrupt controller (IC) are not yet implemented, * return an error. diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 58c9f1506b7c..5fbee8182caa 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -48,6 +48,8 @@ DECLARE_PER_CPU(struct vcpu *, curr_vcpu); #define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu) =20 #define guest_cpu_user_regs() ({ BUG_ON("unimplemented"); NULL; }) +#define vcpu_guest_cpu_user_regs(vcpu) \ + (&(vcpu)->arch.cpu_info->guest_cpu_user_regs) =20 #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 5aec627a7adb..17be792afe7d 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -49,6 +49,12 @@ struct arch_vcpu { =20 struct cpu_info *cpu_info; =20 + register_t hcounteren; + register_t hedeleg; + register_t hideleg; + register_t henvcfg; + register_t hstateen0; + register_t vsatp; }; =20 diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index 1f7e612366f8..dd15731a86fa 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -228,6 +228,8 @@ #define ENVCFG_CBIE_INV _UL(0x3) #define ENVCFG_FIOM _UL(0x1) =20 +#define HCOUNTEREN_TM BIT(1, U) + /* =3D=3D=3D=3D=3D User-level CSRs =3D=3D=3D=3D=3D */ =20 /* User Trap Setup (N-extension) */ --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Note that smp_wmb() is used instead of smp_mb__before_atomic() as what we want to guarantee that if a bit in irqs_pending_mask is obversable that the correspondent bit in irqs_pending is observable too. Add lockless tracking of pending vCPU interrupts using atomic bitops. Two bitmaps are introduced: - irqs_pending =E2=80=94 interrupts currently pending for the vCPU - irqs_pending_mask =E2=80=94 bits that have changed in irqs_pending The design follows a multi-producer, single-consumer model, where the consumer is the vCPU itself. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg(). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. On RISC-V interrupts are not injected via guest registers, so pending interrupts must be recorded in irqs_pending (using the new vcpu_{un}set_interrupt() helpers) and flushed to the guest by updating HVIP before returning control to the guest. The consumer side is implemented in a follow-up patch. A barrier between updating irqs_pending and setting the corresponding mask bit in vcpu_set_interrupt()/vcpu_unset_interrupt() guarantees that if the consumer observes a mask bit set, the corresponding pending bit is also visible. This prevents missed interrupts during the flush. It is possible that a guest could have pending bit in the hardware register without being marked pending in irq_pending bitmap as: According to the RISC-V ISA specification: Bits hip.VSSIP and hie.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in hip is an alias (writable) of the same bit in hvip. Additionally: When bit 2 of hideleg is zero, vsip.SSIP and vsie.SSIE are read-only zeros. Else, vsip.SSIP and vsie.SSIE are aliases of hip.VSSIP and hie.VSSIE. This means the guest may modify vsip.SSIP, which implicitly updates hip.VSSIP and the bit being written with 1 would also trigger an interrupt as according to the RISC-V spec: These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in sip, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including sip, sie and sstatus). What means that IRQ_VS_SOFT must be synchronized separately, what is done in vcpu_sync_interrupts(). Note, also, that IRQ_PMU_OVF would want to be synced for the similar reason as IRQ_VS_SOFT, but isn't sync-ed now as PMU isn't supported now. For the remaining VS-level interrupt types (IRQ_VS_TIMER and IRQ_VS_EXT), the specification states they cannot be modified by the guest and are read-only because of: Bits hip.VSEIP and hie.VSEIE are the interrupt-pending and interrupt-enab= le bits for VS-level external interrupts. VSEIP is read-only in hip, and is the logical-OR of these interrupt sources: =E2=80=A2 bit VSEIP of hvip; =E2=80=A2 the bit of hgeip selected by hstatus.VGEIN; and =E2=80=A2 any other platform-specific external interrupt signal directe= d to VS-level. Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enab= le bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and any other platform-specific timer interrupt signal directed to VS-level. and When bit 10 of hideleg is zero, vsip.SEIP and vsie.SEIE are read-only zer= os. Else, vsip.SEIP and vsie.SEIE are aliases of hip.VSEIP and hie.VSEIE. When bit 6 of hideleg is zero, vsip.STIP and vsie.STIE are read-only zero= s. Else, vsip.STIP and vsie.STIE are aliases of hip.VSTIP and hie.VSTIE. and also, Bits sip.SEIP and sie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller. Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If implemented, STIP is read-only in sip, and is set and cleared by the execution environment Thus, for these interrupt types, it is sufficient to use vcpu_set_interrupt= () and vcpu_unset_interrupt(), and flush them during the call of vcpu_flush_interrupts() (which is introduced in follow up patch). vcpu_sync_interrupts(), which is called just before entering the VM, slightly bends the rule that the irqs_pending bit must be written first, followed by updating the corresponding bit in irqs_pending_mask. However, it still respects the core guarantee that the producer never clears the mask and only writes to irqs_pending if it is the one that flipped the corresponding mask bit from 0 to 1. Moreover, since the consumer won't run concurrently because vcpu_sync_interrupts() and the consumer path are going to be invoked sequentially immediately before VM entry, it is safe to slightly relax this ordering rule in vcpu_sync_interrupts(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v7: - Drop ifdef RV32 in vcpu_sync_interrupts(). It will be introduced later w= hen it will be more clear from the context why it is needed in this function. - Rename vcpu_sync_interrups()'s argument to curr and add ASSERT(curr =3D=3D current). --- Changes in v6: - Drop for the moment: /* Read current HVIP and VSIE CSRs */ v->arch.vsie =3D csr_read(CSR_VSIE); from vcpu_sync_interrupts() as it isn't used at the moment and will be introduced when a usage will be more clear. --- Changes in v5: - Update the commit message(). - Rename c to curr. - Update vcpu_set_interrupt() to use test_and_set_bit() for irqs_pending bitmask too. - Move #ifdef CONFIG_RISCV_32 above the comment in vcpu_sync_interrupts(). --- Changes in v4: - Update the commit message. - Update the comments in vcpu_(un)set_interrupt() and add the the comment above smp_wmb() barrier. - call vcpu_kick() only if the pending_mask bit going from 0 to 1. - Code style fixes. - Update defintion of RISCV_VCPU_NR_IRQS to cover potential RV128 case and the case if AIA isn't used. - latch current into a local variable in check_for_pcpu_work(). --- Changes in v3: - Use smp_wb() instead of smp_mb__before_atomic(). - Add explanation of the change above in the commit message. - Move vcpu_sync_interrupts() here to producers side. - Introduce check_for_pcpu_work() to be clear from where vcpu_sync_interru= pts() is called. --- Changes in V2: - Move the patch before an introduction of vtimer. - Drop bitmap_zero() of irqs_pending and irqs_pending_mask bitmaps as vcpu structure starts out all zeros. - Drop const for irq argument of vcpu_{un}set_interrupt(). - Drop check "irq < IRQ_LOCAL_MAX" in vcpu_{un}set_interrupt() as it could lead to overrun of irqs_pending and irqs_pending_mask bitmaps. - Drop IRQ_LOCAL_MAX as there is no usage for it now. --- xen/arch/riscv/domain.c | 63 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 22 ++++++++++ xen/arch/riscv/traps.c | 4 ++ 3 files changed, 89 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 08b990f7b9f6..5447c17402dd 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -6,6 +6,7 @@ #include #include =20 +#include #include #include #include @@ -168,6 +169,68 @@ void arch_vcpu_destroy(struct vcpu *v) vfree((void *)&v->arch.cpu_info[1] - STACK_SIZE); } =20 +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq) +{ + bool kick_vcpu; + + /* We only allow VS-mode software, timer, and external interrupts */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + kick_vcpu =3D !test_and_set_bit(irq, v->arch.irqs_pending); + + /* + * The counterpart of this barrier is the one encoded implicitly in xc= hg() + * which is used in consumer part (vcpu_flush_interrupts()). + */ + smp_wmb(); + + kick_vcpu |=3D !test_and_set_bit(irq, v->arch.irqs_pending_mask); + + if ( kick_vcpu ) + vcpu_kick(v); + + return 0; +} + +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq) +{ + /* We only allow VS-mode software, timer, external interrupts */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + clear_bit(irq, v->arch.irqs_pending); + /* + * The counterpart of this barrier is the one encoded implicitly in xc= hg() + * which is used in consumer part (vcpu_flush_interrupts()). + */ + smp_wmb(); + set_bit(irq, v->arch.irqs_pending_mask); + + return 0; +} + +void vcpu_sync_interrupts(struct vcpu *curr) +{ + unsigned long hvip =3D csr_read(CSR_HVIP); + + ASSERT(curr =3D=3D current); + + /* Sync-up HVIP.VSSIP bit changes done by Guest */ + if ( ((curr->arch.hvip ^ hvip) & BIT(IRQ_VS_SOFT, UL)) && + !test_and_set_bit(IRQ_VS_SOFT, &curr->arch.irqs_pending_mask) ) + { + if ( hvip & BIT(IRQ_VS_SOFT, UL) ) + set_bit(IRQ_VS_SOFT, &curr->arch.irqs_pending); + else + clear_bit(IRQ_VS_SOFT, &curr->arch.irqs_pending); + } +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 17be792afe7d..1ecfe18c8519 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -54,8 +54,25 @@ struct arch_vcpu { register_t hideleg; register_t henvcfg; register_t hstateen0; + register_t hvip; =20 register_t vsatp; + + /* + * VCPU interrupts + * + * We have a lockless approach for tracking pending VCPU interrupts + * implemented using atomic bitops. The irqs_pending bitmap represent + * pending interrupts whereas irqs_pending_mask represent bits changed + * in irqs_pending. Our approach is modeled around multiple producer + * and single consumer problem where the consumer is the VCPU itself. + * + * DECLARE_BITMAP() is needed here to support 64 vCPU local interrupts + * on RV32 host. + */ +#define RISCV_VCPU_NR_IRQS MAX(BITS_PER_LONG, 64) + DECLARE_BITMAP(irqs_pending, RISCV_VCPU_NR_IRQS); + DECLARE_BITMAP(irqs_pending_mask, RISCV_VCPU_NR_IRQS); }; =20 struct paging_domain { @@ -94,6 +111,11 @@ static inline void update_guest_memory_policy(struct vc= pu *v, =20 static inline void arch_vcpu_block(struct vcpu *v) {} =20 +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq); +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); + +void vcpu_sync_interrupts(struct vcpu *curr); + #endif /* ASM__RISCV__DOMAIN_H */ =20 /* diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 9fca941526f6..551f886e3a69 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -171,6 +171,10 @@ static void do_unexpected_trap(const struct cpu_user_r= egs *regs) =20 static void check_for_pcpu_work(void) { + struct vcpu *curr =3D current; + + vcpu_sync_interrupts(curr); + p2m_handle_vmenter(); } =20 --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814851; cv=none; d=zohomail.com; s=zohoarc; b=eiWDOkNmJ8+eGkwAnca3jE6lEU4XejpsZwkxyBlNgg6YT56s+EImNx/USIFBAbgbeHmC4HrL4JOl8oEDRwVLlglyKOQ1HoIhB//6JHx8te5C8XEP6t/8oS6yBWAynV4SG2iti9TQp33mM2JBZPfnMLYd0ZsGhuxBF3FB9Hbo+5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772814851; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TD32rUw8Jt+xF61vzNKRB9KoWMugslbXmkZ8IwQfvzs=; b=kIPnRlvv1fnwbfbWXLmAtaEvyVM3m1ME7FWt56V2YoRx/l/LpG/4SQQbUq/xdWppI2T+Oxwx5U19mSX8Cwelia2lb6FWsAnCq690CP1IZ53frjYS2TBXwpMrWXDP01oycQGhVqTukW1hrcHQ5N8Vf+BgiO5L+mPJJHguG40lUcE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772814851155111.71088648277373; Fri, 6 Mar 2026 08:34:11 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1247974.1546333 (Exim 4.92) (envelope-from ) id 1vyY7X-0003VQ-4P; Fri, 06 Mar 2026 16:33:47 +0000 Received: by outflank-mailman (output) from mailman id 1247974.1546333; Fri, 06 Mar 2026 16:33:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7W-0003Uq-V5; Fri, 06 Mar 2026 16:33:46 +0000 Received: by outflank-mailman (input) for mailman id 1247974; Fri, 06 Mar 2026 16:33:45 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7V-00030j-JG for xen-devel@lists.xenproject.org; Fri, 06 Mar 2026 16:33:45 +0000 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [2a00:1450:4864:20::435]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 3e69eeb1-197a-11f1-b164-2bf370ae4941; Fri, 06 Mar 2026 17:33:45 +0100 (CET) Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-439b94a19fdso5418564f8f.0 for ; Fri, 06 Mar 2026 08:33:45 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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Add the consumer side (vcpu_flush_interrupts()) of the lockless pending interrupt tracking introduced in part 1 (for producers). According, to the design only one consumer is possible, and it is vCPU itself. vcpu_flush_interrupts() is expected to be ran (as guests aren't ran now due to the lack of functionality) before the hypervisor returns control to the guest. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg() (with aquire semantics). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. The worst thing which could happen with such approach is that a new pending bit will be set to irqs_pending bitmap during update of hvip variable in vcpu_flush_interrupt() but it isn't problem as the new pending bit won't be lost and just be proceded during the next flush. As AIA specs introduced hviph register which would want to be updated when guest related AIA code vcpu_update_hvip() is introduced instead of just open-code it in vcpu_flush_interrupts(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v7: - Rename argument v of vcpu_flush_interrupts() to curr. - Add ASSERT(curr =3D=3D current) to be sure that this functions is called= only for current vCPU as the whole vcpu_flush_interrupts() implemented to wor= k=20 with current (at the moment, at least). - Drop vcpu_update_hvip() function and open code it in vcpu_flush_interrup= t() as there is no more update of hvip unconditionally and hviph will be updated separately. (originally it was planned to update unconditionally both hvip and hviph inside vcpu_update_hvip() after if() conditions in vcpu_flush_interrupt()) --- Changes in v6: - Nothing changed. Only rebase. --- Changes in v5: - Reorder the defintions of local variables (mask, val, hvip) in vcpu_flush_interrupts(). Also, drop a blank line between them. - Move #ifdef CONFIG_RISCV_32 above the comment in vcpu_flush_interrupts() and align the comment properly. - Add Acked-by: Jan Beulich . --- Changes in v4: - Move defintion of hvip local variable to narrower space in vcpu_flush_interrupts(). - Use initializers for mask and val variables. - Use local variable c as an argument of vcpu_flush_interrupts() in check_for_pcpu_work(). --- Changes in v3: - Update the error message in case of RV32 from "hviph" to v->arch.hviph. - Make const argument of vcpu_update_hvip. - Move local variables mask and val inside if() in vcpu_flush_interrupts(). - Call vcpu_flush_interrupts() in check_pcpu_work(). - Move vcpu_update_hvip() inside if() in vcpu_flush_interrupts(). --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 27 +++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/traps.c | 2 ++ 3 files changed, 30 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 5447c17402dd..f3e3ad149453 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -231,6 +231,33 @@ void vcpu_sync_interrupts(struct vcpu *curr) } } =20 +void vcpu_flush_interrupts(struct vcpu *curr) +{ + ASSERT(curr =3D=3D current); + + if ( ACCESS_ONCE(curr->arch.irqs_pending_mask[0]) ) + { + unsigned long mask =3D xchg(&curr->arch.irqs_pending_mask[0], 0UL); + unsigned long val =3D ACCESS_ONCE(curr->arch.irqs_pending[0]) & ma= sk; + register_t *hvip =3D &curr->arch.hvip; + + *hvip &=3D ~mask; + *hvip |=3D val; + + csr_write(CSR_HVIP, *hvip); + } + +#ifdef CONFIG_RISCV_32 + /* + * Flush AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't + * supported now. + */ +# error "Update v->arch.hviph" +#endif +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 1ecfe18c8519..59d23e4f9247 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -115,6 +115,7 @@ int vcpu_set_interrupt(struct vcpu *v, unsigned int irq= ); int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); =20 void vcpu_sync_interrupts(struct vcpu *curr); +void vcpu_flush_interrupts(struct vcpu *curr); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:44 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3f2fad62-197a-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814825; x=1773419625; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PUa+J5dx/g0jfCQXCa5GsS6lcARiceV/jkoJtxvsNwc=; b=FEJfwGK+82JNUSYtm7sbdmwEJsaLrGrJOldr4U9TjjZBc/IbW3KtDjxQdmaTA7KJU8 NzdwaWERTvYKWp8Y8eAFlTs2ZK/fSCI3mDDGkGfgMbuCNMnd4eiSWZxMP2Kb5yZmvNNV 8MPo89b5wZGYfl56oP0XFCTc3fDvgCEFtweCus5S1FQxkaYVtDQ8ZvG+/dQqeOU2ce1W 28LPfEU1bcmgANBQpcPSXdT412ZPs58huHRHSbHi4mSkdhhcx0uem20gerzf9U7JlGY8 I/7rrSbqlD755pWs+7iZHch5nGYR4xOap6tT8+JS7Us91ySAoR3a0WDe2rC2sYAR3zTG TNuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814825; x=1773419625; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=PUa+J5dx/g0jfCQXCa5GsS6lcARiceV/jkoJtxvsNwc=; b=Z6QOPQMsGUQfwTFVfotGfBbvJa/maJEl9Iy483ktG69nHXb1BcFXbmdsW9dGOSxyaV En17BBoF4U8NWOSFLo896X0AIZjNXCELcNcwJSye/Tv8ugbrT3mfQUB3T5kSbSESx2d5 p5fw68fIX2pBkc/m5qiZrJMb+bDWkDJqopIiWHHDCZldrdX05hr266dxlq/lyc1A+qXh iejuX8BWDyClHdqwidf7mnjp5zZEGJBeOK7OTYWCKzI7C335uCDn/D6QmD4RZ1PNh12r 3fe/xo7HaljEX28wHFbmEkiki/6CUhzi9dn1FGXF0394fUKSDU9t6celYuo6fK4c3Ai7 lZmA== X-Gm-Message-State: AOJu0YzZ6utrY3IClM0nINhNUwwmw4n1NDo1MkerSQpfIgn3IqAOHiMs PhpobhyEGf82VNqG+sXmtJ5S2wk4zZp2BtryX1FbXTl7QvHjQ9QyE/ckChPjAg== X-Gm-Gg: ATEYQzxJdu0QCB87WX9mhan8E5/pgCcvpwVvZ7Zvj9NOvkSWvpIfoWZMat1FjotI5iw W3ohdYfbqb6mA5wluowndGS2AcPX1Bzz527a/XiJJIyjuBqaWeA8ooDUZFAfho+Niilgki31VEw SE2euwW2WdA7WGYWm/H5Y2Z680braq47VisRrW9s/S115mskbR2RfWGMwfvS5V3tMNY1hGSWvgO nBypHyVH8SR7fJ7CRPH+4885WXviRahEjpJJKGm/Q6YPctdTjaCapKIbe9+wLkkYJqf1td1ucxh BmHnb1TaV2+ghd0rYcGHbds1JE8/IxPDbyJGI7DVP5DO1uGUUST4oIHM/6ZufsJnu8S6kymtxJY ubfvV9+lTHRHl9yOn/tc6ugeEbL537EDVmjUuawCi4OmJ4Yii9m0/JZUlwTGrrcIGJ/zRTYmPnV JsPduwWpJgnub7LH1Ks8KmnX4FYrmeakbXXY2dmicm5HsWDVJj8kRt1LR3xbAGa6k8AxruGg== X-Received: by 2002:a05:600c:198f:b0:483:6ff1:18b with SMTP id 5b1f17b1804b1-485268bd6cbmr46440355e9.0.1772814825032; Fri, 06 Mar 2026 08:33:45 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v7 05/14] xen/riscv: introduce basic vtimer infrastructure for guests Date: Fri, 6 Mar 2026 17:33:22 +0100 Message-ID: <1a5fcf53fa4a3e935b1814c129aa131fe1068168.1772814110.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814853140158500 Lay the groundwork for guest timer support by introducing a per-vCPU virtual timer backed by Xen=E2=80=99s common timer infrastructure. The virtual timer is programmed in response to the guest SBI sbi_set_timer() call and injects a virtual supervisor timer interrupt into the vCPU when it expires. While a dedicated struct vtimer is not strictly required at present, it is expected to become necessary once SSTC support is introduced. In particular, it will need to carry additional state such as whether SSTC is enabled, the next compare value (e.g. for the VSTIMECMP CSR) to be saved and restored across context switches, and time delta state (e.g. HTIMEDELTA) required for use cases such as migration. Introducing struct vtimer now avoids a later refactoring. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6-v7: - Nothing changed. Only rebase. --- Changes in v5: - Drop copyright line from asm/vtimer.h. - Add Acked-by: Jan Beulich . --- Changes in v4: - Add vcpu_timer_destroy() to void arch_vcpu_destroy(). --- Changes in v3: - use one container_of() to get vcpu instead of two container_of()s. --- Changes in v2: - Drop domain_vtimer_init() as it does nothing. - Drop "struct vcpu *v;" from struct vtimer as it could be taken from arch_vcpu using container_of(). - Drop vtimer_initialized, use t->status =3D=3D TIMER_STATUS_invalid instead to understand if timer was or wasn't initialized. - Drop inclusion of xen/domain.h as xen/sched.h already includes it. - s/ xen/time.h/ xen.timer.h in vtimer.c. - Drop ULL in if-conidtion in vtimer_set_timer() as with the cast it isn't necessary to have suffix ULL. - Add migrate timer to vtimer_set_timer() to be sure that vtimer will occur on pCPU it was ran, so the signalling to that vCPU will (commonly) be cheaper. - Check if the timeout has already expired and just inject the event in vtimer_vtimer_set_timer(). - Drop const for ticks argument of vtimer_set_timer(). - Merge two patches to one: - xen/riscv: introduce vtimer - xen/riscv: introduce vtimer_set_timer() and vtimer_expired() --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 10 +++- xen/arch/riscv/include/asm/domain.h | 3 ++ xen/arch/riscv/include/asm/vtimer.h | 17 +++++++ xen/arch/riscv/vtimer.c | 71 +++++++++++++++++++++++++++++ 5 files changed, 100 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/include/asm/vtimer.h create mode 100644 xen/arch/riscv/vtimer.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index bc47e83b26d7..ffbd7062e214 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -22,6 +22,7 @@ obj-y +=3D traps.o obj-y +=3D vmid.o obj-y +=3D vm_event.o obj-y +=3D vsbi/ +obj-y +=3D vtimer.o =20 $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index f3e3ad149453..b59e026a9635 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 struct csr_masks { register_t hedeleg; @@ -148,11 +149,14 @@ int arch_vcpu_create(struct vcpu *v) =20 vcpu_csr_init(v); =20 + if ( (rc =3D vcpu_vtimer_init(v)) ) + goto fail; + /* - * As the vtimer and interrupt controller (IC) are not yet implemented, + * As interrupt controller (IC) is not yet implemented, * return an error. * - * TODO: Drop this once the vtimer and IC are implemented. + * TODO: Drop this once IC is implemented. */ rc =3D -EOPNOTSUPP; goto fail; @@ -166,6 +170,8 @@ int arch_vcpu_create(struct vcpu *v) =20 void arch_vcpu_destroy(struct vcpu *v) { + vcpu_timer_destroy(v); + vfree((void *)&v->arch.cpu_info[1] - STACK_SIZE); } =20 diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 59d23e4f9247..6c48bf13111d 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -8,6 +8,7 @@ #include =20 #include +#include =20 struct vcpu_vmid { uint64_t generation; @@ -49,6 +50,8 @@ struct arch_vcpu { =20 struct cpu_info *cpu_info; =20 + struct vtimer vtimer; + register_t hcounteren; register_t hedeleg; register_t hideleg; diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h new file mode 100644 index 000000000000..111863610a92 --- /dev/null +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ASM__RISCV__VTIMER_H +#define ASM__RISCV__VTIMER_H + +#include + +struct vtimer { + struct timer timer; +}; + +int vcpu_vtimer_init(struct vcpu *v); +void vcpu_timer_destroy(struct vcpu *v); + +void vtimer_set_timer(struct vtimer *t, uint64_t ticks); + +#endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c new file mode 100644 index 000000000000..32d142bcdfcd --- /dev/null +++ b/xen/arch/riscv/vtimer.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +static void vtimer_expired(void *data) +{ + struct vtimer *t =3D data; + struct vcpu *v =3D container_of(t, struct vcpu, arch.vtimer); + + vcpu_set_interrupt(v, IRQ_VS_TIMER); +} + +int vcpu_vtimer_init(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + init_timer(&t->timer, vtimer_expired, t, v->processor); + + return 0; +} + +void vcpu_timer_destroy(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + if ( t->timer.status =3D=3D TIMER_STATUS_invalid ) + return; + + kill_timer(&v->arch.vtimer.timer); +} + +void vtimer_set_timer(struct vtimer *t, const uint64_t ticks) +{ + struct vcpu *v =3D container_of(t, struct vcpu, arch.vtimer); + s_time_t expires =3D ticks_to_ns(ticks - boot_clock_cycles); + + vcpu_unset_interrupt(v, IRQ_VS_TIMER); + + /* + * According to the RISC-V sbi spec: + * If the supervisor wishes to clear the timer interrupt without + * scheduling the next timer event, it can either request a timer + * interrupt infinitely far into the future (i.e., (uint64_t)-1), + * or it can instead mask the timer interrupt by clearing sie.STIE C= SR + * bit. + */ + if ( ticks =3D=3D ((uint64_t)~0) ) + { + stop_timer(&t->timer); + + return; + } + + if ( expires < NOW() ) + { + /* + * Simplify the logic if the timeout has already expired and just + * inject the event. + */ + stop_timer(&t->timer); + vcpu_set_interrupt(v, IRQ_VS_TIMER); + + return; + } + + migrate_timer(&t->timer, smp_processor_id()); + set_timer(&t->timer, expires); +} --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814858; cv=none; d=zohomail.com; s=zohoarc; b=Sb4L2o8MWu8Oo8fwjc9ZbJLRBYPCFgZVkVG5cnJDL5RCsT/fVb0ztt7tCu5c+nMSaS8qFD/cqfx6Z1d9dJPStASCspn2AdDz/EQ5W30D9+xahaXGV6YtX3cmwYPGPUz3ufvghaPTZks0nxkbVE8jBWXkv/CW0gs1wYyKSuIQn+4= ARC-Message-Signature: i=1; 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This mirrors the behavior of Arm and enables proper vCPU wakeup handling on RISC-V. Remove the stub implementation from stubs.c, as it is now provided by arch/riscv/domain.c. Since vcpu_kick() calls perfc_incr(vcpu_kick), add perfcounter for vcpu_kick to handle the case when CONFIG_PERF_COUNTERS=3Dy. Although CONFIG_PERF_COUNTERS is not enabled by default, it can be enabled, for example, by randconfig what will lead to CI build issues. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4-v7: - Nothing changed. Only rebase. --- Changes in v3: - Add asm/perfc_defn.h to provide vcpu_kick perfcoounter to cover the case when CONFIG_PERF_COUNTERS=3Dy. --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/domain.c | 14 ++++++++++++++ xen/arch/riscv/include/asm/Makefile | 1 - xen/arch/riscv/include/asm/perfc_defn.h | 3 +++ xen/arch/riscv/stubs.c | 5 ----- 4 files changed, 17 insertions(+), 6 deletions(-) create mode 100644 xen/arch/riscv/include/asm/perfc_defn.h diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index b59e026a9635..c8ce1efa884d 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include #include +#include #include =20 #include @@ -264,6 +266,18 @@ void vcpu_flush_interrupts(struct vcpu *curr) #endif } =20 +void vcpu_kick(struct vcpu *v) +{ + bool running =3D v->is_running; + + vcpu_unblock(v); + if ( running && v !=3D current ) + { + perfc_incr(vcpu_kick); + smp_send_event_check_mask(cpumask_of(v->processor)); + } +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/a= sm/Makefile index 3824f31c395c..86c56251d5d7 100644 --- a/xen/arch/riscv/include/asm/Makefile +++ b/xen/arch/riscv/include/asm/Makefile @@ -7,7 +7,6 @@ generic-y +=3D hypercall.h generic-y +=3D iocap.h generic-y +=3D irq-dt.h generic-y +=3D percpu.h -generic-y +=3D perfc_defn.h generic-y +=3D random.h generic-y +=3D softirq.h generic-y +=3D vm_event.h diff --git a/xen/arch/riscv/include/asm/perfc_defn.h b/xen/arch/riscv/inclu= de/asm/perfc_defn.h new file mode 100644 index 000000000000..8a4b945df662 --- /dev/null +++ b/xen/arch/riscv/include/asm/perfc_defn.h @@ -0,0 +1,3 @@ +/* This file is intended to be included multiple times. */ + +PERFCOUNTER(vcpu_kick, "vcpu: notify other vcpu") diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index daadff0138e4..eedf8bf9350a 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -203,11 +203,6 @@ void vcpu_block_unless_event_pending(struct vcpu *v) BUG_ON("unimplemented"); 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At present, vtimer_ctxt_switch_from() is a no-op because the RISC-V SSTC extension, which provides a virtualization-aware timer, is not yet supported. Xen therefore relies the virtual (SBI-based) timer. The virtual timer uses Xen's internal timer infrastructure and must be associated with the pCPU on which the vCPU is currently running so that timer events can be delivered efficiently. As a result, vtimer_ctxt_switch_= to() migrates the timer to the target pCPU when a vCPU is scheduled in. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4-v7: - Nothing changed. Only rebase. --- Changes in v3: - s/vtimer_ctx_switch_to/vtimer_ctxt_switch_to - s/vtimer_ctx_switch_from/vtimer_ctxt_switch_from - Add Acked-by: Jan Beulich . --- Changes in v2: - Align the parameters names for vtimer_ctx_switch_from() and vtimer_ctx_= switch_to() in declarations to match the ones in the defintions to make Misra happy. - s/vtimer_save/vtimer_ctx_switch_from. - s/vtimer_restore/vtimer_ctx_switch_to. - Update the commit message. --- xen/arch/riscv/include/asm/vtimer.h | 3 +++ xen/arch/riscv/vtimer.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h index 111863610a92..b4d48d1a1732 100644 --- a/xen/arch/riscv/include/asm/vtimer.h +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -14,4 +14,7 @@ void vcpu_timer_destroy(struct vcpu *v); =20 void vtimer_set_timer(struct vtimer *t, uint64_t ticks); =20 +void vtimer_ctxt_switch_from(struct vcpu *p); +void vtimer_ctxt_switch_to(struct vcpu *n); + #endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index 32d142bcdfcd..afd8a53a7387 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include =20 @@ -69,3 +70,17 @@ void vtimer_set_timer(struct vtimer *t, const uint64_t t= icks) migrate_timer(&t->timer, smp_processor_id()); set_timer(&t->timer, expires); } + +void vtimer_ctxt_switch_from(struct vcpu *p) +{ + ASSERT(!is_idle_vcpu(p)); + + /* Nothing to do at the moment as SSTC isn't supported now. */ +} + +void vtimer_ctxt_switch_to(struct vcpu *n) +{ + ASSERT(!is_idle_vcpu(n)); + + migrate_timer(&n->arch.vtimer.timer, n->processor); +} --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814854; cv=none; d=zohomail.com; s=zohoarc; b=KqIH9mbcr3UXyXbowQPrBB0qVBda2vXFqm8DYuEShJdU/xcQfTa4+8molTIFpt1YJdfNWkm0PF2ShD+Edd5hY4sa+whKBAqYOqcjEC9nUsBcUoIHoojzYKMqxVqJMXCK2UDYdTL1Men/YkSAjZjraDfd/pRG4xo2Y2WtmMHAUjs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772814854; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AFH/mmXdjfsZGFnjZSa+nYBoxFRy8PjJpaEBRZ8E9iE=; b=CfwXWl75070xWK2ObxTy4nZCmu6HY2xme5Mq6P9i2hl3sDXU9SWjo5b2bnCrFtb0pQIABE9AsyftJiVU9gU/30WHcc5PDRLItp76ZgBWJloMdnWtvcu6GGGgulIbCKXDpCXo3lr+ENnNHmvVSV6hAFfHpJe8WqaFM4viGJ+HMzM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772814854534675.0368522265397; Fri, 6 Mar 2026 08:34:14 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1247979.1546379 (Exim 4.92) (envelope-from ) id 1vyY7c-0004kV-4h; Fri, 06 Mar 2026 16:33:52 +0000 Received: by outflank-mailman (output) from mailman id 1247979.1546379; Fri, 06 Mar 2026 16:33:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7b-0004jR-S3; Fri, 06 Mar 2026 16:33:51 +0000 Received: by outflank-mailman (input) for mailman id 1247979; Fri, 06 Mar 2026 16:33:50 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7a-0003HN-Ky for xen-devel@lists.xenproject.org; Fri, 06 Mar 2026 16:33:50 +0000 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [2a00:1450:4864:20::434]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 40cb5aa9-197a-11f1-9ccf-f158ae23cfc8; Fri, 06 Mar 2026 17:33:49 +0100 (CET) Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-439b7c2788dso4198654f8f.1 for ; Fri, 06 Mar 2026 08:33:49 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:47 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 40cb5aa9-197a-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814828; x=1773419628; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AFH/mmXdjfsZGFnjZSa+nYBoxFRy8PjJpaEBRZ8E9iE=; b=mGyH7Ltb7HzT21mf4u7CIsGbzU3dLFfqETGZxzOcmwbN2DvFbZI7Uzt8DnkzFvRoO1 RHpCxOY3iooonWlzboWyr0uT7kj0iITxiCeS8547vuEfs6D8twvvL5+qbaWkrDKddftT 2bymNKy6xJvAl9W+mfNDeqkXQQt4A+8yCeL7jOO4IRvsR+gRw6pcoTTidtrXQZAgXlIb DALyIkqcUUAxbAO2OGDVCIILCq2CElw75kvCBKj/O9UyOIVhK5BgO5INmBec5rGExDAP LuVveeQohkjubaJeoEkPvBkhmECuBAshwcoUJdi5bKYyR4PGb3BuP53hhLmPAKsg7CNy 0YqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814828; x=1773419628; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=AFH/mmXdjfsZGFnjZSa+nYBoxFRy8PjJpaEBRZ8E9iE=; b=sDuSD2nQ7giepTdu0VEG7zNHmwUs3OUXLvSdT1zKS1sWTfF1Tu//dupja6CAu5ME5x M25koQy/3uzepG4TnJinCCz0HpddNnMpFEhjsUJPgDh1/i7HSUOsmPybYOf6QMcExVVJ bS+iKA9fNcrC0laMN5P4o4HufIJZ0/RdlnXvSTnVrHKlsak+vh0posnWOHE0nPssfhZb 4rX30UrggqQ3pxo5pVJVkhykgL4aOj0pqlkdqtZEvLWTs3WAE+KpBdyThB+ctqCMwR/+ 3ovFM63kG9+OY/nvOjUsBIKfd+UK94M23DKiqPVsIwch7L53B50cAC+jfhRQJZzZOpwt Qotg== X-Gm-Message-State: AOJu0YwY/LMAY87g8+4+Vl33Wd21d83AOZmGISBH2XRiaEpBkjgTnAiY iswxGRtvSBX+EyaT6+h+wAix3p2C/Wu2/wmFSOsP1nSePh7lX3OEe8ge428FOg== X-Gm-Gg: ATEYQzwhAeO6pTKSox6R8h4WekX8XQjzTbCNy0glT29rjqT510eInDyL00ztP0zBI5D R4BY9mL7OTXptc0gmwY7cGVQ1C7GTsVveGH8r2MUWDIHNq5NylL/xg48RHuEO2IRrSDlD+J8o0Y ebXlEv9S2b+Q3bDribKExQtGrz9AJf9AiykIwjp1GYLN9q4QZLjoP/Ggvuo8Q2rdX4nR1HmB9/Y 3au3yzwHZIqUMq4aqbxDs/s7zk6y6gtSmFcHpFZXZJYjM2cKcFzyn4tUzDaMYBjopk0r4JJfQeD evJeMZyfolOKet/znotbe2m0TjadjfxJMkYgG7U1VZkZMHILUHmAkWSNLpUQ1FGM9AFU2eQm6pq rmCJieqdy7HfSkNMY+9EQNCN2JscCZNuKLVv5WERYj7uqIzGVzGsaRX3ytjXYAQlQj+3ZGeQHDT RXzlMV9MTUezFMbZUHLLGY6009rAxtWqZW2aROWeT5exdZePY+NL1ZOz4vOEHxCJEphg+13DcW6 y+s X-Received: by 2002:a05:6000:2506:b0:439:aef4:944b with SMTP id ffacd0b85a97d-439da351a36mr4504521f8f.19.1772814828144; Fri, 06 Mar 2026 08:33:48 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v7 08/14] xen/riscv: implement SBI legacy SET_TIMER support for guests Date: Fri, 6 Mar 2026 17:33:25 +0100 Message-ID: <888b2d5a4a3ee9a83de4568b17253f865febaf9f.1772814110.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814858748154100 Add handling of the SBI_EXT_0_1_SET_TIMER function ID to the legacy extension ecall handler. The handler now programs the vCPU=E2=80=99s virtual timer via vtimer_set_timer() and returns SBI_SUCCESS. This enables guests using the legacy SBI timer interface to schedule timer events correctly. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3-v7: - Nothing changed. Only rebase. --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/vsbi/legacy-extension.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/riscv/vsbi/legacy-extension.c b/xen/arch/riscv/vsbi/l= egacy-extension.c index 2e8df191c295..090c23440cea 100644 --- a/xen/arch/riscv/vsbi/legacy-extension.c +++ b/xen/arch/riscv/vsbi/legacy-extension.c @@ -7,6 +7,7 @@ =20 #include #include +#include =20 static void vsbi_print_char(char c) { @@ -44,6 +45,11 @@ static int vsbi_legacy_ecall_handler(unsigned long eid, = unsigned long fid, ret =3D SBI_ERR_NOT_SUPPORTED; break; =20 + case SBI_EXT_0_1_SET_TIMER: + vtimer_set_timer(¤t->arch.vtimer, regs->a0); + regs->a0 =3D SBI_SUCCESS; + break; + default: /* * TODO: domain_crash() is acceptable here while things are still = under --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814860; cv=none; d=zohomail.com; s=zohoarc; b=J2jwR6c2BfrTcrjrDoJNfDe7AKoqEzrnXoOOlcVYU9Q7zplzhTQRwszViz9cIGWyDeL7FDSjFx7ul2ym4hOwkBd5tQ74xkVmzL3Dn53kIEKr5OWxGAuss9hfg2em7iApL34Kq9SHktWWIOTOG1a/GfSMFGEH/BdSy++qTqqFtQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772814860; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=J/Kmt/9cTJTTmvSy1vXRcQGyNeZ//R0WlMTYDIyos0A=; b=NvQ4KxKvQdjGFeiPDd+nM9LN13aOhOwAeI75GovmpX0a1uZZ6bIOVvsLXuesmWxe4NpWktxoNiILNtD62SUkltdZ0jLbg3kJmCitaAERAhKYjWbqN0QqMOk4YeMP268RxTj16NSGcGT05ygND/fgQ7E81EINljSgIisYdudc7uU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772814860259557.197478928626; Fri, 6 Mar 2026 08:34:20 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1247980.1546389 (Exim 4.92) (envelope-from ) id 1vyY7d-00055O-Er; Fri, 06 Mar 2026 16:33:53 +0000 Received: by outflank-mailman (output) from mailman id 1247980.1546389; Fri, 06 Mar 2026 16:33:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7d-000552-8E; Fri, 06 Mar 2026 16:33:53 +0000 Received: by outflank-mailman (input) for mailman id 1247980; Fri, 06 Mar 2026 16:33:50 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7a-00030j-Qb for xen-devel@lists.xenproject.org; Fri, 06 Mar 2026 16:33:50 +0000 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [2a00:1450:4864:20::330]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 41808ec9-197a-11f1-b164-2bf370ae4941; Fri, 06 Mar 2026 17:33:50 +0100 (CET) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-48371bb515eso139921555e9.1 for ; Fri, 06 Mar 2026 08:33:50 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:48 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 41808ec9-197a-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814829; x=1773419629; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J/Kmt/9cTJTTmvSy1vXRcQGyNeZ//R0WlMTYDIyos0A=; b=k5LthWAOiDzs4QDXyz8R2RdafHEnLGbO4ltENA1atSpq9PDh7R6/bSbg3sD0+V2e0b c9LcV2Iifint2NBg22744OQxjbqgSRb0UhGp9orQYFIquOtGaSVJ3hOK2gjzx4EvRYAN PCedSRQD0HdXRXeTDIdTrlxkpiHN4Rar+TXuJLZc3r3v6QViErPnluMZ7vjjgS6gnJo/ daeuim/GB2EAzTwWLwVffeAcrkw6rCrbVZFi6mg9tLXI5hV0LCGzShSkWal+KVv59hDv 43la/VlB5YjEbwSZw2lUxOYyd6W/vbfDWG9hEpCR15yP2SIYtyufH30BVFwbS4OH6Xl9 UtgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814829; x=1773419629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=J/Kmt/9cTJTTmvSy1vXRcQGyNeZ//R0WlMTYDIyos0A=; b=iAHNLl6X5g7qKW4apoygHjzG7wc/LKKU267XHxOtRGCI2HwP63Mt6m+SwYCrfB0+cC hNLNHhp8HJwOe/b0OeAMb7CCHjUPy06ZbeePjll4fdeB8bvwFdIVUu1VNyKNTRCMXB9p NAKXImQWKFRe9jwtHz46BWkdNv+N2BjVQ63b/z8qt8xlCMXfhYrUAKhknjKZ55yIe43b 62ZVNcev/yW1NX6Bz9CLSQK/XnVowcv63xWJLT+GB45IfTO9qUzOAFbaIfkboTJBzaLd mnwbreYIFb++awRwRwuOAfMjQipmk6tAwM7fNMKYihWF7xTisW6rAtUcG/s6r9zyz1l+ cN6g== X-Gm-Message-State: AOJu0YxB0cKG/ZuSK0gOQmzncVwsb2RwWLC6yIqH2ByhKrB7eP0lPZJA uXEUqzrooyptRrTON9Yqcjae1b4V7vvCziErfLYE0hc+fHdP6wL2/eI9Czxt1Q== X-Gm-Gg: ATEYQzwMGunL2mWqR/dIyeMug4sL+jX/9iSRA+9KCXPlEg3Qbjkv4PM4tDMMQxEbJGA p9Fu/FEoDfgc/w1iFJUL0t2po+YUh+LK7nmpjKHC3Jz7bzcyFEAdr+9zwz75D+mO4SO79XYzPgA FtkOwr7aSBVfWbzF3BtP+/wnzlzbisE36kynVovdu6tqkac1P1l8QtXQvD8CuSaMEfDhJvcUUFc MYXJRTMv7RfQjjLCGHS0s5kDq621LSKedxpy7GUUJpr7YH3xBRqcJjYLnHFYrT0q3o5j23cH9y0 OZEW0mhk54uRHHkgmfGo1hQmBjVd9XniHqhQr7FxiXj5jhuhe8fYzac9NM7XiBLx1Npfq9bqTiP tY79gd06R4k2S0gOVR87RU7JrwFyOzkNLv8mg4S4txkt+njgLsdrcDN9dQTb2tv/fXkbPZB5H+R VBKyAaPTzYY5xH12+tyCtUSQlWem3KR2WWMNofw6Wh3HBJF82Honihsr6QHvMBVIMkIQ== X-Received: by 2002:a05:600c:859a:b0:477:a36f:1a57 with SMTP id 5b1f17b1804b1-485269188cfmr33076975e9.3.1772814829291; Fri, 06 Mar 2026 08:33:49 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v7 09/14] xen/riscv: introduce sbi_set_timer() Date: Fri, 6 Mar 2026 17:33:26 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814861641154100 Introduce a function pointer for sbi_set_timer(), since different OpenSBI versions may implement the TIME extension with different extension IDs and/or function IDs. If the TIME extension is not available, fall back to the legacy timer mechanism. This is useful when Xen runs as a guest under another Xen, because the TIME extension is not currently virtualised and therefore will not appear as available. Despite of the fact that sbi_set_timer_v01 is introduced and used as fall back, SBI v0.1 still isn't fully supported (with the current SBI calls usage, sbi_rfence_v01 should be introduced too), so panic() in sbi_init() isn't removed. The sbi_set_timer() pointer will be used by reprogram_timer() to program Xen=E2=80=99s physical timer as without SSTC extension there is no any other option except SBI call to do that as only M-timer is available for us. Use dprintk() for all the cases to print that a speicifc SBI extension is available as it isn't really necessary in case of release builds. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6-v7: - Nothing changed. Only rebase. --- Changes in v5: - Add inclusion of to to deal with the compila= tion issue: ./arch/riscv/include/asm/sbi.h:156:30: error: expected ')' before 'sbi_= set_timer' 156 | extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value= ); - Rephrase the first sentence of the comment above declaration of sbi_set_t= imer pointer to function. --- Changes in v4: - Add "stime_value is in absolute time" to the comment above declaration of sbi_set_timer() function pointer. - Add Acked-by: Jan Beulich . --- Changes in v3: - Init sbi_set_timer with sbi_set_timer_v01 as fallback value. - Sort SBI IDs in the same way as SBI EXT IDs are declared. - Add __ro_after_init for sbi_set_timer variable. - use dprintk instead of printk to print information if SBI ext is availab= le. --- Changes in v2: - Move up defintion of SBI_EXT_TIME_SET_TIMER and use the same padding as defintions around it. - Add an extra comment about stime_value granuality above declaration of sbi_set_timer function pointer. - Refactor implemetation of sbi_set_timer_v02(). - Provide fallback for sbi_set_timer_v01(). - Update the commit message. --- xen/arch/riscv/include/asm/sbi.h | 22 ++++++++++++++++++ xen/arch/riscv/sbi.c | 40 +++++++++++++++++++++++++++++++- 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index 79f7ff5c5501..ed7af200288f 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -13,6 +13,7 @@ #define ASM__RISCV__SBI_H =20 #include +#include =20 /* SBI-defined implementation ID */ #define SBI_XEN_IMPID 7 @@ -29,6 +30,7 @@ =20 #define SBI_EXT_BASE 0x10 #define SBI_EXT_RFENCE 0x52464E43 +#define SBI_EXT_TIME 0x54494D45 =20 /* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 @@ -48,6 +50,9 @@ #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6 =20 +/* SBI function IDs for TIME extension */ +#define SBI_EXT_TIME_SET_TIMER 0x0 + #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f000000 #define SBI_SPEC_VERSION_MINOR_MASK 0x00ffffff =20 @@ -134,6 +139,23 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, = vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); =20 +/* + * Programs the clock for next event at (or after) stime_value. stime_valu= e is + * in absolute time. This function must clear the pending timer interrupt = bit + * as well. + * + * If the supervisor wishes to clear the timer interrupt without schedulin= g the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific nega= tive + * error code. + */ +extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); + /* * Initialize SBI library * diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index 425dce44c679..b4a7ae6940c1 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -249,6 +249,38 @@ static int (* __ro_after_init sbi_rfence)(unsigned lon= g fid, unsigned long arg4, unsigned long arg5); =20 +static int cf_check sbi_set_timer_v02(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +static int cf_check sbi_set_timer_v01(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) =3D sbi_set_ti= mer_v01; + int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -324,7 +356,13 @@ int __init sbi_init(void) if ( sbi_probe_extension(SBI_EXT_RFENCE) > 0 ) { sbi_rfence =3D sbi_rfence_v02; - printk("SBI v0.2 RFENCE extension detected\n"); + dprintk(XENLOG_INFO, "SBI v0.2 RFENCE extension detected\n"); + } + + if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) + { + sbi_set_timer =3D sbi_set_timer_v02; + dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:50 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 420cbc5c-197a-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814830; x=1773419630; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AYl+zWkW5xPd0n05ltjvtGI8d6PS/n+RbbF8iPoiaOQ=; b=mdj3j8LxlURwz5uvn8CZQ4am/ZnPlQHwmX/qxgvT0MDZfFRdOO9guZmt4qc2GfGmn3 4jjqh/8z4r5stplhNPwy5pUH0dn4LWd5Qe6Pwyjv8Im6m80wgSo85nCwVmIK7WPcRbGu IV4ILTUuDb3V/zTjKmveB0biwSD287taBdl2RAR7bhlIOfSowVsGIe5uRWNW5uOlikOI isUYGJ7Gv5zg3/njC3hmRUPcpH4wUkczQ2XC9KvP3wCyudWxOvTKVQ6mz1v2FIbkx9P0 TR7JPF1yAFAqVR9Qr+Za+M0K6lSESD9swCVv8JhtB9gAJZNjEXkKhDNlUcKX2rU5kD+A wGGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814830; x=1773419630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=AYl+zWkW5xPd0n05ltjvtGI8d6PS/n+RbbF8iPoiaOQ=; b=TMTdarz0wV044aTaUOgYyMhXO5wYtGey+J2ck+q6g06xKfRfla9n7qRz0GXfhTEj2u jAjF90P2LWioEXNeb7FfD5O1ge9ho0qNnu8WslLwMm/jLhUfxiEV1ja5nUunE3QHr9fb N6ZIcq1qK4cKVh+1XOEfHpnVgoiVhpiFURg4dPv1qT1Df8o1Y7won2pi9JjdRxflmCJ0 4RW3UP5jnLmFx+gUK0jGb0yPcT/cBmDeXbZfw+1EDIQd7Vnlm+ngW8Ycn0ftBIwTimTg XMQ5WqBXMlMyNdTc3r6hjSbfUWVpKZluT8f2D3+18J2gJKL3M6gtNFUicpLBi+MCWBr7 jV7w== X-Gm-Message-State: AOJu0Yy0E+fXhJwH8t35w8WHJOYH9hVGjNGVpeUdQtT/8XVAG/S8nJ03 h2ZqoScUgqy/MaTuwsaUqdBxJFxpUmzT25n9CyHSENUdOy+F6xpQb7JyPfrTKw== X-Gm-Gg: ATEYQzzX3RD6CQIKcx+J9ULCEslMYgQDHYNZulAmj1Xb4PD8SpdXThTPIhn/Qv3Cter lHLoPdnRWJTZgSAKv9WB6B99RKMB6mgu5TI4XaT119AeocwJYSKVKR58lPTBYCuWm+4seCJ0rsE 177FH6Gz+G845x7OYHKZx1mUiWalY9PIc9+OVwQ3WvJzrn2lMO3LAlihyKUXiIEKPxg6YfBtnYo sfhdeOcQ1gs19CLcfmyIPt3F92H4PZgc+rpkTEti4eAo+OH3lH2uKBFZbbqhvwP/n5xb8le26LY r5BFfxG7ik8bE+wmGYggyzEAN1dWynDJ+P6HpoLNIsSjVWBEGMtQYfTNcW6DFN0OckhK0ng9v3V 0Is1gMx7SuDkoFQj333UK0MHOkfOuRe20KPxoeHhxDO5BBmzxYpFumiojEK68PcrDMOIwDdWCUP GyzDu3Aj9N4pYMJk0qoV/XfdBIJLXRl+1KeVl4Si0LdTW91VA+Q6FT8iyWjmqTfkTInA== X-Received: by 2002:a05:600c:1e2a:b0:477:b642:9dc1 with SMTP id 5b1f17b1804b1-4852695819cmr44199145e9.20.1772814830199; Fri, 06 Mar 2026 08:33:50 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v7 10/14] xen/riscv: implement reprogram_timer() via SBI Date: Fri, 6 Mar 2026 17:33:27 +0100 Message-ID: <89884307fb74c534c0ed07afc1443aee4cab9a7b.1772814110.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814857004158500 Content-Type: text/plain; charset="utf-8" Implement reprogram_timer() on RISC-V using the standard SBI timer call. The privileged architecture only defines machine-mode timer interrupts (using mtime/mtimecmp). Therefore, timer services for S/HS/VS mode must be provided by M-mode via SBI calls. SSTC (Supervisor-mode Timer Control) is optional and is not supported on the boards available to me, so the only viable approach today is to program the timer through SBI. reprogram_timer() enables/disables the supervisor timer interrupt and programs the next timer deadline using sbi_set_timer(). If the SBI call fails, the code panics, because sbi_set_timer() is expected to return either 0 or -ENOSUPP (this has been stable from early OpenSBI versions to the latest ones). The SBI spec does not define a standard negative error code for this call, and without SSTC there is no alternative method to program the timer, so the SBI timer call must be available. reprogram_timer() currently returns int for compatibility with the existing prototype. While it might be cleaner to return bool, keeping the existing signature avoids premature changes in case sbi_set_timer() ever needs to return other values (based on which we could try to avoid panic-ing) in the future. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v5 - v7: - Nothing changed. Only rebase. --- Changes in v4: - Add Acked-by: Jan Beulich . --- Changes in v3: - Correct the comments in reprogram_timer(). - Move enablement of timer interrupt after sbi_set_timer() to avoid potentially receiving a timer interrupt between these 2 operations. --- Changes in v2: - Add TODO comment above sbi_set_timer() call. - Update the commit message. --- xen/arch/riscv/stubs.c | 5 ----- xen/arch/riscv/time.c | 43 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index eedf8bf9350a..2f3a0ce76af9 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -21,11 +21,6 @@ nodemask_t __read_mostly node_online_map =3D { { [0] =3D= 1UL } }; =20 /* time.c */ =20 -int reprogram_timer(s_time_t timeout) -{ - BUG_ON("unimplemented"); -} - void send_timer_event(struct vcpu *v) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 2c7af0a5d63b..7efa76fdbcb1 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,6 +7,9 @@ #include #include =20 +#include +#include + unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 @@ -40,6 +43,46 @@ static void __init preinit_dt_xen_time(void) cpu_khz =3D rate / 1000; } =20 +int reprogram_timer(s_time_t timeout) +{ + uint64_t deadline, now; + int rc; + + if ( timeout =3D=3D 0 ) + { + /* Disable timer interrupt */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; + } + + deadline =3D ns_to_ticks(timeout) + boot_clock_cycles; + now =3D get_cycles(); + if ( deadline <=3D now ) + return 0; + + /* + * TODO: When the SSTC extension is supported, it would be preferable = to + * use the supervisor timer registers directly here for better + * performance, since an SBI call and mode switch would no longer + * be required. + * + * This would also reduce reliance on a specific SBI implementat= ion. + * For example, it is not ideal to panic() if sbi_set_timer() re= turns + * a non-zero value. Currently it can return 0 or -ENOSUPP, and + * without SSTC we still need an implementation because only the + * M-mode timer is available, and it can only be programmed in + * M-mode. + */ + if ( (rc =3D sbi_set_timer(deadline)) ) + panic("%s: timer wasn't set because: %d\n", __func__, rc); + + /* Enable timer interrupt */ + csr_set(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; +} + void __init preinit_xen_time(void) { if ( acpi_disabled ) --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814859; cv=none; d=zohomail.com; s=zohoarc; b=Dpm7lgIejJSXVJuOvpK+YQGsrNEfmnRkvf0j9Ni80huUQ6cUxIlpqxVurMexsAH7obW4do6B67+JQ460HpbabrbnJcylpFlh2zp0DL4V2pqqOSG5mEPbhk9It2aRgW+70hEkDSAThAyqAxCBG8NNfsl4VcQpRLGQxi9qhnJXSLs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772814859; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sVTsKCN0wSfASIBvtQYg3brcx2aWUdWXZHC8J7YgVpo=; b=GpbHt1NwM/tNLWL/VSixKYC/AvsV+AY5Z01IwTcKcYzl9DqhFIuWs1n/h5+rfLZTn4YkHFgF2tWVsOXVaGwD4V3xaymQMUjp1NGmIPvSmU7L18CIytaqDFPxERsF/jaoyrls1IGMMV85HUoih/63QK0OIYXElR9AL67j6zio+jk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 17728148592781012.5753995710122; Fri, 6 Mar 2026 08:34:19 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1247983.1546408 (Exim 4.92) (envelope-from ) id 1vyY7g-0005mq-H2; Fri, 06 Mar 2026 16:33:56 +0000 Received: by outflank-mailman (output) from mailman id 1247983.1546408; Fri, 06 Mar 2026 16:33:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7g-0005mX-Dd; Fri, 06 Mar 2026 16:33:56 +0000 Received: by outflank-mailman (input) for mailman id 1247983; Fri, 06 Mar 2026 16:33:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7d-0003HN-Uh for xen-devel@lists.xenproject.org; Fri, 06 Mar 2026 16:33:53 +0000 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [2a00:1450:4864:20::32d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 42b2c3d4-197a-11f1-9ccf-f158ae23cfc8; Fri, 06 Mar 2026 17:33:52 +0100 (CET) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-483487335c2so79746765e9.2 for ; Fri, 06 Mar 2026 08:33:52 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:51 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 42b2c3d4-197a-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814831; x=1773419631; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sVTsKCN0wSfASIBvtQYg3brcx2aWUdWXZHC8J7YgVpo=; b=C5WD/ptislK0gk/27Z9QRkML3FdDH9WnR76RxuARrWdW9BkVUL1W+G496AY4PHITjV rGxEUSVFNJIIMV4Jj3AeXsXyFqcD3Lln91U5glcEL6bUvp+hghhmuyJK0PaV8zBs+PMx /hDjHyTUp27QtaxmmXxqHVFGnZjQaK6VgrgPHsEJ3HJ6G9WbSYD32FNW9L4PMnXIWTRZ dLYg6gfnIoxHFKTlS9lhBU5upN3cwUUq3A6Pok/Difg7yLhpB2S5afONx1gv7IExWfP1 kyOF+b5yO893iDOSuFFZ628rd3WwfzlpWAhd3mmCAtAPeO60JJfXZZS+O4Dkny5DCqY9 jdNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814831; x=1773419631; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sVTsKCN0wSfASIBvtQYg3brcx2aWUdWXZHC8J7YgVpo=; b=k0cC2sfWRJRZWL7XXwIdAD9S4lbUlb3aPscNrAHJGQak21YctGp2NrCteT6QbeHFMW kzriRWa0i1XTIF5IJMyN93SdboD5vCwoUillyxQt2RHYNADMerTxKPRDoMuK0BrRhhB+ Np16IRQP/KWLblHnAqQ6YfvlQ6FZBnRutDCrJcBjTovFf0Dl4CdPY8WXF70QVjUhIWDb lYURZs2RazVmxidNWTG+uwghYkcrdvsW8FaJtYY26qRvEkAtia1PPKP+zZeriBZjsl8P ZcMAr/ZjlRPC8crM/A9Kzixq/4/5WLzeqlhLbBwt0IV5dDJwiia9YJoGyBN4Va/pYtGT Q8xA== X-Gm-Message-State: AOJu0Yy+y7+rX4M9ielRib1c7QeaBJ46p9ihM6jrEZY8vptkP8Lo05ln AaNFWy9XTyFuQtl7QOd8NpIKYgK5Un4NyjOb4C0ZNIyC3wj0R2UlAyay0rVzuw== X-Gm-Gg: ATEYQzyyPYQqkglBhi6jlo/SuDolJ3v0RmAg5Z1dg+i/08HYUS4usGy0iIWKfy718WJ iNPPBl9eq5qi1xDLZiYTRNKPIMwa8F+53kG0ZSzN9t7jUiXREgdyi/nYhRK1/mjrnVxdqW7egJD TwcWJuYBZ45kNOIzNgVr6YB3rH7mENLqNC9sE3iKbaFjJ9t28IsdSyE8tQ+/Gb2tcqXzUcICQZU DUV0XBNeXCxApn/TMgQsMXO+Itg34/MvxpKHfGlycWb7kyC9beFUfruPuzgYtnh63Q4j9RtVvtQ S45ouGUZhwRMWyndUB10p527hcEMXGDF4lCVmV0fkMPii1Co4Pk1CJfmwt4YobUNdGZdsiFwiME Ti7iUMsHG5102zDseGUTkzJYlV5WTMRQih6Uml5aqsvQf8rYlAHLcX2LQB4EXMGL0Nxd1Tz47vG xvSDV9yicdsQ5j1u0CSeXDt4tW8WO1T/PAmFf0QDAqRo2Xg9snS8Gq8U3PxY+LTBPUIA== X-Received: by 2002:a05:600c:138a:b0:47e:e2eb:bc22 with SMTP id 5b1f17b1804b1-4852691c5bamr48041945e9.5.1772814831354; Fri, 06 Mar 2026 08:33:51 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v7 11/14] xen/riscv: handle hypervisor timer interrupts Date: Fri, 6 Mar 2026 17:33:28 +0100 Message-ID: <8a1b9279cf17fbe258af62c95377540c236b292e.1772814110.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814860922158500 Content-Type: text/plain; charset="utf-8" Introduce timer_interrupt() to process IRQ_S_TIMER interrupts. The handler disables further timer interrupts by clearing SIE.STIE and raises TIMER_SOFTIRQ so the generic timer subsystem can perform its processing. Update do_trap() to dispatch IRQ_S_TIMER to this new handler. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4-v7: - Nothing changed. Only rebase. --- Changes in v3: - add Acked-by: Jan Beulich . --- Changes in v2: - Drop cause argument of timer_interrupt() as it isn't used inside the function and anyway it is pretty clear what is the cause inside timer_interrupt(). --- xen/arch/riscv/traps.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 244264c92a79..326f2be62823 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include #include @@ -180,6 +181,15 @@ static void check_for_pcpu_work(void) p2m_handle_vmenter(); } =20 +static void timer_interrupt(void) +{ + /* Disable the timer to avoid more interrupts */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + /* Signal the generic timer code to do its work */ + raise_softirq(TIMER_SOFTIRQ); +} + void do_trap(struct cpu_user_regs *cpu_regs) { register_t pc =3D cpu_regs->sepc; @@ -221,6 +231,10 @@ void do_trap(struct cpu_user_regs *cpu_regs) intc_handle_external_irqs(cpu_regs); break; =20 + case IRQ_S_TIMER: + timer_interrupt(); + break; + default: intr_handled =3D false; break; --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814855; cv=none; d=zohomail.com; s=zohoarc; b=PCoNqfnPThpPBlmfigt0wZWkzrUaJxrklvA192LfWfN7fNU1OVQe2HKwFyLgwygNnrUxuayLPf1GMnC44AXc8BdCqDfPraKga49pYlOvuwPoRPTLXvM6nABbnK795K1HlA7nSBQOdXP20x9vMb0GgHZKM+XWWCahNhmk+H28BEY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772814855; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CHQw0iiSnYlgicKjMQWpmEGJyBczoqjDPyy2AZz+9Fw=; b=ZLsAKcTwcGFlJue+uhwUj+Rb7rpOl8oiMic2CcsHB/uUx1yyefGZ+mONjulm/Ur+vSEx0GtRSRkZ3JzB0NfAbvIdmwpCg+v3TCRPKANO5u8PlETmW6V6/gMeL8BwkuhtGWsPSgZ7hcFU/02DBKyQo9e2yLyuBd0iDVMRbBuEfOs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772814855292231.41623988402694; Fri, 6 Mar 2026 08:34:15 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1247984.1546415 (Exim 4.92) (envelope-from ) id 1vyY7h-0005qY-C6; Fri, 06 Mar 2026 16:33:57 +0000 Received: by outflank-mailman (output) from mailman id 1247984.1546415; Fri, 06 Mar 2026 16:33:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7g-0005pU-Tz; Fri, 06 Mar 2026 16:33:56 +0000 Received: by outflank-mailman (input) for mailman id 1247984; Fri, 06 Mar 2026 16:33:54 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7d-00030j-SR for xen-devel@lists.xenproject.org; Fri, 06 Mar 2026 16:33:53 +0000 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [2a00:1450:4864:20::431]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 4341cdb7-197a-11f1-b164-2bf370ae4941; Fri, 06 Mar 2026 17:33:53 +0100 (CET) Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-439cd6b0aedso1877979f8f.1 for ; Fri, 06 Mar 2026 08:33:53 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:52 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4341cdb7-197a-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814832; x=1773419632; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CHQw0iiSnYlgicKjMQWpmEGJyBczoqjDPyy2AZz+9Fw=; b=EzvjXlOBt+82hkUl0YrMvdyEsVAFxquwuHIV9uIUyb45VKS3Fg5VQvyeMLOuvbwTBy TfIrTGh0KEaTjmwi8kbQX6XoFA63NxhpX4cqrMLRMN3XtcqttyS3hNxCc5sXFJI5kiM8 2mMXAaMbOU4o4sQ71IjTqg159DSl9zRl1UCey9FwCW64JeJGPJipSPeCnC+ZSJcZ2YH2 5YcKyTtuwrbhhVwwhuW5iL95gkk1cFOcNSnrfy7/Cmvtm1jS029I8CB3+BcvkipyME7P L5Wc6BQU00uo58LLRve4n68cvDFwKYGxNPTriRjhoG0H/B8sjnhR6J8vvdmsFxteksFi UZaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814832; x=1773419632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=CHQw0iiSnYlgicKjMQWpmEGJyBczoqjDPyy2AZz+9Fw=; b=u1j9Uihsmz0p8AHQdm7qXCU+gYQu/DU7lp6TkUPKiF4mYtFVFvXsu3qGI8QBvlz/uj 2ZId7qGQSyjTSkfJEQ+RkSiPlEIkj/bSlzxBJuQYoGaPdJLoAX1fDHu5o28/o0TSECFG s79zGaUo9LPQKJ5qpKmWcnY6opiqDGZrzUus5ZiP3ZPRhXmwkuDsqntiuh1ov4qrUpJ1 6XyEJeBpzi5AQcVxkNh0Cgs0P0OoASqWKSaHI5GJ2oRyYGWmN1ywvYn0RxsINVt78oJf fqWGw2yMnqLN0nQHqTbmiaXpde4pWxUT98Mbsy5UUcvxmFzZTbg2jpmmVm6TzM7LSoBS qP4A== X-Gm-Message-State: AOJu0YytURpBvscRr4KgKDBjv5UpP18gLDpYpNeqUHTp95Ys3ClBbM5w AmpAlGTXkdUlVW7F8rylpZfa6JsZaTAazDsx/HiNbXIrrUKZbcU9WAv4bO1E6w== X-Gm-Gg: ATEYQzzDw/7qK0VVfYHQn/qwUn0Cwajn0tGtLat78vTbZdGs/yIIiZUvBYS67TKU4sS Fl46bi8plknDQPTA+841Hf0kmr7T4LYT9RC1LW2vOSJRj33Z2QD+wpiChWrUmci7nSP/Jf/O88L fmWC7fmuHI+Je4dDESVD+CanhJHz8zRutggOoC1DRNxtiFPimGeWtleIlJTFSAEUCvyh/quLzNr woOTVcn40ZAK9WlwdJvZQmMzMObwzSIYPt5VQsGhIVxAmRpeF+GWU9GO2BeoXeBcMnh09+JQodj tZHRCxM0F9lsYeXHln+N+lm8ujn0uN7+boZukI7WmLxX5k9oSc3UDRc8i5Z0EeFf002hVEZvGgc FBwkn1na9rRi//XOPBcSuaGETiuH+HAz+dIGNCIDro8rat1zbCXv+B9sKhzYljaPE0gp2qwQsws uY4arNPM8WFXx7gwBVc7L7GoyTYb5zI+Wm6IMV6f2zJbUq5eIK8BpwkBi/YGZsDqVymg== X-Received: by 2002:a05:6000:144a:b0:439:bc31:a04d with SMTP id ffacd0b85a97d-439da8941femr4925276f8f.41.1772814832338; Fri, 06 Mar 2026 08:33:52 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v7 12/14] xen/riscv: init tasklet subsystem Date: Fri, 6 Mar 2026 17:33:29 +0100 Message-ID: <0475cb50e04a48aedd730f2f0ab57381cc26d6ed.1772814110.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814856953158500 Content-Type: text/plain; charset="utf-8" As the tasklet subsystem is now initialized, it is necessary to implement sync_local_execstate(), since it is invoked when something calls tasklet_softirq_action(), which is registered in tasklet_subsys_init(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6-v7: - Nothing changed. Only rebase. --- Changes in v5: - It was something wrong with prev. rebase. So fix that and move removing of sync_local_execstate() and sync_vcpu_execstate() to the next patch. --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - add Acked-by: Jan Beulich . --- Changes in v2: - Update the commit message. - Move implementation of sync_vcpu_execstate() to separate commit as it doesn't connect to tasklet subsystem. --- xen/arch/riscv/setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index bca6ca09eddd..cae49bb29626 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -133,6 +134,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, panic("Booting using ACPI isn't supported\n"); } =20 + tasklet_subsys_init(); + init_IRQ(); =20 riscv_fill_hwcap(); --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814859; cv=none; d=zohomail.com; s=zohoarc; b=KSLErgjrTh1VzqKyK+Di6GUTcsmte9uTpWTcomLuk3mqeYlmyH3YfVRw5wGpsRpY4KmHD1yFXitgdNo8m9H1P7lqwmTFofDD2fFPKFUYK30prBT4v/2theUWNzlks0Sv7bHm0G8Uvia5Cqn/7Su49fTqett9kNfO6UVLfrFuOOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772814859; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cYzV7pV3IRuCnaF6MoayYG+rthZpT+FdfN6FzWyJXSQ=; b=CY5vLfs4HOYKO98loVCNPN2G4KRzAV3qjdUneR1AOPbmRXkQ4KGl8/syiGajj5AuwWnD5thbfSawTbSSteOpO77Ez7n1KgQ8mclgZTmEMXlWoP4lL9dX9Euf6Ny8Rq7bllNzuEu9o1S+wLe2HFkpJ2LsUzyeC6tehBuG0Gv8/Ao= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772814859174294.5008512217603; Fri, 6 Mar 2026 08:34:19 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1247986.1546418 (Exim 4.92) (envelope-from ) id 1vyY7i-0005zX-1J; Fri, 06 Mar 2026 16:33:58 +0000 Received: by outflank-mailman (output) from mailman id 1247986.1546418; Fri, 06 Mar 2026 16:33:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7h-0005vK-Ij; Fri, 06 Mar 2026 16:33:57 +0000 Received: by outflank-mailman (input) for mailman id 1247986; Fri, 06 Mar 2026 16:33:55 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7e-00030j-Uc for xen-devel@lists.xenproject.org; Fri, 06 Mar 2026 16:33:54 +0000 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [2a00:1450:4864:20::42e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 43d443d0-197a-11f1-b164-2bf370ae4941; Fri, 06 Mar 2026 17:33:54 +0100 (CET) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-439ce3605ecso1560842f8f.0 for ; Fri, 06 Mar 2026 08:33:54 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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RISC-V does not support lazy context switching, so nothing is done in sync_vcpu_execstate() and sync_local_execstate(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6-v7: - Nothing changed. Only rebase. --- Changes in v5: - It was something wrong with prev. rebase. Drop stubs for sync_local_execstate() and sync_vcpu_execstate() in this patch. --- Changes in v4: - Drop footer as [PATCH] sched: move vCPU exec state barriers is merged to upstream/staging. - Add Acked-by: Jan Beulich . --- Changes in v3: - Align sync_vcpu_execstate() with patch: [PATCH] sched: move vCPU exec state barriers --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 10 ++++++++++ xen/arch/riscv/stubs.c | 10 ---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index c8ce1efa884d..7e3070101714 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -278,6 +278,16 @@ void vcpu_kick(struct vcpu *v) } } =20 +void sync_local_execstate(void) +{ + /* Nothing to do -- no lazy switching */ +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + /* Nothing to do -- no lazy switching */ +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 2f3a0ce76af9..acbb5b9123ea 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -91,16 +91,6 @@ void continue_running(struct vcpu *same) BUG_ON("unimplemented"); } =20 -void sync_local_execstate(void) -{ - BUG_ON("unimplemented"); -} - -void sync_vcpu_execstate(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - void startup_cpu_idle_loop(void) { BUG_ON("unimplemented"); --=20 2.53.0 From nobody Mon Apr 13 01:55:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772814855; cv=none; d=zohomail.com; s=zohoarc; b=BBq7R7gju2R5ga4ZEpYCZCWFns3WXucEH1wLugUbNOMGRgOw8vCQ/EzmJHcu0Smx1EWRn2kBDSGUxUquteX7MJVusTajNbSrt07kaNfdk20nL0/laJAuN1h8mvOfbhqpMtsqxbD2GCxBs9WSRmAFPmoey8KFTAyGeJLK2mxpUNw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772814855; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qFpsHTy+iZE+ZlLI/wSoHNKAABJERus7tjJu21kZd2A=; b=LgvbV2Bv84iQ6+SybEztoMwbF6CtLGzTPcQH9vmvpCa4Xv1XTOSLL/jayAErGu3MOz0u8tKG7Da/rWhPt3LLjpM7YHDjTm+xc22AKDDM0/f7MGXFOwzwe4VCf50VwppL2jUBv6nnqJMCixzHSbaPs+9ujbOMUUHc39D8uQhxF0c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772814855431238.3310408578576; Fri, 6 Mar 2026 08:34:15 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1247988.1546430 (Exim 4.92) (envelope-from ) id 1vyY7j-0006Pb-Li; Fri, 06 Mar 2026 16:33:59 +0000 Received: by outflank-mailman (output) from mailman id 1247988.1546430; Fri, 06 Mar 2026 16:33:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7j-0006OI-9K; Fri, 06 Mar 2026 16:33:59 +0000 Received: by outflank-mailman (input) for mailman id 1247988; Fri, 06 Mar 2026 16:33:57 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vyY7h-0003HN-2Z for xen-devel@lists.xenproject.org; Fri, 06 Mar 2026 16:33:57 +0000 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [2a00:1450:4864:20::32c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 44742426-197a-11f1-9ccf-f158ae23cfc8; Fri, 06 Mar 2026 17:33:55 +0100 (CET) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-48371bb515eso139922685e9.1 for ; Fri, 06 Mar 2026 08:33:55 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae57c05sm4406550f8f.39.2026.03.06.08.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:33:53 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 44742426-197a-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772814834; x=1773419634; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qFpsHTy+iZE+ZlLI/wSoHNKAABJERus7tjJu21kZd2A=; b=c/VEaL7MKi7XawxZ031l/Wj7E2m8bIBAHYmP0SbEsYoR0Hjy9lr5nu57miDo+7uFJQ HzuZnvXQB7V7D1Ocic+fk+Ge8WGx36N8dVifHX7UAPP/xiR78fm4kEO3wkqEQbCJ2kNL CZThkYtnEtBe6ejK/uRtmKwnqZU5+OzAY+aTc0Q5x49qjbzkJzVoU1fbOSjStXrPvZ2C WAdjZjk/v17VibI6NCwzW44XABgbsi6KcY+dtyO6to3Or9Jqno47pf59t5VYybf7+K+t xnePYR/uPAASaOc5wDikjm6/3vWXNK39z8GTQJwglO2aIntilHPxP3GupSeOXOYBLb36 hBvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772814834; x=1773419634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=qFpsHTy+iZE+ZlLI/wSoHNKAABJERus7tjJu21kZd2A=; b=Mqu5wf0zrvB15s2yUVhHetipNZvORV5BLfK8lBfqpmvLmGCfFkYKT84KzollCs0x85 Z6sxYzlqbjeTsG8zeozxSn/gGIA+hBSWwaKpdrvYsPXZAh9fT6U3iJyRHDRI0rhkzp1L bLnP78OAjUyj7kS7uLToulsRe+eZmrHyowbZpHLBbq/3Gj5iCmisTTT54gAyj9AGi3ie ql7ccA6vbuAt9beDqcnNGFcjSen40q+VjIqr3msyCldDRx5LbClZ33hmSZQs3iDPLSO6 igHWofbV8hbOuPR0KhjIh09PpIHw4x3a+70lDHoAmETuS+1HQf6YXrMN5MnXnVvXwu6/ FQlw== X-Gm-Message-State: AOJu0YwfDU9MULWb1m4yh3WaFMIZzYtsvvE3i4BplAj8up/ZxStE8ufZ kcvpFWqtC36M+qysRJDbrEP/GwjaD3a6wactLmnqyE/ZcAQ1AXhFJfPjM2Fu6w== X-Gm-Gg: ATEYQzy3Zd5EGKrv+P2dTIPSwqOiqiWjCCFYn12EilJ7Fv+HtC0r5QA4hKCn22u58Ti Ye7OtGK4bvATWPIgbL1GU0U/5ZXmqLqt3AKkJXh0YkNH8AIc278I6hsZTKL4FsZsEkOuv07ECr8 zYv6HbKj6mBTpr3a+LBUIYVXIgI0k0bES2T0mNxvxOvpuIdpHxeYHbFSUeU8IenesuLtEt5uj/V FXNdf0EmwG8GzMr4oegpW7SOxZy2AjEoItaNC5w0W9YbiiNh56Lsi+v/4GbspixqzJrfce6YaSF hceFvo854xMidHb5EO0um4z58kDEAa0bZoxPiOuLPu2tAIBfT40WknS6DNTdRBjK/pLJsdFN+mV 99yE5iaooMqju8KQY5TYMe1IQZ/f99bAn/Ng05bWSoZB6BZDtLOpMo9qUza1RwOCX+4qiEhiOOQ vk+TYwhfeWVTCxUDnenkpYDjVc659rnwXvUhT4J7jhT+a+w7kIy9divUzr1VwA+1X58g== X-Received: by 2002:a05:600c:45c6:b0:483:c35d:3662 with SMTP id 5b1f17b1804b1-48526957c37mr42964395e9.18.1772814834067; Fri, 06 Mar 2026 08:33:54 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Doug Goldstein , Stefano Stabellini , Alistair Francis , Connor Davis , Jan Beulich Subject: [PATCH v7 14/14] xen/riscv: Disable SSTC extension and add trap-based CSR probing Date: Fri, 6 Mar 2026 17:33:31 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772814857599154100 Content-Type: text/plain; charset="utf-8" Some RISC-V platforms expose the SSTC extension, but its CSRs are not properly saved and restored by Xen. Using SSTC in Xen could therefore lead to unexpected behaviour. To avoid this in QEMU, disable SSTC by passing "sstc=3Doff". On real hardware, OpenSBI does not provide a mechanism to disable SSTC via the DTS (riscv,isa or similar property), as it does not rely on that property to determine extension availability. Instead, it directly probes the CSR_STIMECMP register. Introduce struct trap_info together with the do_expected_trap() handler to safely probe CSRs. The helper csr_read_allowed() attempts to read a CSR while catching traps, allowing Xen to detect whether the register is accessible. This mechanism is used at boot to verify SSTC support and panic if the CSR is not available. The trap handling infrastructure may also be reused for other cases where controlled trap handling is required (e.g. probing instructions such as HLV*). Also reorder header inclusion in asm-offsets.c to follow Xen coding style: should be included before headers as there is no any specific reason to remain the current order. Signed-off-by: Oleksii Kurochko --- Changes in v7: - new patch. IMO, it is okay to have this patch separetely as at the moment it won't = be an issue if Xen will use CSR_STIMECMP to setup its timer. The issue will start to occur when a guest will run. --- automation/scripts/qemu-smoke-riscv64.sh | 2 +- xen/arch/riscv/cpufeature.c | 8 ++++++ xen/arch/riscv/entry.S | 24 ++++++++++++++++++ xen/arch/riscv/include/asm/csr.h | 32 ++++++++++++++++++++++++ xen/arch/riscv/include/asm/traps.h | 7 ++++++ xen/arch/riscv/riscv64/asm-offsets.c | 7 +++++- 6 files changed, 78 insertions(+), 2 deletions(-) diff --git a/automation/scripts/qemu-smoke-riscv64.sh b/automation/scripts/= qemu-smoke-riscv64.sh index c0b1082a08fd..1909abb7af32 100755 --- a/automation/scripts/qemu-smoke-riscv64.sh +++ b/automation/scripts/qemu-smoke-riscv64.sh @@ -7,7 +7,7 @@ rm -f smoke.serial =20 export TEST_CMD=3D"qemu-system-riscv64 \ -M virt,aia=3Daplic-imsic \ - -cpu rv64,svpbmt=3Don \ + -cpu rv64,svpbmt=3Don,sstc=3Doff \ -smp 1 \ -nographic \ -m 2g \ diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 03e27b037be0..987d36dc7eee 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -17,6 +17,8 @@ #include =20 #include +#include +#include =20 #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -483,6 +485,7 @@ void __init riscv_fill_hwcap(void) unsigned int i; const size_t req_extns_amount =3D ARRAY_SIZE(required_extensions); bool all_extns_available =3D true; + struct trap_info trap; =20 riscv_fill_hwcap_from_isa_string(); =20 @@ -509,4 +512,9 @@ void __init riscv_fill_hwcap(void) if ( !all_extns_available ) panic("Look why the extensions above are needed in " "https://xenbits.xenproject.org/docs/unstable/misc/riscv/boo= ting.txt\n"); + + csr_read_allowed(CSR_STIMECMP, (unsigned long)&trap); + + if ( !trap.scause ) + panic("SSTC isn't supported\n"); } diff --git a/xen/arch/riscv/entry.S b/xen/arch/riscv/entry.S index 202a35fb03a8..b434948da3a4 100644 --- a/xen/arch/riscv/entry.S +++ b/xen/arch/riscv/entry.S @@ -99,3 +99,27 @@ restore_registers: =20 sret END(handle_trap) + + /* + * We assume that the faulting instruction is 4 bytes long and bli= ndly + * increment SEPC by 4. + * + * This should be safe because all places that may trigger this ha= ndler + * use ".option norvc" around the instruction that could cause the= trap, + * or the instruction is not available in the RVC instruction set. + * + * do_expected_trap(a3, a4): + * a3 <- pointer to struct trap_info + * a4 <- temporary register + */ +FUNC(do_expected_trap) + csrr a4, CSR_SEPC + REG_S a4, RISCV_TRAP_SEPC(a3) + csrr a4, CSR_SCAUSE + REG_S a4, RISCV_TRAP_SCAUSE(a3) + + csrr a4, CSR_SEPC + addi a4, a4, 4 + csrw CSR_SEPC, a4 + sret +END(do_expected_trap) diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/= csr.h index 01876f828981..b318cbdf35c3 100644 --- a/xen/arch/riscv/include/asm/csr.h +++ b/xen/arch/riscv/include/asm/csr.h @@ -9,6 +9,7 @@ #include #include #include +#include =20 #ifndef __ASSEMBLER__ =20 @@ -78,6 +79,37 @@ : "memory" ); \ }) =20 +/* + * Some functions inside asm/system.h requires some of the macros above, + * so this header should be included after the macros above are introduced. + */ +#include + +#define csr_read_allowed(csr_num, trap) \ +({ \ + register unsigned long tinfo asm("a3") =3D (unsigned long)trap; \ + register unsigned long ttmp asm("a4"); \ + register unsigned long stvec =3D (unsigned long)&do_expected_trap; \ + register unsigned long ret =3D 0; \ + unsigned long flags; \ + ((struct trap_info *)(trap))->scause =3D 0; \ + local_irq_save(flags); \ + asm volatile ( \ + ".option push\n" \ + ".option norvc\n" \ + "add %[ttmp], %[tinfo], zero\n" \ + "csrrw %[stvec], " STR(CSR_STVEC) ", %[stvec]\n" \ + "csrr %[ret], %[csr]\n" \ + "csrw " STR(CSR_STVEC) ", %[stvec]\n" \ + ".option pop" \ + : [stvec] "+&r" (stvec), [tinfo] "+&r" (tinfo), \ + [ttmp] "+&r" (ttmp), [ret] "=3D&r" (ret) \ + : [csr] "i" (csr_num) \ + : "memory" ); \ + local_irq_restore(flags); \ + ret; \ +}) + #endif /* __ASSEMBLER__ */ =20 #endif /* ASM__RISCV__CSR_H */ diff --git a/xen/arch/riscv/include/asm/traps.h b/xen/arch/riscv/include/as= m/traps.h index 21fa3c3259b3..194d9a72f3ed 100644 --- a/xen/arch/riscv/include/asm/traps.h +++ b/xen/arch/riscv/include/asm/traps.h @@ -7,10 +7,17 @@ =20 #ifndef __ASSEMBLER__ =20 +struct trap_info { + register_t sepc; + register_t scause; +}; + void do_trap(struct cpu_user_regs *cpu_regs); void handle_trap(void); void trap_init(void); =20 +void do_expected_trap(void); + #endif /* __ASSEMBLER__ */ =20 #endif /* ASM__RISCV__TRAPS_H */ diff --git a/xen/arch/riscv/riscv64/asm-offsets.c b/xen/arch/riscv/riscv64/= asm-offsets.c index 472cced4f8af..b0e2a4d86bd3 100644 --- a/xen/arch/riscv/riscv64/asm-offsets.c +++ b/xen/arch/riscv/riscv64/asm-offsets.c @@ -1,8 +1,10 @@ #define COMPILE_OFFSETS =20 +#include + #include #include -#include +#include =20 #define DEFINE(_sym, _val) = \ asm volatile ( "\n.ascii\"=3D=3D>#define " #_sym " %0 /* " #_val " */<= =3D=3D\""\ @@ -54,4 +56,7 @@ void asm_offsets(void) BLANK(); DEFINE(PCPU_INFO_SIZE, sizeof(struct pcpu_info)); BLANK(); + OFFSET(RISCV_TRAP_SEPC, struct trap_info, sepc); + OFFSET(RISCV_TRAP_SCAUSE, struct trap_info, scause); + BLANK(); } --=20 2.53.0