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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd68826asm220079295e9.0.2026.02.26.03.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 03:51:24 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7a857585-1309-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772106685; x=1772711485; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hp5eAdCk/2OvwDZTtcjSxeKObwgzunQJOuXOKfijBE4=; b=RyWH5bb4yR/tmFBThWdUwaJSlABlzhK/2kDuPqtrd6021Qx0ObfANh6QIHhkegpsdE rGDiiZFAiHIhQsUGEA6DMXEoRjuVRD2aXX5QpcQR+Vxt9pqKSobP0fdxgsPJNPB/QLmU 2O8M9WWSbVVPS6UKeVLO3HNZa1RD8RO+qs2c4qacX7LQSY+quVYz1/4us7mNPrMOclc2 p2MW5xk9ix7xspqKj84Q8mRzuQYJbiLuI682u0zHRr6BokxvSIZbzotb3h3ux8hkjhtp AqlH0/s7uH5eTI2v+7GbCbR8dhsEtpEhaO0klQ4zLaFuZD08g+NQ/jdzQUuRH2UIc0sW ZwYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772106685; x=1772711485; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Hp5eAdCk/2OvwDZTtcjSxeKObwgzunQJOuXOKfijBE4=; b=fGmkA5xGfcCcJXTFfhavJqGnRT7VJpRAGcR/ZzUFhpB/C/SLa3+qJtIwOqG/e3H4RR nLXLROjx+Pf0OpRd9oDFf8qDVFQiNyXmU5LhKPCNctydy3Fi7ha2I47YMhiUMtuSWZAB dmG+WL02vr+P7E93mszysQcW6f2iKC/IyM1cF3toP4QhLdM/4AC+e+niXlTwgHlp18Ss diZGt4WcenmTVTpPMRZAWTwm8iFmMIQN/HGXEW+Xnt41co6sriLo5jgOfePhcROSA9JH y5jizuhKeIEk5IuYhZ1lalK2eDoctgosCmdR1KTHFVrrig/Fud6ajAWCAgHpMAziT/jw 3AQA== X-Gm-Message-State: AOJu0YwLU7QWkDaJOxz2D8pc1Bwr6X0dmKXl6z/zCHARuQ+tngC89Xe4 NYrekiTf7D9OSXHAIWuMn+obILLrmE3xGSYmtnrlY30VxQa1XFFBR79bZckA2g== X-Gm-Gg: ATEYQzyCZ029jCQF+i+3ClRkiuDRMVXszRQsJCpuVx572YfCa1tEubMl/q+nLvUV3fb nIC6+a65JviEhsyfaU5Z6VItY6XgISPwL3UiLcKOpgLoeRsaUbPBJBGBzCqzZSodBjcP5PswHQh DzcuklLWSCvGJx81V3SSxtIBL62rJ3C9132SvJsARhtmCnq6cwtklt+WNGUdB112ZVzgqcDylRa Os9cRmyLOa9dSizZQ6AUoy17820lOwmm6+FLhAKpxa2TpQbwTW8oDjgFuP6E/CvuPAX9anFuzkT e1NGB39jeUGV56XeegXDBEZvEXtFy59cciaL0TLZp2x/q8eAyit0iyeuGfQTDmnIKQko/9Yj/MB foNdBnBqL+GbsftjFPjZygJcNnc6wTz8fsKpVLsdUN0h9IIjUbSIcHKUxMZk//oEQe6fkXzi4kV yjtVL8xDCP64PyqZXmC7rEhstUXwXWu8Mj+FcZoem6reQNxU6f5AmQV1l1W8jqYC5tizN2UJ/sP J6n X-Received: by 2002:a05:600c:1e8f:b0:477:98f7:2aec with SMTP id 5b1f17b1804b1-483c3db3198mr31642645e9.3.1772106684538; Thu, 26 Feb 2026 03:51:24 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 01/14] xen/riscv: detect and store supported hypervisor CSR bits at boot Date: Thu, 26 Feb 2026 12:51:01 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772106720998158500 Content-Type: text/plain; charset="utf-8" Some hypervisor CSRs expose optional functionality and may not implement all architectural bits. Writing unsupported bits can either be ignored or raise an exception depending on the platform. Detect the set of writable bits for selected hypervisor CSRs at boot and store the resulting masks for later use. This allows safely programming these CSRs during vCPU context switching and avoids relying on hardcoded architectural assumptions. Use csr_read()&csr_write() instead of csr_swap()+all ones mask as some CSR registers have WPRI fields which should be preserved during write operation. Also, ro_one struct is introduced to cover the cases when a bit in CSR register (at the momemnt, it is only hstateen0) may be r/o-one to have hypervisor view of register seen by guest correct. Masks are calculated at the moment only for hedeleg, henvcfg, hideleg, hstateen0 registers as only them are going to be used in the follow up patch. If the Smstateen extension is not implemented, hstateen0 cannot be read because the register is considered non-existent. Instructions that attempt to access a CSR that is not implemented or not visible in the current mode are reserved and will raise an illegal-instruction exception. Signed-off-by: Oleksii Kurochko --- Changes in V6: - Introduce sub-struct ro_one inside csr_masks to cover the case that hstateen0 could have read-only-one bits. - Refacotr init_csr_masks() to handle hstateen0 case when a bit is r/o-one and handle WPRI fields properly. - Update the commit message. --- Changes in V5: - Move everything related to csr_masks to domain.c and make it static. - Move declaration of old variable in init_csr_masks() inside INIT_CSR_MAS= K. - Use csr_swap() in INIT_CSR_MASK(). --- Changes in V4: - Move csr_masks defintion to domain.c. Make it static as at the moment it is going to be used only in domain.c. - Rename and refactor X macros inside init_csr_masks(). --- Changes in V3: - New patch. --- xen/arch/riscv/domain.c | 47 ++++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/setup.h | 2 ++ xen/arch/riscv/setup.c | 2 ++ 3 files changed, 51 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index b60320b90def..902aaac74290 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -2,9 +2,56 @@ =20 #include #include +#include #include #include =20 +#include +#include + +struct csr_masks { + register_t hedeleg; + register_t henvcfg; + register_t hideleg; + register_t hstateen0; + + struct { + register_t hstateen0; + } ro_one; +}; + +static struct csr_masks __ro_after_init csr_masks; + +void __init init_csr_masks(void) +{ + /* + * The mask specifies the bits that may be safely modified without + * causing side effects. + * + * For example, registers such as henvcfg or hstateen0 contain WPRI + * fields that must be preserved. Any write to the full register must + * therefore retain the original values of those fields. + */ +#define INIT_CSR_MASK(csr, field, mask) do { \ + old =3D csr_read(CSR_##csr); \ + csr_write(CSR_##csr, (old & ~(mask)) | (mask)); \ + csr_masks.field =3D csr_swap(CSR_##csr, old); \ + } while (0) + + register_t old; + + INIT_CSR_MASK(HEDELEG, hedeleg, ULONG_MAX); + INIT_CSR_MASK(HIDELEG, hideleg, ULONG_MAX); + + INIT_CSR_MASK(HENVCFG, henvcfg, _UL(0xE0000003000000FF)); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + INIT_CSR_MASK(HSTATEEN0, hstateen0, _UL(0xDE00000000000007)); + csr_masks.ro_one.hstateen0 =3D old; + } +} + static void continue_new_vcpu(struct vcpu *prev) { BUG_ON("unimplemented\n"); diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/as= m/setup.h index c9d69cdf5166..2215894cfbb1 100644 --- a/xen/arch/riscv/include/asm/setup.h +++ b/xen/arch/riscv/include/asm/setup.h @@ -11,6 +11,8 @@ void setup_mm(void); =20 void copy_from_paddr(void *dst, paddr_t paddr, unsigned long len); =20 +void init_csr_masks(void); + #endif /* ASM__RISCV__SETUP_H */ =20 /* diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 9b4835960d20..bca6ca09eddd 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -137,6 +137,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, =20 riscv_fill_hwcap(); =20 + init_csr_masks(); + preinit_xen_time(); =20 intc_preinit(); --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772106717; cv=none; d=zohomail.com; s=zohoarc; b=Fzy3HJD0zDGU5aiJqCJ9lHMIjpWLgVqsHq0/JWYx6Ju4X9ljEa9gBcPQrFUjzPi4Fm6cRIfDqldrYTOL5zLSnVJAmGsIZt4bnLgqfb2CQZYCGf7wOBcEH3kYDawEg/OmwYw8LNDAYh6FsGqFGlMusRPokFfOhH6f2/DbyKlxMFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772106717; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mjWgFbv6nb7y5dLkGr2P5tKeDiy8GNkU4xO5G3VBP8c=; b=Y0fuWnXdWkimInB7CaYRs6CqDDZrFQu+mMVYdb3ce0uQV23gobPpgoavyuvwwdpf8zm5ZU5l2FmhUD5/KAORBG7nRZ7aKAtUnmUA/lGpQTvPmWvMDqrqu5kjwuto2bh7SQvVGWUDaxGzi4l7JXBQM/P1w7cA2/KcEZA+eRw9FaY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 177210671795688.6313700041494; Thu, 26 Feb 2026 03:51:57 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1241453.1542494 (Exim 4.92) (envelope-from ) id 1vvZty-0006fg-9d; Thu, 26 Feb 2026 11:51:30 +0000 Received: by outflank-mailman (output) from mailman id 1241453.1542494; Thu, 26 Feb 2026 11:51:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZty-0006fZ-77; Thu, 26 Feb 2026 11:51:30 +0000 Received: by outflank-mailman (input) for mailman id 1241453; Thu, 26 Feb 2026 11:51:29 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZtx-0006EH-6A for xen-devel@lists.xenproject.org; Thu, 26 Feb 2026 11:51:29 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7b62d24c-1309-11f1-9ccf-f158ae23cfc8; Thu, 26 Feb 2026 12:51:27 +0100 (CET) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-483bd7354efso10329965e9.2 for ; Thu, 26 Feb 2026 03:51:27 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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The function configures trap and interrupt delegation to VS-mode by setting the appropriate bits in the hedeleg and hideleg registers, initializes hstatus so that execution enters VS-mode when control is passed to the guest, and restricts guest access to hardware performance counters by initializing hcounteren, as unrestricted access would require additional handling in Xen. When the Smstateen and SSAIA extensions are available, access to AIA CSRs and IMSIC guest interrupt files is enabled by setting the corresponding bits in hstateen0, avoiding unnecessary traps into Xen (note that SVSLCT(Supervisor Virtual Select) name is used intead of CSRIND as OpenSBI uses such name and riscv_encoding.h is mostly based on it). If the Svpbmt extension is supported, the PBMTE bit is set in henvcfg to allow its use for VS-stage address translation. Guest access to the ENVCFG CSR is also enabled by setting ENVCFG bit in hstateen0, as a guest may need to control certain characteristics of the U-mode (VU-mode when V=3D1) execution environment. For CSRs that may contain read-only bits (e.g. hedeleg, hideleg, hstateen0), to the written value a correspondent mask is applied to avoid divergence between the software state and the actual CSR contents. As hstatus is not part of struct arch_vcpu (it already resides in struct cpu_user_regs), introduce vcpu_guest_cpu_user_regs() to provide a uniform way to access hstatus and other guest CPU user registers. This establishes a consistent and well-defined initial CSR state for vCPUs prior to their first context switch. Signed-off-by: Oleksii Kurochko --- Changes in V6: - Apply introduced in prev. patch csr_masks.ro_one.hstaten0 in vcpu_csr_in= it(). --- Changes in v5: - Initialize of hstateen0 with SMSTATEEN0_HSENVCFG when a variable is defined. - Use |=3D for a code inside if (*_ssaia) case. - Put declaration of the registers hedeleg and hideleg together in arch_vc= pu structure as they are typically used together so better chances to be in the same cache line. --- Changes in v4: - Move local variable hstateen0 into narrower scope. - Code style fixes. - Move the call of vcpu_csr_init(v) after if ( is_idle_vcpu() ) check in arcg_vcpu_create(). --- Changes in v3: - Add hypervisor register used to initalize vCPU state. - Apply masks introduced before instead of csr_write()/csr_read() pattern. --- Changes in v2: - As hstatus isn't a part of arch_vcpu structure (as it is already a part = of cpu_user_regs) introduce vcpu_guest_cpu_user_regs() to be able to access hstatus and other CPU user regs. - Sort hideleg bit setting by value. Drop a stray blank. - Drop | when the first initialization of hcounteren and hennvcfg happen. - Introduce HEDELEG_DEFAULT. Sort set bits by value and use BIT() macros instead of open-coding it. - Apply pattern csr_write() -> csr_read() for hedeleg and hideleg instead of direct bit setting in v->arch.h{i,e}deleg as it could be that for some reason some bits of hedeleg and hideleg are r/o. The similar patter is used for hstateen0 as some of the bits could be r/= o. - Add check that SSAIA is avaialable before setting of SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_SVSLCT bits. - Drop local variables hstatus, hideleg and hedeleg as they aren't used anymore. --- xen/arch/riscv/domain.c | 63 +++++++++++++++++++++ xen/arch/riscv/include/asm/current.h | 2 + xen/arch/riscv/include/asm/domain.h | 6 ++ xen/arch/riscv/include/asm/riscv_encoding.h | 2 + 4 files changed, 73 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 902aaac74290..2a81f8d94f9a 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -8,6 +8,7 @@ =20 #include #include +#include =20 struct csr_masks { register_t hedeleg; @@ -20,6 +21,21 @@ struct csr_masks { } ro_one; }; =20 +#define HEDELEG_DEFAULT (BIT(CAUSE_MISALIGNED_FETCH, U) | \ + BIT(CAUSE_FETCH_ACCESS, U) | \ + BIT(CAUSE_ILLEGAL_INSTRUCTION, U) | \ + BIT(CAUSE_BREAKPOINT, U) | \ + BIT(CAUSE_MISALIGNED_LOAD, U) | \ + BIT(CAUSE_LOAD_ACCESS, U) | \ + BIT(CAUSE_MISALIGNED_STORE, U) | \ + BIT(CAUSE_STORE_ACCESS, U) | \ + BIT(CAUSE_USER_ECALL, U) | \ + BIT(CAUSE_FETCH_PAGE_FAULT, U) | \ + BIT(CAUSE_LOAD_PAGE_FAULT, U) | \ + BIT(CAUSE_STORE_PAGE_FAULT, U)) + +#define HIDELEG_DEFAULT (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) + static struct csr_masks __ro_after_init csr_masks; =20 void __init init_csr_masks(void) @@ -52,6 +68,51 @@ void __init init_csr_masks(void) } } =20 +static void vcpu_csr_init(struct vcpu *v) +{ + v->arch.hedeleg =3D HEDELEG_DEFAULT & csr_masks.hedeleg; + + vcpu_guest_cpu_user_regs(v)->hstatus =3D HSTATUS_SPV | HSTATUS_SPVP; + + v->arch.hideleg =3D HIDELEG_DEFAULT & csr_masks.hideleg; + + /* + * VS should access only the time counter directly. + * Everything else should trap. + */ + v->arch.hcounteren =3D HCOUNTEREN_TM; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svpbmt) ) + v->arch.henvcfg =3D ENVCFG_PBMTE & csr_masks.henvcfg; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) ) + { + /* Allow guest to access CSR_SENVCFG */ + register_t hstateen0 =3D SMSTATEEN0_HSENVCFG; + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) + /* + * If the hypervisor extension is implemented, the same three + * bits are defined also in hypervisor CSR hstateen0 but conce= rn + * only the state potentially accessible to a virtual machine + * executing in privilege modes VS and VU: + * bit 60 CSRs siselect and sireg (really vsiselect and + * vsireg) + * bit 59 CSRs siph and sieh (RV32 only) and stopi (really + * vsiph, vsieh, and vstopi) + * bit 58 all state of IMSIC guest interrupt files, inclu= ding + * CSR stopei (really vstopei) + * If one of these bits is zero in hstateen0, and the same bit= is + * one in mstateen0, then an attempt to access the correspondi= ng + * state from VS or VU-mode raises a virtual instruction excep= tion. + */ + hstateen0 |=3D SMSTATEEN0_AIA | SMSTATEEN0_IMSIC | SMSTATEEN0_= SVSLCT; + + v->arch.hstateen0 =3D (hstateen0 & csr_masks.hstateen0) | + csr_masks.ro_one.hstateen0; + } +} + static void continue_new_vcpu(struct vcpu *prev) { BUG_ON("unimplemented\n"); @@ -74,6 +135,8 @@ int arch_vcpu_create(struct vcpu *v) if ( is_idle_vcpu(v) ) return 0; =20 + vcpu_csr_init(v); + /* * As the vtimer and interrupt controller (IC) are not yet implemented, * return an error. diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/= asm/current.h index 58c9f1506b7c..5fbee8182caa 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -48,6 +48,8 @@ DECLARE_PER_CPU(struct vcpu *, curr_vcpu); #define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu) =20 #define guest_cpu_user_regs() ({ BUG_ON("unimplemented"); NULL; }) +#define vcpu_guest_cpu_user_regs(vcpu) \ + (&(vcpu)->arch.cpu_info->guest_cpu_user_regs) =20 #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 5aec627a7adb..17be792afe7d 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -49,6 +49,12 @@ struct arch_vcpu { =20 struct cpu_info *cpu_info; =20 + register_t hcounteren; + register_t hedeleg; + register_t hideleg; + register_t henvcfg; + register_t hstateen0; + register_t vsatp; }; =20 diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index 1f7e612366f8..dd15731a86fa 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -228,6 +228,8 @@ #define ENVCFG_CBIE_INV _UL(0x3) #define ENVCFG_FIOM _UL(0x1) =20 +#define HCOUNTEREN_TM BIT(1, U) + /* =3D=3D=3D=3D=3D User-level CSRs =3D=3D=3D=3D=3D */ =20 /* User Trap Setup (N-extension) */ --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Note that smp_wmb() is used instead of smp_mb__before_atomic() as what we want to guarantee that if a bit in irqs_pending_mask is obversable that the correspondent bit in irqs_pending is observable too. Add lockless tracking of pending vCPU interrupts using atomic bitops. Two bitmaps are introduced: - irqs_pending =E2=80=94 interrupts currently pending for the vCPU - irqs_pending_mask =E2=80=94 bits that have changed in irqs_pending The design follows a multi-producer, single-consumer model, where the consumer is the vCPU itself. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg(). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. On RISC-V interrupts are not injected via guest registers, so pending interrupts must be recorded in irqs_pending (using the new vcpu_{un}set_interrupt() helpers) and flushed to the guest by updating HVIP before returning control to the guest. The consumer side is implemented in a follow-up patch. A barrier between updating irqs_pending and setting the corresponding mask bit in vcpu_set_interrupt()/vcpu_unset_interrupt() guarantees that if the consumer observes a mask bit set, the corresponding pending bit is also visible. This prevents missed interrupts during the flush. It is possible that a guest could have pending bit in the hardware register without being marked pending in irq_pending bitmap as: According to the RISC-V ISA specification: Bits hip.VSSIP and hie.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in hip is an alias (writable) of the same bit in hvip. Additionally: When bit 2 of hideleg is zero, vsip.SSIP and vsie.SSIE are read-only zeros. Else, vsip.SSIP and vsie.SSIE are aliases of hip.VSSIP and hie.VSSIE. This means the guest may modify vsip.SSIP, which implicitly updates hip.VSSIP and the bit being written with 1 would also trigger an interrupt as according to the RISC-V spec: These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in sip, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including sip, sie and sstatus). What means that IRQ_VS_SOFT must be synchronized separately, what is done in vcpu_sync_interrupts(). Note, also, that IRQ_PMU_OVF would want to be synced for the similar reason as IRQ_VS_SOFT, but isn't sync-ed now as PMU isn't supported now. For the remaining VS-level interrupt types (IRQ_VS_TIMER and IRQ_VS_EXT), the specification states they cannot be modified by the guest and are read-only because of: Bits hip.VSEIP and hie.VSEIE are the interrupt-pending and interrupt-enab= le bits for VS-level external interrupts. VSEIP is read-only in hip, and is the logical-OR of these interrupt sources: =E2=80=A2 bit VSEIP of hvip; =E2=80=A2 the bit of hgeip selected by hstatus.VGEIN; and =E2=80=A2 any other platform-specific external interrupt signal directe= d to VS-level. Bits hip.VSTIP and hie.VSTIE are the interrupt-pending and interrupt-enab= le bits for VS-level timer interrupts. VSTIP is read-only in hip, and is the logical-OR of hvip.VSTIP and any other platform-specific timer interrupt signal directed to VS-level. and When bit 10 of hideleg is zero, vsip.SEIP and vsie.SEIE are read-only zer= os. Else, vsip.SEIP and vsie.SEIE are aliases of hip.VSEIP and hie.VSEIE. When bit 6 of hideleg is zero, vsip.STIP and vsie.STIE are read-only zero= s. Else, vsip.STIP and vsie.STIE are aliases of hip.VSTIP and hie.VSTIE. and also, Bits sip.SEIP and sie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller. Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If implemented, STIP is read-only in sip, and is set and cleared by the execution environment Thus, for these interrupt types, it is sufficient to use vcpu_set_interrupt= () and vcpu_unset_interrupt(), and flush them during the call of vcpu_flush_interrupts() (which is introduced in follow up patch). vcpu_sync_interrupts(), which is called just before entering the VM, slightly bends the rule that the irqs_pending bit must be written first, followed by updating the corresponding bit in irqs_pending_mask. However, it still respects the core guarantee that the producer never clears the mask and only writes to irqs_pending if it is the one that flipped the corresponding mask bit from 0 to 1. Moreover, since the consumer won't run concurrently because vcpu_sync_interrupts() and the consumer path are going to be invoked sequentially immediately before VM entry, it is safe to slightly relax this ordering rule in vcpu_sync_interrupts(). Signed-off-by: Oleksii Kurochko --- Changes in v6: - Drop for the moment: /* Read current HVIP and VSIE CSRs */ v->arch.vsie =3D csr_read(CSR_VSIE); from vcpu_sync_interrupts() as it isn't used at the moment and will be introduced when a usage will be more clear. --- Changes in v5: - Update the commit message(). - Rename c to curr. - Update vcpu_set_interrupt() to use test_and_set_bit() for irqs_pending bitmask too. - Move #ifdef CONFIG_RISCV_32 above the comment in vcpu_sync_interrupts(). --- Changes in v4: - Update the commit message. - Update the comments in vcpu_(un)set_interrupt() and add the the comment above smp_wmb() barrier. - call vcpu_kick() only if the pending_mask bit going from 0 to 1. - Code style fixes. - Update defintion of RISCV_VCPU_NR_IRQS to cover potential RV128 case and the case if AIA isn't used. - latch current into a local variable in check_for_pcpu_work(). --- Changes in v3: - Use smp_wb() instead of smp_mb__before_atomic(). - Add explanation of the change above in the commit message. - Move vcpu_sync_interrupts() here to producers side. - Introduce check_for_pcpu_work() to be clear from where vcpu_sync_interru= pts() is called. --- Changes in V2: - Move the patch before an introduction of vtimer. - Drop bitmap_zero() of irqs_pending and irqs_pending_mask bitmaps as vcpu structure starts out all zeros. - Drop const for irq argument of vcpu_{un}set_interrupt(). - Drop check "irq < IRQ_LOCAL_MAX" in vcpu_{un}set_interrupt() as it could lead to overrun of irqs_pending and irqs_pending_mask bitmaps. - Drop IRQ_LOCAL_MAX as there is no usage for it now. --- xen/arch/riscv/domain.c | 71 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 22 +++++++++ xen/arch/riscv/traps.c | 4 ++ 3 files changed, 97 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 2a81f8d94f9a..047dbebc1a09 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -6,6 +6,7 @@ #include #include =20 +#include #include #include #include @@ -158,6 +159,76 @@ void arch_vcpu_destroy(struct vcpu *v) vfree((void *)&v->arch.cpu_info[1] - STACK_SIZE); } =20 +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq) +{ + bool kick_vcpu; + + /* We only allow VS-mode software, timer, and external interrupts */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + kick_vcpu =3D !test_and_set_bit(irq, v->arch.irqs_pending); + + /* + * The counterpart of this barrier is the one encoded implicitly in xc= hg() + * which is used in consumer part (vcpu_flush_interrupts()). + */ + smp_wmb(); + + kick_vcpu |=3D !test_and_set_bit(irq, v->arch.irqs_pending_mask); + + if ( kick_vcpu ) + vcpu_kick(v); + + return 0; +} + +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq) +{ + /* We only allow VS-mode software, timer, external interrupts */ + if ( irq !=3D IRQ_VS_SOFT && + irq !=3D IRQ_VS_TIMER && + irq !=3D IRQ_VS_EXT ) + return -EINVAL; + + clear_bit(irq, v->arch.irqs_pending); + /* + * The counterpart of this barrier is the one encoded implicitly in xc= hg() + * which is used in consumer part (vcpu_flush_interrupts()). + */ + smp_wmb(); + set_bit(irq, v->arch.irqs_pending_mask); + + return 0; +} + +void vcpu_sync_interrupts(struct vcpu *v) +{ + unsigned long hvip =3D csr_read(CSR_HVIP); + + /* Sync-up HVIP.VSSIP bit changes done by Guest */ + if ( ((v->arch.hvip ^ hvip) & BIT(IRQ_VS_SOFT, UL)) && + !test_and_set_bit(IRQ_VS_SOFT, &v->arch.irqs_pending_mask) ) + { + if ( hvip & BIT(IRQ_VS_SOFT, UL) ) + set_bit(IRQ_VS_SOFT, &v->arch.irqs_pending); + else + clear_bit(IRQ_VS_SOFT, &v->arch.irqs_pending); + } + +#ifdef CONFIG_RISCV_32 + /* + * Sync-up AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't supported + * now. + */ +# error "Update v->arch.vsieh" +#endif +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 17be792afe7d..e19365c6fb77 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -54,8 +54,25 @@ struct arch_vcpu { register_t hideleg; register_t henvcfg; register_t hstateen0; + register_t hvip; =20 register_t vsatp; + + /* + * VCPU interrupts + * + * We have a lockless approach for tracking pending VCPU interrupts + * implemented using atomic bitops. The irqs_pending bitmap represent + * pending interrupts whereas irqs_pending_mask represent bits changed + * in irqs_pending. Our approach is modeled around multiple producer + * and single consumer problem where the consumer is the VCPU itself. + * + * DECLARE_BITMAP() is needed here to support 64 vCPU local interrupts + * on RV32 host. + */ +#define RISCV_VCPU_NR_IRQS MAX(BITS_PER_LONG, 64) + DECLARE_BITMAP(irqs_pending, RISCV_VCPU_NR_IRQS); + DECLARE_BITMAP(irqs_pending_mask, RISCV_VCPU_NR_IRQS); }; =20 struct paging_domain { @@ -94,6 +111,11 @@ static inline void update_guest_memory_policy(struct vc= pu *v, =20 static inline void arch_vcpu_block(struct vcpu *v) {} =20 +int vcpu_set_interrupt(struct vcpu *v, unsigned int irq); +int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); + +void vcpu_sync_interrupts(struct vcpu *v); + #endif /* ASM__RISCV__DOMAIN_H */ =20 /* diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 9fca941526f6..551f886e3a69 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -171,6 +171,10 @@ static void do_unexpected_trap(const struct cpu_user_r= egs *regs) =20 static void check_for_pcpu_work(void) { + struct vcpu *curr =3D current; + + vcpu_sync_interrupts(curr); + p2m_handle_vmenter(); } =20 --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772106718; cv=none; d=zohomail.com; s=zohoarc; b=KRPJci01wYQCtx9tfcuwa62rOSWCDs3PLq+md1kM8ZN/qaZ4zZQqkePluCapnHBgKgt7ptA72UOPxA4Lm2UTubMt7XJBcJkWXJinH9WsJHEM4H4ridF+Eo0DFz3GOfhaNlgi+jxXskcvUyv5a3DcVCCpwrbjcSNSKK7Zv8Hlzpk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772106718; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=33kKmz90cEezZ0SKbWH5QuCoRKJPXKUuazyZn8mlTZE=; b=mKCpvLa6PZN4Xwv4t9o6lq1VyjnMtEBlyZ6rylX21N+TE66ZWlMHycbs2CePZiWlZuGSZ+vcJwoJPsXNtMcWwqqsF+EIYRUoae6zs/h+a34mcL4gAAU4yzZuTHZ+JuYyM5w8OYvZvqQ7Wak00tANsbvlfWO4BRw3xl2nC065qlY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772106718520307.6749967922383; Thu, 26 Feb 2026 03:51:58 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1241456.1542523 (Exim 4.92) (envelope-from ) id 1vvZu2-0007Ld-8N; Thu, 26 Feb 2026 11:51:34 +0000 Received: by outflank-mailman (output) from mailman id 1241456.1542523; Thu, 26 Feb 2026 11:51:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZu2-0007Kh-4g; Thu, 26 Feb 2026 11:51:34 +0000 Received: by outflank-mailman (input) for mailman id 1241456; Thu, 26 Feb 2026 11:51:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZu0-0006E8-Mf for xen-devel@lists.xenproject.org; Thu, 26 Feb 2026 11:51:32 +0000 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [2a00:1450:4864:20::330]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 7cd91581-1309-11f1-b164-2bf370ae4941; Thu, 26 Feb 2026 12:51:29 +0100 (CET) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4836f363ad2so9650385e9.1 for ; Thu, 26 Feb 2026 03:51:29 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd68826asm220079295e9.0.2026.02.26.03.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 03:51:28 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7cd91581-1309-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772106689; x=1772711489; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=33kKmz90cEezZ0SKbWH5QuCoRKJPXKUuazyZn8mlTZE=; b=XEGGpl0sBwW93wLua95wUwjmqlZS6NVG6Ultc/synH70ofdyRA31yeJS90QDCSW0K2 GF11xwcRaN6N7QcQFZTu+EF5/VZ5fqwJl1ad1K7YLCm2mHP2EmTFbdepepEJhrROHpJr VMXqRePfXWtTZDWVL9xYxU0YBjHhg86s1sc8Bbe3NvW9p9gaTgP9jslxS2xM1wkc1uVq u7BcxqlQa+B/QkbhPLdMP8iozGRRkGYSmT/Pg1ZEAddUbVvWYfDdFqdkqX5sMOEDL4xa OUXBnuBKQ93QWMVi1t6qKm+2nqQpKlyNTAuoBnQghoWrM+XlAu76vMD7/TuzvCouPVr/ tjEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772106689; x=1772711489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=33kKmz90cEezZ0SKbWH5QuCoRKJPXKUuazyZn8mlTZE=; b=OoFmymOd3WJyz+ZiJp5tPpWlPb9sA3HpHySwEGIAr5gN3buDPLpbamtMDxjE4ISIZB q5V+fNb/qVNj2MG30GjTOL1qiD5A/zptvyQc0MGstJmR6dvUzZ3i75JBhBR4lGNm1x9o LhiR+JVmWWSC48jvHSg/12qJY4t9+6zGq/6IH+QJjYJfRSSRMcxiXe4uK2xCQ4sHLuwR xlN80MVHqgiffPdJX3/45brD8TCBwvubfxv2xYR2S89LMEKi8IpsrfKSfdmpdEL3feha Ld57RSWQmPOiMmLAkw6Eci2fEEtMrVbl8Z1a4K9GjjZ3Ya+p2Ru9DCz5BXqyln6guSg4 0zhA== X-Gm-Message-State: AOJu0Yy4kYMeU8knqexZ9lBI8yt3fjRehjChiQJTGhb2f/GtnFKWfGxi KwTQHkFRtB3hT0/z3y7ikBy67w5q6fH8Ix4H41WNxNC+bddgeN5CG+fvMH7FBA== X-Gm-Gg: ATEYQzzAW1Kw721AmNj9JSA0TjL2F8q1rzilRctwL/2CReJt//mCs3nwZeBiduhyc7Y blvkfLfa8KYqAO6qx29E9Eg7904ehRxovFvS/JtZpg3YhgjNg28XHx7R42VsDdT6H4zQPBV3kKc AtMZb7E2r9oIPxIt5AhvLQ2vfF/vVZESwb5KtbzgLpL3MoTW6fKQunGN0sXVMB/0o59KCeckNu5 h4oQzL+XxDIVMaDpyh1mGMiFuc9Qckp0LjeOCKRYO3mZwGYY6EPgQ/xThSKzSelD8XqunDeDeRR eScEyNGFYVhm+w8f4PPlDt62KSplIvW+yV/RNos/+qLRTeEb4HIs+wuk3s/HnKigYzOgVSE+ViN o4ZtGzghEUAxQHKTHkFcTq2uw5ZRCiHpAllyDEEGn4covrXFKLBjUkLk9A/uku1c2+cR2tGGePn QGvcAsBw0lr6WCQA2z08s1/BiiN/dBCSVUmpL7U37FWO+0EYavU5QgvS5DaTzTg1r1Ww== X-Received: by 2002:a05:600c:470f:b0:46f:c55a:5a8d with SMTP id 5b1f17b1804b1-483a95a852cmr341721945e9.4.1772106688743; Thu, 26 Feb 2026 03:51:28 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 04/14] xen/riscv: introduce tracking of pending vCPU interrupts, part 2 Date: Thu, 26 Feb 2026 12:51:04 +0100 Message-ID: <07a3750bf152f31ef8013194536f199ac3540dcf.1772016457.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772106719050158501 Content-Type: text/plain; charset="utf-8" This patch is based on Linux kernel 6.16.0. Add the consumer side (vcpu_flush_interrupts()) of the lockless pending interrupt tracking introduced in part 1 (for producers). According, to the design only one consumer is possible, and it is vCPU itself. vcpu_flush_interrupts() is expected to be ran (as guests aren't ran now due to the lack of functionality) before the hypervisor returns control to the guest. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg() (with aquire semantics). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. The worst thing which could happen with such approach is that a new pending bit will be set to irqs_pending bitmap during update of hvip variable in vcpu_flush_interrupt() but it isn't problem as the new pending bit won't be lost and just be proceded during the next flush. As AIA specs introduced hviph register which would want to be updated when guest related AIA code vcpu_update_hvip() is introduced instead of just open-code it in vcpu_flush_interrupts(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6: - Nothing changed. Only rebase. --- Changes in v5: - Reorder the defintions of local variables (mask, val, hvip) in vcpu_flush_interrupts(). Also, drop a blank line between them. - Move #ifdef CONFIG_RISCV_32 above the comment in vcpu_flush_interrupts() and align the comment properly. - Add Acked-by: Jan Beulich . --- Changes in v4: - Move defintion of hvip local variable to narrower space in vcpu_flush_interrupts(). - Use initializers for mask and val variables. - Use local variable c as an argument of vcpu_flush_interrupts() in check_for_pcpu_work(). --- Changes in v3: - Update the error message in case of RV32 from "hviph" to v->arch.hviph. - Make const argument of vcpu_update_hvip. - Move local variables mask and val inside if() in vcpu_flush_interrupts(). - Call vcpu_flush_interrupts() in check_pcpu_work(). - Move vcpu_update_hvip() inside if() in vcpu_flush_interrupts(). --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 30 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/traps.c | 2 ++ 3 files changed, 33 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 047dbebc1a09..6988d7032059 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -229,6 +229,36 @@ void vcpu_sync_interrupts(struct vcpu *v) #endif } =20 +static void vcpu_update_hvip(const struct vcpu *v) +{ + csr_write(CSR_HVIP, v->arch.hvip); +} + +void vcpu_flush_interrupts(struct vcpu *v) +{ + if ( ACCESS_ONCE(v->arch.irqs_pending_mask[0]) ) + { + unsigned long mask =3D xchg(&v->arch.irqs_pending_mask[0], 0UL); + unsigned long val =3D ACCESS_ONCE(v->arch.irqs_pending[0]) & mask; + register_t *hvip =3D &v->arch.hvip; + + *hvip &=3D ~mask; + *hvip |=3D val; + + vcpu_update_hvip(v); + } + +#ifdef CONFIG_RISCV_32 + /* + * Flush AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't + * supported now. + */ +# error "Update v->arch.hviph" +#endif +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index e19365c6fb77..5373a498d80b 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -115,6 +115,7 @@ int vcpu_set_interrupt(struct vcpu *v, unsigned int irq= ); int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); =20 void vcpu_sync_interrupts(struct vcpu *v); +void vcpu_flush_interrupts(struct vcpu *v); =20 #endif /* ASM__RISCV__DOMAIN_H */ =20 diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 551f886e3a69..244264c92a79 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -175,6 +175,8 @@ static void check_for_pcpu_work(void) =20 vcpu_sync_interrupts(curr); =20 + vcpu_flush_interrupts(curr); + p2m_handle_vmenter(); } =20 --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772106724; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd68826asm220079295e9.0.2026.02.26.03.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 03:51:29 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7da961ba-1309-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772106690; x=1772711490; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tg5etO1tk6Lt3f6BDEvCCqmunpQhCPFEnQLjlhq8TEw=; b=lNRRXncDpZcQ3C2vN5pa2w/2+0Z8u1zGEAb4OuHBWJv06bQlAHifJ/ACPExfc6bG2n 5ErLJ+Av0ngAKC5PAiawHxdjfM/l4owiu6MyWggf7uYGMi+2nmclJEn93RqouHDwFQPt lnt/0gqGLFRvXFPyyt8sPwuBkGxft99O9zd65mc6kMifiKNrTggX0riAQ7nRtxfPhOsx BhABLhTifrcqR5GNT1BH3kCqjd+061CEofJkvOunbnC/965bYnu13ZNNIOa2WjIMikXP 9/45/MvxvsitcuSscvb/iD2J/p7Igtgqfh0QZNc6S4MQGXaEzUrVLVOC+0SE7pWXQu6p kX/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772106690; x=1772711490; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Tg5etO1tk6Lt3f6BDEvCCqmunpQhCPFEnQLjlhq8TEw=; b=sLpo5od1yn2VbIUfQuClNBpzZpNhado7s8zor7WMtTbSozQjfCBAcnQFtHjh90vg71 1O+oP/n9Y8Djx/ScoQasbhXXN0zfGBqXULRuHF0ujmeYQyxEgV/DdbJ4E5BdCgu4N4eu AytAICl5sx+vzUvV8qf1HmAY8hZ69XC++oXvje8P94pwufV3+u4QWYh+EItgHIfaPYQe be8CqobEHpzvoTjGPvoFxA4Dv8dJuCR/ZDv6EmKF/wtD2k1UkZVCMam7NORLqJw47A3e lLZEXoRXj0UqfFbYxdCH8IuZVOdklBVkhd8bwDxacCXNJF3uFGSpLLAYMZgLrQ9cSJeH 311A== X-Gm-Message-State: AOJu0YyolOfMAr0NYLwnfOgQsn4bKKSBGvVpQ+6hvguIn+4jMRu5T0A7 mOcTkObFzm3ZFN+6a4Z0mCaKRM6lk90aUE2czhGkVyjgPH1zbSGi3/rbWFpnKA== X-Gm-Gg: ATEYQzxwilM9iPkPpr/07BgtFcqZWiParMBkcvV2BhLeSXIcABUeAI8J2VZbKkITcZZ vz5fVjqfAJssvhvTt+08/ZVkzP/JhOAoh48AYA1giCEKTP+lYxP320wUGEmwAM+E2mw4t41Xvtg s2WVvGZfreYxLoLRxak88RVKPy+RNg1Qp5XGVuY+tbhfCrdMZXEI21GhajIVzKPS2C+Yve9mFVT N6r5N8rXsks42AfxGjypZor8Z/akBtgS3ERGbJwSgSEv4ZI17CfFFW+pjlutGubmRUCvAoeLL5y 1klZC5VTU5HFoIbOnD1a+f0nW8nJiT9mZhT+F4L+m5OywlyUNXgf4Tg+9l81yJIvLgP7NMy2pX0 TEduWjh7TJIL0YQjrMu7GXRpnlA/O5e4fP6yFpmZRj458Qs4RRbeyzOl/SLvK0CBWAp5Gop03ZO yRqVwo3+OJoTQi7jH0KNHYAdsz6ZheW+FZfEJYKtJUhS7ynfcKu2qDtSrKfDrSyHzrmA== X-Received: by 2002:a05:600c:8b02:b0:47d:5e02:14e5 with SMTP id 5b1f17b1804b1-483a95a86eamr340717315e9.5.1772106690170; Thu, 26 Feb 2026 03:51:30 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Alistair Francis , Connor Davis Subject: [PATCH v6 05/14] xen/time: move ticks<->ns helpers to common code Date: Thu, 26 Feb 2026 12:51:05 +0100 Message-ID: <545c2af877d519b1186c79fd6108d33e7e52cd3b.1772016457.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772106725034158500 Content-Type: text/plain; charset="utf-8" ticks_to_ns() and ns_to_ticks() are not architecture-specific, so provide a common implementation that is more resilient to overflow than the historical Arm version. This is not a practical issue for Arm, as the latest ARM ARM that timer frequency should be fixed at 1 GHz and older platforms used much lower rates, which is shy of 32-bit overflow. As the helpers are declared as static inline, they should not affect x86, which does not use them. On Arm, these helpers were historically implemented as out-of-line functions because the counter frequency was originally defined as static and unavaila= ble to headers [1]. Later changes [2] removed this restriction, but the helpers remained unchanged. Now they can be implemented as static inline without any issues. Centralising the helpers avoids duplication and removes subtle differences between architectures while keeping the implementation simple. Drop redundant includes where already pulls it in. No functional change is intended. [1] ddee56dc2994 arm: driver for the generic timer for ARMv7 [2] 096578b4e489 xen: move XEN_SYSCTL_physinfo, XEN_SYSCTL_numainfo and XEN_SYSCTL_topologyinfo to common code Suggested-by: Jan Beulich Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in v4-v6: - Nothing changed. Only rebase. --- Changes in v3: - Add Reviewed-by: Jan Beulich . --- Changes in v2: - Move ns_to_ticks() and ticks_to_ns() to common code. --- xen/arch/arm/include/asm/time.h | 3 --- xen/arch/arm/time.c | 11 ----------- xen/arch/arm/vtimer.c | 2 +- xen/arch/riscv/include/asm/time.h | 5 ----- xen/arch/riscv/time.c | 1 + xen/include/xen/time.h | 11 +++++++++++ 6 files changed, 13 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/include/asm/time.h b/xen/arch/arm/include/asm/tim= e.h index 49ad8c1a6d47..c194dbb9f52d 100644 --- a/xen/arch/arm/include/asm/time.h +++ b/xen/arch/arm/include/asm/time.h @@ -101,9 +101,6 @@ extern void init_timer_interrupt(void); /* Counter value at boot time */ extern uint64_t boot_count; =20 -extern s_time_t ticks_to_ns(uint64_t ticks); -extern uint64_t ns_to_ticks(s_time_t ns); - void preinit_xen_time(void); =20 void force_update_vcpu_system_time(struct vcpu *v); diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index cc3fcf47b66a..a12912a106a0 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -27,7 +27,6 @@ #include #include #include -#include #include =20 uint64_t __read_mostly boot_count; @@ -47,16 +46,6 @@ unsigned int timer_get_irq(enum timer_ppi ppi) return timer_irq[ppi]; } =20 -/*static inline*/ s_time_t ticks_to_ns(uint64_t ticks) -{ - return muldiv64(ticks, SECONDS(1), 1000 * cpu_khz); -} - -/*static inline*/ uint64_t ns_to_ticks(s_time_t ns) -{ - return muldiv64(ns, 1000 * cpu_khz, SECONDS(1)); -} - static __initdata struct dt_device_node *timer; =20 #ifdef CONFIG_ACPI diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index d2124b175521..2e85ff2b6e62 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -12,13 +12,13 @@ #include #include #include +#include #include =20 #include #include #include #include -#include #include #include #include diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm= /time.h index 1e7801e2ea0e..be3875b9984e 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -24,11 +24,6 @@ static inline cycles_t get_cycles(void) return csr_read(CSR_TIME); } =20 -static inline s_time_t ticks_to_ns(uint64_t ticks) -{ - return muldiv64(ticks, MILLISECS(1), cpu_khz); -} - void preinit_xen_time(void); =20 #endif /* ASM__RISCV__TIME_H */ diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index e962f8518d78..2c7af0a5d63b 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -4,6 +4,7 @@ #include #include #include +#include #include =20 unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ diff --git a/xen/include/xen/time.h b/xen/include/xen/time.h index fe0d7a578a99..2185dd26a439 100644 --- a/xen/include/xen/time.h +++ b/xen/include/xen/time.h @@ -8,6 +8,7 @@ #ifndef __XEN_TIME_H__ #define __XEN_TIME_H__ =20 +#include #include #include =20 @@ -75,6 +76,16 @@ extern void send_timer_event(struct vcpu *v); =20 void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds); =20 +static inline s_time_t ticks_to_ns(uint64_t ticks) +{ + return muldiv64(ticks, MILLISECS(1), cpu_khz); +} + +static inline uint64_t ns_to_ticks(s_time_t ns) +{ + return muldiv64(ns, cpu_khz, MILLISECS(1)); +} + #include =20 #endif /* __XEN_TIME_H__ */ --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd68826asm220079295e9.0.2026.02.26.03.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 03:51:30 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7ef86abe-1309-11f1-b164-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772106693; x=1772711493; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WQbN7SP3fjaaAEDIkqEkmnk4ywUJEbwgcsMMvUSaPN0=; b=ceT4UyAZvKTKCGcH9s35BtWNIBBKYwaDKDnDLDlhDBOUtMeDt9SWjpJwoo7FyFP24o TLM87+A6N8iFS1k4km0NeekHUDFh5v/VF/NokR9UjtPnHw9A838Pu4nynv7BHKK6yhF8 tA9nreJa0csrx9g5X8g9880N+v4PuLfWOuBUz9M/cQ5b9+sHSwj58SmRiBZak0mn+8IQ vBUitBNpDCKKbOeCSu34bnqukE9Dj76AUCg60g6PePZxwMxqBv3Du3UGdnYATKJAKWsn ok83wV4Hk9ncIxr/XE3yEmIin/VugFJ2Fkkx/rfRMrKV+dIjZx0VnGRuQy1mI9+mmOw5 /yXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772106693; x=1772711493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=WQbN7SP3fjaaAEDIkqEkmnk4ywUJEbwgcsMMvUSaPN0=; b=vpCQ+cGiEXaJvn6m7xlvsmK+EhdRjcuC/k7Rs40IJsP1iRyKSsxrf6vMSiUWZOmBp8 tzR886kk1wv5mXIpSpr5peC0w0RLPJjONcn3HpdA+hrrZ/fNZ71Dk0ZOBusOU9egD7iY 9lK1tNYUDgMmyR6BvGuXPV9v4o+lmEnGvqZheI5S8WsowoQIpWCy589nR9Huq6Awssp2 hnZd3Go2Gc6S4bxoGEFkD4U5uLMCzR5xB+b1zpsDfzJnxiQNumeSgbRvWFOgczjfJ9Ew /k4YhUot/c1NwETSF59ScHrEOLa4LbbsCVXaKif2JjV4UWcWUVWmxLF9FZ6LFtLUXKPS +uJw== X-Gm-Message-State: AOJu0Ywel0ggIB9upZaem4zAmfdTifIt2WwAZNBPmt74JMS3Bzf87S1G wnze+mCwP9KocFDWKt34dAf0vxZDDpkafAuaFO+smQrOHoJNUyADHEqAs4HkqA== X-Gm-Gg: ATEYQzy/e1HZcPwbIaoGXAmC6YTvrPsqF/OIr/VQcblk62o6UnoCdK8z0UHCknEdXV7 rkJYta2fDvVPl10VAurxpJ275zkh6tF+GBaPP4Qao4M78W30zRU991rANVr0IfM6VKOncVnHtX6 DSe0Vu9U444T5Iajx1W3DGqj+HHry3KIAx1ndU6tlNv889eIiZrFqD0Tti9WXrqBlNn6U6uS1Wu +7kD521+852Us9dL6uRXhPidgwsRAR/pp6VeD5qJGJH6c2Qjqb6/5USWvNstMdXBCg+AiyI9YMW hhhzA6ejhElkdZHJFAekkLoOC16lq6aOZZ3jAplTmoSmacscTySfKlR70sG1suuL8/LEBNb3935 J9gdQvPkpG24JL55FkYSjPAy8hglf6sJ8fK3j+YY55Jco3JM7tvMC+Ik6OMv3bTTEa3dH2fDkZr aHw12ye1j1t/ojcfxi1uXq7Osp4aXLsgYVeOTfPoVEYldjtEPmjh8x8cdLS8PyPcaTw4aHLYCGx iri X-Received: by 2002:a05:600c:4751:b0:475:de12:d3b5 with SMTP id 5b1f17b1804b1-483a963df99mr310294475e9.34.1772106692483; Thu, 26 Feb 2026 03:51:32 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 06/14] xen/riscv: introduce basic vtimer infrastructure for guests Date: Thu, 26 Feb 2026 12:51:06 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772106717052158500 Lay the groundwork for guest timer support by introducing a per-vCPU virtual timer backed by Xen=E2=80=99s common timer infrastructure. The virtual timer is programmed in response to the guest SBI sbi_set_timer() call and injects a virtual supervisor timer interrupt into the vCPU when it expires. While a dedicated struct vtimer is not strictly required at present, it is expected to become necessary once SSTC support is introduced. In particular, it will need to carry additional state such as whether SSTC is enabled, the next compare value (e.g. for the VSTIMECMP CSR) to be saved and restored across context switches, and time delta state (e.g. HTIMEDELTA) required for use cases such as migration. Introducing struct vtimer now avoids a later refactoring. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6: - Nothing changed. Only rebase. --- Changes in v5: - Drop copyright line from asm/vtimer.h. - Add Acked-by: Jan Beulich . --- Changes in v4: - Add vcpu_timer_destroy() to void arch_vcpu_destroy(). --- Changes in v3: - use one container_of() to get vcpu instead of two container_of()s. --- Changes in v2: - Drop domain_vtimer_init() as it does nothing. - Drop "struct vcpu *v;" from struct vtimer as it could be taken from arch_vcpu using container_of(). - Drop vtimer_initialized, use t->status =3D=3D TIMER_STATUS_invalid instead to understand if timer was or wasn't initialized. - Drop inclusion of xen/domain.h as xen/sched.h already includes it. - s/ xen/time.h/ xen.timer.h in vtimer.c. - Drop ULL in if-conidtion in vtimer_set_timer() as with the cast it isn't necessary to have suffix ULL. - Add migrate timer to vtimer_set_timer() to be sure that vtimer will occur on pCPU it was ran, so the signalling to that vCPU will (commonly) be cheaper. - Check if the timeout has already expired and just inject the event in vtimer_vtimer_set_timer(). - Drop const for ticks argument of vtimer_set_timer(). - Merge two patches to one: - xen/riscv: introduce vtimer - xen/riscv: introduce vtimer_set_timer() and vtimer_expired() --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/domain.c | 10 +++- xen/arch/riscv/include/asm/domain.h | 3 ++ xen/arch/riscv/include/asm/vtimer.h | 17 +++++++ xen/arch/riscv/vtimer.c | 71 +++++++++++++++++++++++++++++ 5 files changed, 100 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/include/asm/vtimer.h create mode 100644 xen/arch/riscv/vtimer.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index bc47e83b26d7..ffbd7062e214 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -22,6 +22,7 @@ obj-y +=3D traps.o obj-y +=3D vmid.o obj-y +=3D vm_event.o obj-y +=3D vsbi/ +obj-y +=3D vtimer.o =20 $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 6988d7032059..56b28750d3aa 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 struct csr_masks { register_t hedeleg; @@ -138,11 +139,14 @@ int arch_vcpu_create(struct vcpu *v) =20 vcpu_csr_init(v); =20 + if ( (rc =3D vcpu_vtimer_init(v)) ) + goto fail; + /* - * As the vtimer and interrupt controller (IC) are not yet implemented, + * As interrupt controller (IC) is not yet implemented, * return an error. * - * TODO: Drop this once the vtimer and IC are implemented. + * TODO: Drop this once IC is implemented. */ rc =3D -EOPNOTSUPP; goto fail; @@ -156,6 +160,8 @@ int arch_vcpu_create(struct vcpu *v) =20 void arch_vcpu_destroy(struct vcpu *v) { + vcpu_timer_destroy(v); + vfree((void *)&v->arch.cpu_info[1] - STACK_SIZE); } =20 diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 5373a498d80b..c0de8612cc25 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -8,6 +8,7 @@ #include =20 #include +#include =20 struct vcpu_vmid { uint64_t generation; @@ -49,6 +50,8 @@ struct arch_vcpu { =20 struct cpu_info *cpu_info; =20 + struct vtimer vtimer; + register_t hcounteren; register_t hedeleg; register_t hideleg; diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h new file mode 100644 index 000000000000..111863610a92 --- /dev/null +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ASM__RISCV__VTIMER_H +#define ASM__RISCV__VTIMER_H + +#include + +struct vtimer { + struct timer timer; +}; + +int vcpu_vtimer_init(struct vcpu *v); +void vcpu_timer_destroy(struct vcpu *v); + +void vtimer_set_timer(struct vtimer *t, uint64_t ticks); + +#endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c new file mode 100644 index 000000000000..32d142bcdfcd --- /dev/null +++ b/xen/arch/riscv/vtimer.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +static void vtimer_expired(void *data) +{ + struct vtimer *t =3D data; + struct vcpu *v =3D container_of(t, struct vcpu, arch.vtimer); + + vcpu_set_interrupt(v, IRQ_VS_TIMER); +} + +int vcpu_vtimer_init(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + init_timer(&t->timer, vtimer_expired, t, v->processor); + + return 0; +} + +void vcpu_timer_destroy(struct vcpu *v) +{ + struct vtimer *t =3D &v->arch.vtimer; + + if ( t->timer.status =3D=3D TIMER_STATUS_invalid ) + return; + + kill_timer(&v->arch.vtimer.timer); +} + +void vtimer_set_timer(struct vtimer *t, const uint64_t ticks) +{ + struct vcpu *v =3D container_of(t, struct vcpu, arch.vtimer); + s_time_t expires =3D ticks_to_ns(ticks - boot_clock_cycles); + + vcpu_unset_interrupt(v, IRQ_VS_TIMER); + + /* + * According to the RISC-V sbi spec: + * If the supervisor wishes to clear the timer interrupt without + * scheduling the next timer event, it can either request a timer + * interrupt infinitely far into the future (i.e., (uint64_t)-1), + * or it can instead mask the timer interrupt by clearing sie.STIE C= SR + * bit. + */ + if ( ticks =3D=3D ((uint64_t)~0) ) + { + stop_timer(&t->timer); + + return; + } + + if ( expires < NOW() ) + { + /* + * Simplify the logic if the timeout has already expired and just + * inject the event. + */ + stop_timer(&t->timer); + vcpu_set_interrupt(v, IRQ_VS_TIMER); + + return; + } + + migrate_timer(&t->timer, smp_processor_id()); + set_timer(&t->timer, expires); +} --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772106717; cv=none; d=zohomail.com; s=zohoarc; b=eAFaiHcrVIaqMtngTYyWMIyFO1d2qXqPn/MCVm8woqFN/DQp+bWjrJpwCdi4OdGV7ZA9xZI9mqcI99pLo0wwlmO8za4hO7kry+WeokhIYvdjpP6159zcVPhFjPKnKLZs3XkqtfRgZW1O7jmk4DmY7RZ+HX2jkRgJ48kQLZdprrc= ARC-Message-Signature: i=1; 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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd68826asm220079295e9.0.2026.02.26.03.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 03:51:33 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7fee7579-1309-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772106694; x=1772711494; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y1ZCln4LGxYbhh7EA/lAbVEGbnMzo0d9tLUWjs8DB5k=; b=eG2HjWeSENtDPApqBcBWK2jpmataLLKC6cZ4NeqLfxqspG2mlw9dQinywOb05UDLqj nzlP9zuzAtslAYo1pP0jHiCJRyT43HSiBMn8gMzKR62IFiTXZWAwYSHmyr8U+6rN37JY 88GMVCYDw2mPtk3+6OVjVp0CflmygO1Q8/DWum1DaWe3Q4gpJtZd+RCile2VSTub67rD jwvYZxkAp1HWEEb2/kX/wJtr3MplsGBcu6DZzTgEPM2BiOze122EqQlOiGLKsmWVvK6z oxJuUmvxSaktKl0iWKBAuLHtEpJyEmOwrkuBPm0G84htLnV/pLDNhCqe/xoDPsSPOkj/ EgVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772106694; x=1772711494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Y1ZCln4LGxYbhh7EA/lAbVEGbnMzo0d9tLUWjs8DB5k=; b=Enqva28TnEHqbLARebVIfr6FviGa/LCWpWBrsNQ9cPdLv/dzjV/ymR/9iREIgceA/D SToceblLQi3RHkXehsCZHM8KLe5C3052wqf65Kv61CIgaA3ICd3uprdve83q22jtOzQJ WA57mmhlNT7Druy5xrnTbRg/5HaWB986YX7F3Ogti7A/BqEoJwnbM1UbK4KeUYMTy3Ke iKi25mP35IhV0/uBaOZoaVMKi3OtDK03NT/Rts6OaS/Pzb6PoOTuLonZo1eor9D2Fi4X Gw89w8IA0AvuwyTo+mc/xWebN+kIMNIFhCVmAZlEops4LloF7/wu07U+UWvFFOvmmN5i XSjg== X-Gm-Message-State: AOJu0YwdI6X1loYif8CjIbJdSX6Cf5MWys+TEhCd8SoeZbtEHQj85LI0 g8IOTYcKUx+x/krhgkfH1kxl6p1CK9cdAHKd/zHdVDlauCTRSRlNXSIKHu7W3A== X-Gm-Gg: ATEYQzzJxUkV6+hALaa5ld5euAlanFGq8GuPtFqHFcZO24Ol2CT+rKhyNV7zcbexFsd quOkCJ8VFnmX8pgDX9Miu1z2r3wS8LYEAI/722F0OMc4+K80K07Tl9JpNXA6oQqZ5wozMLyRtAE M0TKbP3nSa/YP2U4Y8M06d3bOJW/pDv9i7AHxN8Py+xr4YudgdlkhL1OflVe38QZ4mbJx1fhO6F UiqCnAQAyQ+If/k3nAPJw9XM2+aZAHnGN3Y+6/pPs3sQvkhyHigHP02CELmSfo9OAtogAP1E5DD qUYAq9VwqQtTQr9CQJPMwrdgaTrl688q3xsiCxd6ac1/3zotb/qjUCfPfCcKmA0Hk4a1O6BV5oP Vuv5uZw0lCC4tiNPC3f68kiCcJHY9TLYqlfqGtV9dSS8c6zQbBbTq/h2lai7v7YesNzNaRYwiHZ lVJPhb0Q4VeTU9X3LSshx2ssImp06BOG8g1V5fDKoQf08/QltGrkcepcasL5mD4FOEzA== X-Received: by 2002:a05:600c:8b16:b0:480:68ed:1e70 with SMTP id 5b1f17b1804b1-483a963de73mr420137245e9.35.1772106693973; Thu, 26 Feb 2026 03:51:33 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 07/14] xen/riscv: introduce vcpu_kick() implementation Date: Thu, 26 Feb 2026 12:51:07 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772106719155158500 Content-Type: text/plain; charset="utf-8" Add a RISC-V implementation of vcpu_kick(), which unblocks the target vCPU and sends an event check IPI if the vCPU was running on another processor. This mirrors the behavior of Arm and enables proper vCPU wakeup handling on RISC-V. Remove the stub implementation from stubs.c, as it is now provided by arch/riscv/domain.c. Since vcpu_kick() calls perfc_incr(vcpu_kick), add perfcounter for vcpu_kick to handle the case when CONFIG_PERF_COUNTERS=3Dy. Although CONFIG_PERF_COUNTERS is not enabled by default, it can be enabled, for example, by randconfig what will lead to CI build issues. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4-v6: - Nothing changed. Only rebase. --- Changes in v3: - Add asm/perfc_defn.h to provide vcpu_kick perfcoounter to cover the case when CONFIG_PERF_COUNTERS=3Dy. --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/domain.c | 14 ++++++++++++++ xen/arch/riscv/include/asm/Makefile | 1 - xen/arch/riscv/include/asm/perfc_defn.h | 3 +++ xen/arch/riscv/stubs.c | 5 ----- 4 files changed, 17 insertions(+), 6 deletions(-) create mode 100644 xen/arch/riscv/include/asm/perfc_defn.h diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index 56b28750d3aa..fda8cff90f6a 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include #include #include +#include #include =20 #include @@ -265,6 +267,18 @@ void vcpu_flush_interrupts(struct vcpu *v) #endif } =20 +void vcpu_kick(struct vcpu *v) +{ + bool running =3D v->is_running; + + vcpu_unblock(v); + if ( running && v !=3D current ) + { + perfc_incr(vcpu_kick); + smp_send_event_check_mask(cpumask_of(v->processor)); + } +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/a= sm/Makefile index 3824f31c395c..86c56251d5d7 100644 --- a/xen/arch/riscv/include/asm/Makefile +++ b/xen/arch/riscv/include/asm/Makefile @@ -7,7 +7,6 @@ generic-y +=3D hypercall.h generic-y +=3D iocap.h generic-y +=3D irq-dt.h generic-y +=3D percpu.h -generic-y +=3D perfc_defn.h generic-y +=3D random.h generic-y +=3D softirq.h generic-y +=3D vm_event.h diff --git a/xen/arch/riscv/include/asm/perfc_defn.h b/xen/arch/riscv/inclu= de/asm/perfc_defn.h new file mode 100644 index 000000000000..8a4b945df662 --- /dev/null +++ b/xen/arch/riscv/include/asm/perfc_defn.h @@ -0,0 +1,3 @@ +/* This file is intended to be included multiple times. */ + +PERFCOUNTER(vcpu_kick, "vcpu: notify other vcpu") diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index daadff0138e4..eedf8bf9350a 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -203,11 +203,6 @@ void vcpu_block_unless_event_pending(struct vcpu *v) BUG_ON("unimplemented"); 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At present, vtimer_ctxt_switch_from() is a no-op because the RISC-V SSTC extension, which provides a virtualization-aware timer, is not yet supported. Xen therefore relies the virtual (SBI-based) timer. The virtual timer uses Xen's internal timer infrastructure and must be associated with the pCPU on which the vCPU is currently running so that timer events can be delivered efficiently. As a result, vtimer_ctxt_switch_= to() migrates the timer to the target pCPU when a vCPU is scheduled in. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4-v6: - Nothing changed. Only rebase. --- Changes in v3: - s/vtimer_ctx_switch_to/vtimer_ctxt_switch_to - s/vtimer_ctx_switch_from/vtimer_ctxt_switch_from - Add Acked-by: Jan Beulich . --- Changes in v2: - Align the parameters names for vtimer_ctx_switch_from() and vtimer_ctx_= switch_to() in declarations to match the ones in the defintions to make Misra happy. - s/vtimer_save/vtimer_ctx_switch_from. - s/vtimer_restore/vtimer_ctx_switch_to. - Update the commit message. --- xen/arch/riscv/include/asm/vtimer.h | 3 +++ xen/arch/riscv/vtimer.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/xen/arch/riscv/include/asm/vtimer.h b/xen/arch/riscv/include/a= sm/vtimer.h index 111863610a92..b4d48d1a1732 100644 --- a/xen/arch/riscv/include/asm/vtimer.h +++ b/xen/arch/riscv/include/asm/vtimer.h @@ -14,4 +14,7 @@ void vcpu_timer_destroy(struct vcpu *v); =20 void vtimer_set_timer(struct vtimer *t, uint64_t ticks); =20 +void vtimer_ctxt_switch_from(struct vcpu *p); +void vtimer_ctxt_switch_to(struct vcpu *n); + #endif /* ASM__RISCV__VTIMER_H */ diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index 32d142bcdfcd..afd8a53a7387 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ =20 +#include #include #include =20 @@ -69,3 +70,17 @@ void vtimer_set_timer(struct vtimer *t, const uint64_t t= icks) migrate_timer(&t->timer, smp_processor_id()); set_timer(&t->timer, expires); } + +void vtimer_ctxt_switch_from(struct vcpu *p) +{ + ASSERT(!is_idle_vcpu(p)); + + /* Nothing to do at the moment as SSTC isn't supported now. */ +} + +void vtimer_ctxt_switch_to(struct vcpu *n) +{ + ASSERT(!is_idle_vcpu(n)); + + migrate_timer(&n->arch.vtimer.timer, n->processor); +} --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772106724; cv=none; d=zohomail.com; s=zohoarc; b=VHxjRt+1crzfyvCQbWxOkBajY99f6IUch2VX4Vsb6ijE/o0OCMhtVrAf2TpZdD6lf5cY6JMJ9DtWZHqJBkOGmNjOP7nV+lDRvPBLms02VycWpmDe72rmA2XVRHLUZmH+NME2NtIFyJmF5niu2KjigzGhLle+SyPMHEaenpXfi6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772106724; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YPVdYf1isxzjgFuoXm9FNs+0/fH+qzHDGQJ001Hb8No=; b=bVP60t14/qQrJBIvW777s2R5KJIhfv5QGvQdVoPOJslZ1eh9hemZTrTvcn0eGrmiomt2u9/GBn/68YxXYpF+U1dXs9ohW2rvUU8NknJW9clo3Vk+o+pIfXdze2yihXvV9jrAs9DEQXKr0HRXRlI7RHtZHxyHiIhNuetTTyrZmHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772106724249690.6836763256807; Thu, 26 Feb 2026 03:52:04 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1241460.1542553 (Exim 4.92) (envelope-from ) id 1vvZu7-00088X-5j; Thu, 26 Feb 2026 11:51:39 +0000 Received: by outflank-mailman (output) from mailman id 1241460.1542553; Thu, 26 Feb 2026 11:51:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZu7-00088A-2c; Thu, 26 Feb 2026 11:51:39 +0000 Received: by outflank-mailman (input) for mailman id 1241460; Thu, 26 Feb 2026 11:51:38 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZu5-0006E8-TY for xen-devel@lists.xenproject.org; Thu, 26 Feb 2026 11:51:37 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 813fca0c-1309-11f1-b164-2bf370ae4941; Thu, 26 Feb 2026 12:51:37 +0100 (CET) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4834826e5a0so8712645e9.2 for ; Thu, 26 Feb 2026 03:51:37 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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The handler now programs the vCPU=E2=80=99s virtual timer via vtimer_set_timer() and returns SBI_SUCCESS. This enables guests using the legacy SBI timer interface to schedule timer events correctly. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3-v6: - Nothing changed. Only rebase. --- Changes in v2: - Add Acked-by: Jan Beulich . --- xen/arch/riscv/vsbi/legacy-extension.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/riscv/vsbi/legacy-extension.c b/xen/arch/riscv/vsbi/l= egacy-extension.c index 2e8df191c295..090c23440cea 100644 --- a/xen/arch/riscv/vsbi/legacy-extension.c +++ b/xen/arch/riscv/vsbi/legacy-extension.c @@ -7,6 +7,7 @@ =20 #include #include +#include =20 static void vsbi_print_char(char c) { @@ -44,6 +45,11 @@ static int vsbi_legacy_ecall_handler(unsigned long eid, = unsigned long fid, ret =3D SBI_ERR_NOT_SUPPORTED; break; =20 + case SBI_EXT_0_1_SET_TIMER: + vtimer_set_timer(¤t->arch.vtimer, regs->a0); + regs->a0 =3D SBI_SUCCESS; + break; + default: /* * TODO: domain_crash() is acceptable here while things are still = under --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772106727; cv=none; d=zohomail.com; s=zohoarc; b=c4kkFio9a+CWLwrELOWTgXTnkNXo7nArtFgUVkMFFUhtc8QJckjzewqE+p7vQpbyxAqwbFZRiT7XzzHTLDIpZvx19wjKngxBt/Q5qyPxKqunaclQMkprSXmRS01hTBP7AOROnk9qLEq+Zy1PfKGL93/qfot2tTrQP31xiiMxKIQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772106727; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5K7jSa5ElCzdAIrKGdTJ7REReHRZ8bMvKPzPSDPHE2w=; b=dI2VjGJNGVpJRUwcu4Eggm5S7TaQkaH4tw3hNsksgKuqWGc7KFoMwN90Obzqh+z7k22EJY47y74kUjvc/RQr71kMShGwv/smnKBwIAWYZFllkMTbuPQqoy0zwNC43So2VeGWSsUrNJNqV4QYG8KNVobT15QdpzeRXttghdni7UU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772106727052915.2371640541709; Thu, 26 Feb 2026 03:52:07 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1241465.1542574 (Exim 4.92) (envelope-from ) id 1vvZuA-0000JG-3B; Thu, 26 Feb 2026 11:51:42 +0000 Received: by outflank-mailman (output) from mailman id 1241465.1542574; Thu, 26 Feb 2026 11:51:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZu9-0000IO-Tz; Thu, 26 Feb 2026 11:51:41 +0000 Received: by outflank-mailman (input) for mailman id 1241465; Thu, 26 Feb 2026 11:51:40 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZu8-0006EH-Lp for xen-devel@lists.xenproject.org; Thu, 26 Feb 2026 11:51:40 +0000 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [2a00:1450:4864:20::333]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 81f1a138-1309-11f1-9ccf-f158ae23cfc8; Thu, 26 Feb 2026 12:51:38 +0100 (CET) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-48372efa020so6535065e9.2 for ; Thu, 26 Feb 2026 03:51:38 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd68826asm220079295e9.0.2026.02.26.03.51.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 03:51:37 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 81f1a138-1309-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772106697; x=1772711497; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5K7jSa5ElCzdAIrKGdTJ7REReHRZ8bMvKPzPSDPHE2w=; b=BlritWwLH0Oix637nUS19EKZuNhonSpPTeOta/484dHWjyvEiiq+Qf/j6/IbkArtC0 qqoaDup3MvTLVsdwiJ4BooHpmY2Wuka/mP82M9JpGA6GJx4W0ftWRp1w4fu1nTM2LvaV qTnQDmvngw+XErcc+MTCsUW5umZc8OYQIRxmMAtU3iwBSRXnQB6+N4LJHfKZ38zmQWQX LQWQS52kDayk4NYpBxo62cMbv0XLdt1x4b/w75D0KJyOo8HprNMDBbj1C5ARdo8cnLmb oc1BezGzHq+FkD4EyDvhV5jzTigrl9RLktRB1DySwF4eytuGklBf4MXCD69b/jHmzDIJ f6+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772106697; x=1772711497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5K7jSa5ElCzdAIrKGdTJ7REReHRZ8bMvKPzPSDPHE2w=; b=KSZFnEZTV1YmiDeIgbnqYfX/w5UmJq5dvFJYBcw0SBa6jwoJb70mtpOLhkU4O/K2u8 HPqcPqOJOGnKmtJzhpDIP+TQnhSfbpwFdChT2MED+UnZYUjcTzdnP79/7q+5vwgNlNXm /QF2Xv9WblOuqSdYueHULQNwAu4eqDK91dpMHl6QzCmnFCtEjIxC71nhfJmNh35VR4cL zi7F33v1w4657cxamGJwKg+Vwaz1HOEbIemLBYtFqbE6clOfu0Tf+Ot/O0HT/qXG/Dwn /EZLDXQLiKUsAtRAZKxWV7QqHYfh8qSIeQAoUYWwXBybODFLzB39jITn7iqtiSx2OA7H ecBg== X-Gm-Message-State: AOJu0YxobSNn557v7NuGNHlucey6AfSPBgyaAjzordWpD9F2+FpzZTBO zjPsOB2HeV8/wADvtxiIhiMu/Tdh6L/qL5OQZiYs4sDFb9fC5ohxd+S14rf+hw== X-Gm-Gg: ATEYQzx2AjoDfn5ubeXoXz0k/fczU8EqJLTpvl8aIoXJEPiL4SNC1S2pMmqxmMymfWu gGWnmp7H/6S7tEjDE2Wst8tQnSwHBiLmF5FoZKpWjZaV3kXGEDC5RqYrIpvYfkl9gJemw/zmr+6 TnME6rvfmoVcPW8MXW9AjiQp+sV1Um2mN8YIoGPYo3bquObz9JasZftvj9IecFmPPTdQYql4V8r 2jZs3vH0FWapO5dNy9xRW7uuYDp/Yi1TMc7G5W4dX88ZmVDcF4KnnN5WwOidovWLejH6bB0DMvH 6HOPcRSFJFHrrwUvD3t9gCFjwTg9ljR/4g/gaW2aUwtXl1NL0W787EDX0n+JDjlKn4eJnyO3KJa TaPerCxD50sttMe1iKJ0cQrqio4XZwpiXx+K5/3CkVLJu00CFXNWKtxJJ/4ByS4IJH9oYTsbhEI TI+fOCJ6enp/Br0HZzrQQoRQcOR67Vp0ybBs/OYH1px/uu8leQ616RoR2dOqJMqYvoKg== X-Received: by 2002:a05:600c:548a:b0:483:b2a8:33ff with SMTP id 5b1f17b1804b1-483c216bdefmr63756335e9.4.1772106697348; Thu, 26 Feb 2026 03:51:37 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 10/14] xen/riscv: introduce sbi_set_timer() Date: Thu, 26 Feb 2026 12:51:10 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772106729209158500 Introduce a function pointer for sbi_set_timer(), since different OpenSBI versions may implement the TIME extension with different extension IDs and/or function IDs. If the TIME extension is not available, fall back to the legacy timer mechanism. This is useful when Xen runs as a guest under another Xen, because the TIME extension is not currently virtualised and therefore will not appear as available. Despite of the fact that sbi_set_timer_v01 is introduced and used as fall back, SBI v0.1 still isn't fully supported (with the current SBI calls usage, sbi_rfence_v01 should be introduced too), so panic() in sbi_init() isn't removed. The sbi_set_timer() pointer will be used by reprogram_timer() to program Xen=E2=80=99s physical timer as without SSTC extension there is no any other option except SBI call to do that as only M-timer is available for us. Use dprintk() for all the cases to print that a speicifc SBI extension is available as it isn't really necessary in case of release builds. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6: - Nothing changed. Only rebase. --- Changes in v5: - Add inclusion of to to deal with the compila= tion issue: ./arch/riscv/include/asm/sbi.h:156:30: error: expected ')' before 'sbi_= set_timer' 156 | extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value= ); - Rephrase the first sentence of the comment above declaration of sbi_set_t= imer pointer to function. --- Changes in v4: - Add "stime_value is in absolute time" to the comment above declaration of sbi_set_timer() function pointer. - Add Acked-by: Jan Beulich . --- Changes in v3: - Init sbi_set_timer with sbi_set_timer_v01 as fallback value. - Sort SBI IDs in the same way as SBI EXT IDs are declared. - Add __ro_after_init for sbi_set_timer variable. - use dprintk instead of printk to print information if SBI ext is availab= le. --- Changes in v2: - Move up defintion of SBI_EXT_TIME_SET_TIMER and use the same padding as defintions around it. - Add an extra comment about stime_value granuality above declaration of sbi_set_timer function pointer. - Refactor implemetation of sbi_set_timer_v02(). - Provide fallback for sbi_set_timer_v01(). - Update the commit message. --- xen/arch/riscv/include/asm/sbi.h | 22 ++++++++++++++++++ xen/arch/riscv/sbi.c | 40 +++++++++++++++++++++++++++++++- 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index 79f7ff5c5501..ed7af200288f 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -13,6 +13,7 @@ #define ASM__RISCV__SBI_H =20 #include +#include =20 /* SBI-defined implementation ID */ #define SBI_XEN_IMPID 7 @@ -29,6 +30,7 @@ =20 #define SBI_EXT_BASE 0x10 #define SBI_EXT_RFENCE 0x52464E43 +#define SBI_EXT_TIME 0x54494D45 =20 /* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 @@ -48,6 +50,9 @@ #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5 #define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6 =20 +/* SBI function IDs for TIME extension */ +#define SBI_EXT_TIME_SET_TIMER 0x0 + #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f000000 #define SBI_SPEC_VERSION_MINOR_MASK 0x00ffffff =20 @@ -134,6 +139,23 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, = vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); =20 +/* + * Programs the clock for next event at (or after) stime_value. stime_valu= e is + * in absolute time. This function must clear the pending timer interrupt = bit + * as well. + * + * If the supervisor wishes to clear the timer interrupt without schedulin= g the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific nega= tive + * error code. + */ +extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); + /* * Initialize SBI library * diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index 425dce44c679..b4a7ae6940c1 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -249,6 +249,38 @@ static int (* __ro_after_init sbi_rfence)(unsigned lon= g fid, unsigned long arg4, unsigned long arg5); =20 +static int cf_check sbi_set_timer_v02(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +static int cf_check sbi_set_timer_v01(uint64_t stime_value) +{ + struct sbiret ret; + + ret =3D sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, +#ifdef CONFIG_RISCV_32 + stime_value >> 32, +#else + 0, +#endif + 0, 0, 0, 0); + + return sbi_err_map_xen_errno(ret.error); +} + +int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) =3D sbi_set_ti= mer_v01; + int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -324,7 +356,13 @@ int __init sbi_init(void) if ( sbi_probe_extension(SBI_EXT_RFENCE) > 0 ) { sbi_rfence =3D sbi_rfence_v02; - printk("SBI v0.2 RFENCE extension detected\n"); + dprintk(XENLOG_INFO, "SBI v0.2 RFENCE extension detected\n"); + } + + if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) + { + sbi_set_timer =3D sbi_set_timer_v02; + dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); 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The privileged architecture only defines machine-mode timer interrupts (using mtime/mtimecmp). Therefore, timer services for S/HS/VS mode must be provided by M-mode via SBI calls. SSTC (Supervisor-mode Timer Control) is optional and is not supported on the boards available to me, so the only viable approach today is to program the timer through SBI. reprogram_timer() enables/disables the supervisor timer interrupt and programs the next timer deadline using sbi_set_timer(). If the SBI call fails, the code panics, because sbi_set_timer() is expected to return either 0 or -ENOSUPP (this has been stable from early OpenSBI versions to the latest ones). The SBI spec does not define a standard negative error code for this call, and without SSTC there is no alternative method to program the timer, so the SBI timer call must be available. reprogram_timer() currently returns int for compatibility with the existing prototype. While it might be cleaner to return bool, keeping the existing signature avoids premature changes in case sbi_set_timer() ever needs to return other values (based on which we could try to avoid panic-ing) in the future. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v5 - v6: - Nothing changed. Only rebase. --- Changes in v4: - Add Acked-by: Jan Beulich . --- Changes in v3: - Correct the comments in reprogram_timer(). - Move enablement of timer interrupt after sbi_set_timer() to avoid potentially receiving a timer interrupt between these 2 operations. --- Changes in v2: - Add TODO comment above sbi_set_timer() call. - Update the commit message. --- xen/arch/riscv/stubs.c | 5 ----- xen/arch/riscv/time.c | 43 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 5 deletions(-) diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index eedf8bf9350a..2f3a0ce76af9 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -21,11 +21,6 @@ nodemask_t __read_mostly node_online_map =3D { { [0] =3D= 1UL } }; =20 /* time.c */ =20 -int reprogram_timer(s_time_t timeout) -{ - BUG_ON("unimplemented"); -} - void send_timer_event(struct vcpu *v) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 2c7af0a5d63b..7efa76fdbcb1 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,6 +7,9 @@ #include #include =20 +#include +#include + unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 @@ -40,6 +43,46 @@ static void __init preinit_dt_xen_time(void) cpu_khz =3D rate / 1000; } =20 +int reprogram_timer(s_time_t timeout) +{ + uint64_t deadline, now; + int rc; + + if ( timeout =3D=3D 0 ) + { + /* Disable timer interrupt */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; + } + + deadline =3D ns_to_ticks(timeout) + boot_clock_cycles; + now =3D get_cycles(); + if ( deadline <=3D now ) + return 0; + + /* + * TODO: When the SSTC extension is supported, it would be preferable = to + * use the supervisor timer registers directly here for better + * performance, since an SBI call and mode switch would no longer + * be required. + * + * This would also reduce reliance on a specific SBI implementat= ion. + * For example, it is not ideal to panic() if sbi_set_timer() re= turns + * a non-zero value. Currently it can return 0 or -ENOSUPP, and + * without SSTC we still need an implementation because only the + * M-mode timer is available, and it can only be programmed in + * M-mode. + */ + if ( (rc =3D sbi_set_timer(deadline)) ) + panic("%s: timer wasn't set because: %d\n", __func__, rc); + + /* Enable timer interrupt */ + csr_set(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + return 1; +} + void __init preinit_xen_time(void) { if ( acpi_disabled ) --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772106727; cv=none; d=zohomail.com; s=zohoarc; b=GwC0d5mVPNVTVECe2la1w46AKaMXVELQVjCdjYRdKEiYUjAKDW2TBMWKqiM32VPSAPp1+AkOQUWYJAmqtSnzV3u+NV7FYQGUcUINy5toiQcN0dq0L5KQanlMdEzRHGzanhW1kkEgGglYzZGGyYDukj7x6I6wy/DHQYBvltbRjSc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772106727; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZhCTeImiDeyxrLk5y++AZ4LSK5JxMOQ72SQ4iMIQuPE=; b=HlDKR6tUr7TjqTZapHPo0m5Dm9DQUOZCIVovR5Uyd1uKKMVosVlLCOXUfkEgagY8uQRGzSb3m7bsMIEfgWPMT7PyPdaVDanmMA7Y8u1APIHjgARadUUKkwmg+q4zb8OE9TPr/cWunYA6rwmUxMlzkQxYxpbihs1Bn+UMBnc2Tsg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772106727926811.6236256856338; Thu, 26 Feb 2026 03:52:07 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1241468.1542590 (Exim 4.92) (envelope-from ) id 1vvZuB-0000hs-S6; Thu, 26 Feb 2026 11:51:43 +0000 Received: by outflank-mailman (output) from mailman id 1241468.1542590; Thu, 26 Feb 2026 11:51:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZuB-0000go-MK; Thu, 26 Feb 2026 11:51:43 +0000 Received: by outflank-mailman (input) for mailman id 1241468; Thu, 26 Feb 2026 11:51:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZuA-0006EH-Gy for xen-devel@lists.xenproject.org; Thu, 26 Feb 2026 11:51:42 +0000 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [2a00:1450:4864:20::32c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 83963750-1309-11f1-9ccf-f158ae23cfc8; Thu, 26 Feb 2026 12:51:41 +0100 (CET) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4806cc07ce7so9144315e9.1 for ; Thu, 26 Feb 2026 03:51:41 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. 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The handler disables further timer interrupts by clearing SIE.STIE and raises TIMER_SOFTIRQ so the generic timer subsystem can perform its processing. Update do_trap() to dispatch IRQ_S_TIMER to this new handler. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4-v6: - Nothing changed. Only rebase. --- Changes in v3: - add Acked-by: Jan Beulich . --- Changes in v2: - Drop cause argument of timer_interrupt() as it isn't used inside the function and anyway it is pretty clear what is the cause inside timer_interrupt(). --- xen/arch/riscv/traps.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 244264c92a79..326f2be62823 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 #include #include @@ -180,6 +181,15 @@ static void check_for_pcpu_work(void) p2m_handle_vmenter(); } =20 +static void timer_interrupt(void) +{ + /* Disable the timer to avoid more interrupts */ + csr_clear(CSR_SIE, BIT(IRQ_S_TIMER, UL)); + + /* Signal the generic timer code to do its work */ + raise_softirq(TIMER_SOFTIRQ); +} + void do_trap(struct cpu_user_regs *cpu_regs) { register_t pc =3D cpu_regs->sepc; @@ -221,6 +231,10 @@ void do_trap(struct cpu_user_regs *cpu_regs) intc_handle_external_irqs(cpu_regs); break; =20 + case IRQ_S_TIMER: + timer_interrupt(); + break; + default: intr_handled =3D false; break; --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772106723; cv=none; d=zohomail.com; s=zohoarc; b=RFS4UDgq431r5w5HqucYOvvjxH66xk+jgr16UciXqQyZt7GBj/mNdnvyoH1c40fNyR0sm26gQAUWMJAHsZEnjb8vX9Boqge3qp8657ixMWiWjkxlp6cla8TNaHrMDAG3C5dxMga8Gld0LctWXncymIYVc7kc/+IOqWL6BBcYiSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772106723; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EaQEBFzhV9Xkezeed5Ppkja6vI/PHHkt+nSsCnYzAYc=; b=dz0zTkSYegkCzFG7l1x6aLNyeCGSZ5/W+yP74JMd7nUaqkS+b6ggEfgJBBmIeoo2ySW8JD+iso5vk9HgXTINqieO6cANZX+zJ1x05LskntyuG0H2rxQvi3XdINwxc4eNUKhYSo4DpuYiJWqA02MIsn+bcZlHD7kt8/TxhreHqV4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 177210672321787.01070868785109; Thu, 26 Feb 2026 03:52:03 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1241470.1542601 (Exim 4.92) (envelope-from ) id 1vvZuD-00017Q-C3; Thu, 26 Feb 2026 11:51:45 +0000 Received: by outflank-mailman (output) from mailman id 1241470.1542601; Thu, 26 Feb 2026 11:51:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZuD-00016W-7L; Thu, 26 Feb 2026 11:51:45 +0000 Received: by outflank-mailman (input) for mailman id 1241470; Thu, 26 Feb 2026 11:51:44 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZuB-0006EH-Vt for xen-devel@lists.xenproject.org; Thu, 26 Feb 2026 11:51:43 +0000 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [2a00:1450:4864:20::332]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 84475c12-1309-11f1-9ccf-f158ae23cfc8; Thu, 26 Feb 2026 12:51:42 +0100 (CET) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-48336a6e932so4567215e9.3 for ; Thu, 26 Feb 2026 03:51:42 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd68826asm220079295e9.0.2026.02.26.03.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 03:51:40 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 84475c12-1309-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772106701; x=1772711501; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EaQEBFzhV9Xkezeed5Ppkja6vI/PHHkt+nSsCnYzAYc=; b=Lh+wHAjidi/c6fhvmhBenkQmZCrY7dJf+E6qWE85oxqp/GAlwjF4Axq54RxctUQ3Ro ZqkRNxPjgn17XHzeKGOxdJc8hPzDhOUln1bCbcZPhN2+ZxPgdqACE237KJ7JGVNOGoLn 4hxHa0LdyPTHtycsaRlIpOG6V5r0+F3Lst8wKunK3ngheQ0Z5FYnH7E684tiGnnZS8Z6 qpDojKk/GFG567kFw+0hmk6qukWqcgYkfirlJMXFo8FdW6yAjZ2xkWOhGOTM5dtYVnhK YVU7A65smtY7263NV3oTLy88uVFucdIvL3FU0L3trvpOaXotudbfyReip8XU+hB+900m PjbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772106701; x=1772711501; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=EaQEBFzhV9Xkezeed5Ppkja6vI/PHHkt+nSsCnYzAYc=; b=ZWExT6PVnh2Kfi+NLOsah7XjUoNsXF/hXM0C6iDJT92B+Pahgt5pH4b5NiGu71YWmU FOpee86pBhjmN+zJA72zJGB14ux7XZkp7XnOyE8I5Be1nhhGD75PR+nuKpPyzF2YYPZQ yIGDHzIHdj6GQSncfrkLTgDEPp5cG76rdaZLFEiXvDH7JNlbWYrmokRjDZz04+wp9KtA 56F38BfR6LUe8+ivEN8YosytDoCMr9cSuObRODvS2lTjYCQm75VpQ+98EYsfcnj3Za5F 68E3mWZv+7gP6xyLS5AjT4P6qI3fLzaaxrcgjTZ03V2g8/fF3lhk3t0yjOtM0loDTfBy 7YQQ== X-Gm-Message-State: AOJu0YzZpTzA1WdnYZzlAnNhYQXFo1VhlGAAdY5/PFNpsRstX4KDD9W+ EeqgixRJX4Q6vmUcSEoqwEriAO99jAuOYiF3YXT4wFucbiir+wZqVdZ4BhcsiA== X-Gm-Gg: ATEYQzyxt9KAl4OII3X68gTGu7ox14ggxW+F5ZJtYvrYwi8CE2fZnNnFtHMeUf3rSMc rMjA+oRHPbuO0yE8iwwaD8a1J2L6Xz3xvxr6PFcZsZbBr4EzSQZrtQQtwge9rKlpA2mR5zheh9i Cmu3JFlDQLJG9R5cJt7UH4yQVrOALVrTkIGbc5Yb+s5LqH13Gy69GQc0u19+44+xfXjcSb97G47 gk+FW1ftijfJVDgOosPK6gmlX+HUagsAKCk/RZJbxZ3YmMQy9WAi8Vjr1KXUnAAWdS/DKkR/zuR VTxQEz1h2WSWBNO7DC+5In8y5odqBoWTDTgfPm1SHPgRJ/yx1UJFICDl1yim2yiSJIEPKyEZ4us kagi1FgxV2c6GXCKtl2HCMU3iwxZZODAbFYsVmuM7C4EtPR7BD9SBg3HmOhWQPi6HDsJsb1ccI0 nwTUJUPyzBZr6m4j3g1w3i+ZAnAsz8SNtAyq5cqNKnj6q+j9R9UU+xfodZcI3KuMVDpdOQR61pB zZEzaYQ X-Received: by 2002:a05:600c:8708:b0:483:a922:2e8d with SMTP id 5b1f17b1804b1-483c216ab55mr57972105e9.4.1772106701281; Thu, 26 Feb 2026 03:51:41 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 13/14] xen/riscv: init tasklet subsystem Date: Thu, 26 Feb 2026 12:51:13 +0100 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772106724978158500 Content-Type: text/plain; charset="utf-8" As the tasklet subsystem is now initialized, it is necessary to implement sync_local_execstate(), since it is invoked when something calls tasklet_softirq_action(), which is registered in tasklet_subsys_init(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6: - Nothing changed. Only rebase. --- Changes in v5: - It was something wrong with prev. rebase. So fix that and move removing of sync_local_execstate() and sync_vcpu_execstate() to the next patch. --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - add Acked-by: Jan Beulich . --- Changes in v2: - Update the commit message. - Move implementation of sync_vcpu_execstate() to separate commit as it doesn't connect to tasklet subsystem. --- xen/arch/riscv/setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index bca6ca09eddd..cae49bb29626 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -133,6 +134,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, panic("Booting using ACPI isn't supported\n"); } =20 + tasklet_subsys_init(); + init_IRQ(); =20 riscv_fill_hwcap(); --=20 2.53.0 From nobody Tue Mar 3 03:02:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1772107092; cv=none; d=zohomail.com; s=zohoarc; b=NvJhQf1GeHV8eymFgUH0D4PnQ9H8OREwYISzhuPmG9pYHrjYCF8jDhQrRZ+bHlIPuFUcurPJ8wCr32UGawNj0FzZjcj4qNVIdiFg/B9MfePWCF/vKUsSESn80SOv9sk13zy/5xjVbK4hZllWlfz54otevAT7zIPznrw9LjJONF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772107092; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pu3ONN1y8CnzVPPPqwVx01znDwKu8x6AESEnaYZMJ9s=; b=ZFjmiwb2TenFrtmhE4TWE4oqYwB9PPeR7zUariY01qoVR/ecD+YwIIOJwyCK8A9Va35CyhFwVqt8Ov/5PCvsXvED8yD5UD+qxvt0yXOxLkrUn374xaYMXUW7FB78JSdK8jxBFZw5HALCRhO4VStKWL/siBZVEzi7mWwCLva9nsU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1772107092157676.8700755316796; Thu, 26 Feb 2026 03:58:12 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1241586.1542613 (Exim 4.92) (envelope-from ) id 1vva0D-0005Ky-Ap; Thu, 26 Feb 2026 11:57:57 +0000 Received: by outflank-mailman (output) from mailman id 1241586.1542613; Thu, 26 Feb 2026 11:57:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vva0D-0005Kr-8I; Thu, 26 Feb 2026 11:57:57 +0000 Received: by outflank-mailman (input) for mailman id 1241586; Thu, 26 Feb 2026 11:57:56 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vvZuD-0006EH-2R for xen-devel@lists.xenproject.org; Thu, 26 Feb 2026 11:51:45 +0000 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [2a00:1450:4864:20::329]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 84fdef89-1309-11f1-9ccf-f158ae23cfc8; Thu, 26 Feb 2026 12:51:43 +0100 (CET) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-483770e0b25so7372105e9.0 for ; Thu, 26 Feb 2026 03:51:43 -0800 (PST) Received: from fedora (user-109-243-67-101.play-internet.pl. [109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd68826asm220079295e9.0.2026.02.26.03.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 03:51:42 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 84fdef89-1309-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772106702; x=1772711502; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pu3ONN1y8CnzVPPPqwVx01znDwKu8x6AESEnaYZMJ9s=; b=Q55DSSMxraHRy7VcTNID2XI8TY6x676cdTOzNAOP5OHe7mZAsfjVKhIq2qvfXQWnON IM/KYhvuy2xXxl4ON4o3Kj2Rekkw3cwtDSGZ6oNg7F8XcWiPAbmQA3yBarrsjR1GKq7W su0EnUalICO7LpgpHyPrVK8gUaq/5S+5yPMxwmM3H4395UVtpUdbrs7IrRTMvbC0YYdY EYUR/r9DDAjE/tcIkC7kovuc4zOx9o/z/Czt7uT7PkFQZm6SzSDw/dfzFvsH5WlfQQbB A3KBcSxg59aybm3WBt3g8jMJGzkOc+YRpHRCfFmYb/CI7r63BW4MYVR8I++fn8ge7OcH oZJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772106702; x=1772711502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=pu3ONN1y8CnzVPPPqwVx01znDwKu8x6AESEnaYZMJ9s=; b=qBOeUKxZpjHBGYzGFQD515EAN6sSXznSpotaausb0b+HuHdnTcgUwFnOJe5+05a5hK d8x4+pUaAmJ8+qTzAJE3L5oQzt6U0aNqaoQmurrjtwdxFwO+kUQs1TC5Zmmw47Eo0qGM +9RZs05KobGecxNPrWDSdqO0YMeS6vRKa70pYzRMxg1vU4uTYg3RBaL/zJpmqfv8ZkKz jMeDguVkKpCkktxZio5YfIQanr0wCjkBYGltb1bnLacBb9jDUhtuIfBLBt6zXhLGtL5Z 4Gjb+KZLEC2UUuKDdMDVCypgGEdYifqBMNt+fvbC/QBIviT2Y7wUlYzXN7oyRznXtLKI VOLA== X-Gm-Message-State: AOJu0Yy7tYO8OsoN/W0GPJX6l4QA+GRBj7hHZdrr8MkyyT8FeK/ABrRj TsaPlFKgUcL6FnxKiFV8XJr1ljDgBJm6hEKcSa+wqOgrqH4ZQxqjjDBXyXmclg== X-Gm-Gg: ATEYQzyc4ywa/5ZfVE704iMmmtv/n27V7JSxwh0fXxcYbSfr3do9KvZvEis2NKmjZcj l8zuynT5haoGWNSUOwngHujeILq1oPDLG1CsfwEZfo2vG+PwL+mpRoKk/VfOGAm5HO8UDwJNFW8 +PU+T7ZlzLxEb1Zn5e/p9O/jkn0Wq3DeNW/dPBFOxpAEncmUVdR1Ly9DpLktOVVolyE2FSGG99v NfnrzKAzN1WkxnTqJVxEiDiMRkUcD5ARCA7HnQ6PMpvIdr6KTZ1sfm61CU7D3PEauyzCt1rlmGC Y/jbmj5RsNVtkjcg9GjV3pdD7W0JRGMZl/tKkymyxhd2iwyhEUZc6x0GQxGx55mBgodzhqA46dd fBGOivSxJvnBiHlYeAKJDE9PBnUqxWnLln5KiRTzS+nHJpdhSM1f+qiM6R/SaEZR3KXWz2E/M6a TBNOPGn7yE9dJlC5md3P93atDShloL4h/GdZOKwdPxf2hhTRzRTxMmzP4mkDcMBF9ZZat+yw== X-Received: by 2002:a05:600c:8183:b0:477:9dc1:b706 with SMTP id 5b1f17b1804b1-483a962e3d4mr287053045e9.19.1772106702486; Thu, 26 Feb 2026 03:51:42 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 14/14] xen/riscv: implement sync_vcpu_execstate() Date: Thu, 26 Feb 2026 12:51:14 +0100 Message-ID: <9572c925ccbed3fa391b3a0c9d8eddad87c49ab7.1772016457.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772107098711158500 Content-Type: text/plain; charset="utf-8" The scheduler may call this function to force synchronization of given vCPU's state. RISC-V does not support lazy context switching, so nothing is done in sync_vcpu_execstate() and sync_local_execstate(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v6: - Nothing changed. Only rebase. --- Changes in v5: - It was something wrong with prev. rebase. Drop stubs for sync_local_execstate() and sync_vcpu_execstate() in this patch. --- Changes in v4: - Drop footer as [PATCH] sched: move vCPU exec state barriers is merged to upstream/staging. - Add Acked-by: Jan Beulich . --- Changes in v3: - Align sync_vcpu_execstate() with patch: [PATCH] sched: move vCPU exec state barriers --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 10 ++++++++++ xen/arch/riscv/stubs.c | 10 ---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index fda8cff90f6a..6e852d3b71c2 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -279,6 +279,16 @@ void vcpu_kick(struct vcpu *v) } } =20 +void sync_local_execstate(void) +{ + /* Nothing to do -- no lazy switching */ +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + /* Nothing to do -- no lazy switching */ +} + static void __init __maybe_unused build_assertions(void) { /* diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 2f3a0ce76af9..acbb5b9123ea 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -91,16 +91,6 @@ void continue_running(struct vcpu *same) BUG_ON("unimplemented"); } =20 -void sync_local_execstate(void) -{ - BUG_ON("unimplemented"); -} - -void sync_vcpu_execstate(struct vcpu *v) -{ - BUG_ON("unimplemented"); -} - void startup_cpu_idle_loop(void) { BUG_ON("unimplemented"); --=20 2.53.0